Standard cell layout generation method and apparatus, electronic device, and storage medium

Abstract

The application provides a standard cell layout generation method and device, electronic equipment and storage medium, and relates to the technical field of computers. The standard cell layout generation method comprises the following steps: based on the hardware description language and the driving capability of a to-be-drawn standard cell, at least one subcircuit is extracted from a preset subcircuit library to obtain a corresponding target subcircuit combination of the to-be-drawn standard cell; wherein the subcircuit library comprises a plurality of subcircuits, each subcircuit is a circuit composed of at least one transistor, and any standard cell can be spliced to obtain at least one subcircuit in the subcircuit library; the driving capability of the target subcircuit combination is the same as the driving capability of the to-be-drawn standard cell, and the circuit structure of the target subcircuit combination is the same as the circuit structure described in the hardware description language; and based on the target subcircuit combination, the layout of the to-be-drawn standard cell is obtained.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a method, apparatus, electronic device, and storage medium for generating a standard cell layout. Background Technology

[0002] In current industrial integrated circuit design, standard cell circuits, consisting of a certain number of transistors, are considered the smallest building blocks of very large-scale integrated circuit (VLSI) designs. These standard cells include various basic units such as inverters, AND gates, registers, selectors, and full adders. When drawing integrated circuit layouts, the layouts of various standard cells from a pre-defined standard cell library can be directly combined to obtain the integrated circuit layout.

[0003] To ensure the overall performance of integrated circuits, a suitable standard cell physical layout framework is typically selected. The integrated circuit layout is then obtained by combining the layouts of standard cells within this framework. However, the layouts of standard cells under different standard cell physical layout frameworks all require manual drawing, resulting in low efficiency in generating standard cell layouts. Summary of the Invention

[0004] This application provides a standard cell layout generation method, apparatus, electronic device, and storage medium to improve the efficiency of standard cell layout generation.

[0005] In a first aspect, this application provides a method for generating a standard cell layout, comprising: extracting at least one sub-circuit from a preset sub-circuit library based on the hardware description language and driving capability of the standard cell to be drawn, thereby obtaining a target sub-circuit combination corresponding to the standard cell to be drawn; wherein, the sub-circuit library includes multiple sub-circuits, each sub-circuit being a circuit composed of at least one transistor, and any standard cell can be obtained by splicing together at least one sub-circuit from the sub-circuit library; the driving capability of the target sub-circuit combination is the same as the driving capability of the standard cell to be drawn, and the circuit structure of the target sub-circuit combination is the same as the circuit structure described by the hardware description language; and obtaining the layout of the standard cell to be drawn based on the target sub-circuit combination.

[0006] In this embodiment, a pre-defined subcircuit library is used, allowing the generation of a target subcircuit combination corresponding to the standard cell to be drawn to be obtained based on the total subcircuit combinations in the library. Furthermore, the layout of the standard cell to be drawn is obtained based on the target subcircuit combination. This eliminates the need for manual drawing of the standard cell layout, thereby improving the efficiency of standard cell layout generation.

[0007] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, each sub-circuit in the sub-circuit library has at least one circuit structure netlist file, and multiple circuit structure netlist files corresponding to the same sub-circuit have different driving capabilities; the target sub-circuit combination includes: the sub-circuit it has and the circuit structure netlist file of the entire target sub-circuit combination; based on the hardware description language and driving capability of the standard unit to be drawn, at least one sub-circuit is extracted from the preset sub-circuit library to obtain the target sub-circuit combination corresponding to the standard unit to be drawn, including: extracting at least one sub-circuit from the sub-circuit library that can be combined to obtain the circuit structure of the standard unit to be drawn, and obtaining the sub-circuit it has; obtaining a target circuit structure netlist file that matches the driving capability of the standard unit to be drawn from the circuit structure netlist file of the at least one sub-circuit; merging the target circuit structure netlist files of the at least one sub-circuit, and adding the connection relationship between the at least one sub-circuit according to the circuit structure described by the hardware description language of the standard unit to be drawn, to obtain the circuit structure netlist file of the target sub-circuit combination.

[0008] In this embodiment, since the same subcircuit in the subcircuit library can have multiple circuit structure netlist files corresponding to different driving capabilities, even the same combination of subcircuits can have different driving capabilities. Therefore, this solution can generate standard cells with different driving capabilities, improving its applicability. Furthermore, by first determining multiple voltage circuits corresponding to the circuit structure of the standard cell to be drawn, the hardware description language of the standard cell can be satisfied; then, the circuit structure netlist file of the subcircuit is determined, so that the driving capability of the final target subcircuit combination matches the driving capability of the standard cell to be drawn. Therefore, the final target subcircuit combination is the circuit of the standard cell to be drawn, thus ensuring that the physical layout obtained subsequently based on this target subcircuit combination corresponds to the standard cell to be drawn, improving the accuracy of this solution.

[0009] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, each sub-circuit includes multiple physical layouts, and the multiple physical layouts are generated based on the circuit structure netlist files of each sub-circuit. For each circuit structure netlist file, N physical layouts corresponding to N standard cell layout frames are generated, where N is a positive integer. Obtaining the layout of the standard cell to be drawn based on the target sub-circuit combination includes: acquiring the target physical layouts of each sub-circuit in the target sub-circuit combination; the target physical layout is a physical layout generated based on a target circuit structure netlist file that matches the driving capability of the standard cell to be drawn; and stitching the target physical layouts of each sub-circuit into the layout of the standard cell to be drawn according to the connection relationships between the sub-circuits specified in the circuit structure netlist file of the target sub-circuit combination.

[0010] In this embodiment of the application, after determining the target sub-circuit combination, the target physical layout of each voltage circuit can be spliced ​​together according to the connection relationship between the sub-circuits specified in the circuit structure netlist file of the target sub-circuit combination to obtain the layout of the standard cell to be drawn. There is no need to manually draw the layout of the standard cell, thereby improving the generation efficiency of the standard cell layout.

[0011] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, N is a constant greater than or equal to 2; according to the connection relationship between subcircuits specified in the circuit structure netlist file of the target subcircuit combination, the target physical layout of each subcircuit is spliced ​​into the layout of the standard cell to be drawn, including: for the N standard cell layout frames: the target physical layouts of each subcircuit corresponding to the same standard cell layout frame are spliced ​​according to the connection relationship between subcircuits specified in the circuit structure netlist file of the target subcircuit combination to obtain N layouts of the standard cell to be drawn.

[0012] In this embodiment, since each circuit structure netlist file of the sub-circuit corresponds to N physical layouts, this solution can obtain the layout of the standard cell to be drawn under N different standard cell layout frameworks, eliminating the need for manual drawing of the standard cell layout for each standard cell layout framework, thus improving the generation efficiency of the standard cell layout.

[0013] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, after obtaining N layouts of the standard unit to be drawn, the method further includes: selecting, based on the feature data of each of the N layouts, the target layout whose feature data best matches the requirements of the standard unit to be drawn as the final layout of the standard unit to be drawn; wherein, the feature data characterizes the circuit characteristics of the entire circuit corresponding to the layout.

[0014] In this embodiment of the application, due to the circuit characteristics of the entire circuit corresponding to the feature data standard layout, the layout that best matches the requirements of the standard unit to be drawn is taken as the final layout of the standard unit to be drawn, so that the final layout can better meet the actual usage requirements of the standard unit to be drawn.

[0015] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, after obtaining N layouts of the standard unit to be drawn, the method further includes: for each of the N layouts, calculating the feature data of the layout based on the feature data of each of the target physical layouts that make up the layout; storing each of the N layouts and the feature data corresponding to each layout in a preset standard unit library.

[0016] In this embodiment, the feature data of the layout can be calculated using the feature data of the target physical layout, thereby reducing the difficulty of calculating the feature data of the standard unit to be drawn. Simultaneously, storing each layout and its corresponding feature data in a preset standard unit library facilitates direct subsequent retrieval of the layout and feature data of the standard unit to be drawn, improving the user experience.

[0017] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, the standard unit library may also include a hardware description language and circuit structure diagram for each standard unit.

[0018] In this embodiment, since the standard cell library also includes the hardware description language and circuit structure diagram of each standard cell, the standard cell library obtained by this solution can be applied to more scenarios, thereby improving the applicability of this solution.

[0019] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, each sub-circuit includes multiple physical layouts, and the multiple physical layouts are generated based on the netlist files of each circuit structure of the sub-circuit. For each circuit structure netlist file, N physical layouts corresponding to N standard cell layout frames are generated, where N is a positive integer. Based on the target sub-circuit combination, obtaining the layout of the standard cell to be drawn includes: for each standard cell layout frame, determining the feature data of the target sub-circuit combination under that standard cell layout frame based on the feature data of each sub-circuit possessed by the target sub-circuit combination and the frame parameters of that standard cell layout frame. The feature data of the sub-circuit characterizes the circuit characteristics of the sub-circuit; the feature data of the target sub-circuit combination characterizes the overall circuit characteristics of the target sub-circuit combination; from the feature data of the target sub-circuit combination under the N standard cell layout frameworks, the target feature data that best meets the requirements of the standard cell to be drawn is selected; the target physical layout of each sub-circuit corresponding to the target standard cell layout framework is spliced ​​according to the connection relationship between the sub-circuit as specified in the circuit structure netlist file of the target sub-circuit combination to obtain the layout of the standard cell to be drawn; wherein, the target standard cell layout framework is the standard cell layout framework corresponding to the target feature data.

[0020] In this embodiment, by determining the feature data of the target subcircuit combination under each standard cell layout framework, the target feature data that best meets the requirements of the standard cell to be drawn can be determined. The standard cell layout framework corresponding to the target feature data is taken as the target standard cell layout framework, and the layout of the target standard cell to be drawn under the target standard cell layout framework is taken as the layout of the standard cell to be drawn. Thus, only one layout stitching is required to obtain the layout of the standard cell to be drawn, improving the efficiency of obtaining the standard cell layout.

[0021] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, the feature data includes at least one of the following: layout area occupancy, number of virtual gates, parasitic resistance of each node in the subcircuit, parasitic capacitance, delay time corresponding to the gate node to the subcircuit port, toggle time corresponding to the gate node to the subcircuit port, dynamic power consumption corresponding to the gate node to the subcircuit port, and static power consumption corresponding to the gate node state.

[0022] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, obtaining the layout of the standard cell to be drawn based on the target sub-circuit combination includes: generating the layout of the standard cell to be drawn based on the circuit structure netlist file of the target sub-circuit combination using an automatic layout and routing tool.

[0023] In this embodiment, the layout of the standard cell to be drawn is generated directly from the layout automatic placement and routing tool, eliminating the need for manual drawing and improving the efficiency of obtaining the standard cell layout.

[0024] Secondly, this application provides a method for establishing a standard cell library, comprising: obtaining a layout of standard cells to be drawn according to the method described in the first aspect and / or any possible implementation of the first aspect; and constructing a standard cell library based on the obtained layout of each standard cell to be drawn and the hardware description language of each standard cell to be drawn.

[0025] In this embodiment of the application, the standard cell layout generation method eliminates the need for manual drawing of standard cell layouts, thereby improving the generation efficiency of standard cell layouts and enabling the construction of a standard cell library conveniently and quickly.

[0026] In conjunction with the technical solution provided in the second aspect above, in some possible implementations, the subcircuit library further includes feature data of each physical layout of the subcircuit. Based on the obtained layout of each standard unit to be drawn and the hardware description language of each standard unit to be drawn, a standard unit library is constructed, including: for the layout of each standard unit to be drawn, calculating the feature data of the layout based on the feature data of each of the target physical layouts that make up the layout; and constructing the standard unit library based on the obtained layout and feature data of each standard unit to be drawn, and the hardware description language of each standard unit to be drawn.

[0027] In this embodiment, the feature data of the layout is calculated using the feature data of the target physical layout, reducing the difficulty of calculating the feature data of the standard cells to be drawn. Each layout and its corresponding feature data are stored in a preset standard cell library, facilitating direct retrieval of the layout and feature data of the standard cells to be drawn later, thus improving the user experience.

[0028] In conjunction with the technical solution provided in the second aspect above, in some possible implementations, before constructing the standard cell library based on the obtained layout of each standard cell to be drawn and the hardware description language of each standard cell to be drawn, the method further includes: obtaining the circuit structure diagram of each standard cell to be drawn; correspondingly, constructing the standard cell library based on the obtained layout of each standard cell to be drawn and the hardware description language of each standard cell to be drawn includes: constructing the standard cell library based on the obtained layout and feature data of each standard cell to be drawn, as well as the hardware description language and circuit structure diagram of each standard cell to be drawn.

[0029] In this embodiment, since the constructed standard cell library includes the hardware description language and circuit structure diagram of the standard cell to be drawn, the standard cell library obtained by this solution can be applied to more scenarios, thereby improving the applicability of this solution.

[0030] Thirdly, this application provides a subcircuit library, comprising: multiple subcircuits, each subcircuit having at least one circuit structure netlist file, and the multiple circuit structure netlist files corresponding to the same subcircuit having different driving capabilities; the same circuit structure netlist file corresponds to a physical layout under at least one standard cell layout framework; wherein, each subcircuit is a circuit composed of at least one transistor, and any standard cell can be obtained by splicing together at least one subcircuit in the subcircuit library.

[0031] In conjunction with the technical solution provided in the second aspect above, in some possible implementations, the subcircuit library also includes feature data for each physical layout.

[0032] In conjunction with the technical solution provided in the second aspect above, in some possible implementations, the multiple voltage circuits in the subcircuit library are divided into an N-type transistor subcircuit library and a P-type transistor subcircuit library according to the transistor type included in the subcircuit; wherein, each subcircuit included in the N-type transistor subcircuit library includes only N-type transistors, and each subcircuit included in the P-type transistor subcircuit library includes only P-type transistors.

[0033] In conjunction with the technical solution provided in the second aspect above, in some possible implementations, the subcircuit library also includes a circuit structure diagram of each subcircuit.

[0034] Fourthly, this application provides a standard cell layout generation apparatus, comprising: a first processing module and a second processing module; the first processing module is used to extract at least one sub-circuit from a preset sub-circuit library based on the hardware description language and driving capability of the standard cell to be drawn, to obtain a target sub-circuit combination corresponding to the standard cell to be drawn; wherein, the sub-circuit library includes multiple sub-circuits, each sub-circuit being a circuit composed of at least one transistor, and any standard cell can be obtained by splicing together at least one sub-circuit in the sub-circuit library; the driving capability of the target sub-circuit combination is the same as the driving capability of the standard cell to be drawn, and the circuit structure of the target sub-circuit combination is the same as the circuit structure described by the hardware description language; the second processing module is used to obtain the layout of the standard cell to be drawn based on the target sub-circuit combination.

[0035] Fifthly, this application provides a standard cell library building apparatus, comprising: an acquisition module, configured to obtain a layout of a standard cell to be drawn according to the method described in the first aspect and / or any possible implementation of the first aspect; and a third processing module, configured to construct a standard cell library based on the obtained layout of each standard cell to be drawn and the hardware description language of each standard cell to be drawn.

[0036] In a sixth aspect, this application provides an electronic device, comprising: a memory and a processor, the memory and the processor being connected; the memory being used to store a program; the processor being used to invoke the program stored in the memory to execute the method described in the first aspect and / or in combination with any possible implementation of the first aspect; and / or to execute the method described in the second aspect and / or in combination with any possible implementation of the second aspect.

[0037] In a seventh aspect, this application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a computer, performs the method described in the first aspect and / or in combination with any possible implementation of the first aspect, and / or performs the method described in the second aspect and / or in combination with any possible implementation of the second aspect. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic flowchart illustrating a standard cell layout generation method according to an embodiment of this application;

[0040] Figure 2 This is a schematic diagram illustrating a sub-circuit library according to an embodiment of this application;

[0041] Figure 3 This application illustrates a sub-circuit structure table in an embodiment.

[0042] Figure 4 This is a schematic flowchart illustrating a standard cell layout generation method according to an embodiment of this application;

[0043] Figure 5 This is a flowchart illustrating a method for establishing a standard cell library according to an embodiment of this application;

[0044] Figure 6This is a schematic diagram illustrating the relationship between a sub-circuit library and a standard cell library, as shown in an embodiment of this application.

[0045] Figure 7 This is a schematic diagram illustrating an embodiment of the present application for generating a standard cell library based on a subcircuit library;

[0046] Figure 8 This is a structural block diagram of a standard cell layout generation apparatus shown in an embodiment of this application;

[0047] Figure 9 This is a structural block diagram illustrating a standard unit library creation device according to an embodiment of this application;

[0048] Figure 10 This is a structural block diagram of an electronic device shown in an embodiment of this application. Detailed Implementation

[0049] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0050] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0051] The technical solution of this application will now be described in detail with reference to the accompanying drawings.

[0052] Please see Figure 1 , Figure 1 This is a flowchart illustrating a standard cell layout generation method according to an embodiment of this application. The following will be combined with... Figure 1 The steps involved are explained.

[0053] S100: Based on the hardware description language and driving capability of the standard cell to be drawn, extract at least one sub-circuit from the preset sub-circuit library to obtain the target sub-circuit combination corresponding to the standard cell to be drawn.

[0054] The subcircuit library contains multiple subcircuits, each of which is a circuit composed of at least one transistor. Any standard cell can be obtained by splicing together at least one subcircuit from the subcircuit library. The driving capability of the target subcircuit combination is the same as that of the standard cell to be drawn, and the circuit structure of the target subcircuit combination is the same as the circuit structure described by the hardware description language.

[0055] In one implementation, each subcircuit in the subcircuit library has at least one circuit structure netlist file, and the multiple circuit structure netlist files corresponding to the same subcircuit have different driving capabilities; the target subcircuit combination includes: the subcircuit it has and the circuit structure netlist file of the entire target subcircuit combination.

[0056] The driving capability includes various parameters of the transistors that make up the voltage circuit, such as the transistor size and threshold voltage.

[0057] Based on this, the specific method for extracting at least one sub-circuit from a pre-defined sub-circuit library to obtain the target sub-circuit combination corresponding to the standard unit to be drawn, based on the hardware description language and driving capability of the standard unit to be drawn, can be as follows: First, extract at least one sub-circuit that can be combined to obtain the circuit structure of the standard unit to be drawn from the sub-circuit library to obtain the sub-circuit of the target sub-circuit combination; then, obtain the target circuit structure netlist file that matches the driving capability of the standard unit to be drawn from the circuit structure netlist file of at least one sub-circuit; finally, merge the target circuit structure netlist files of at least one sub-circuit, and add the connection relationship between at least one sub-circuit according to the circuit structure described by the hardware description language of the standard unit to be drawn to obtain the circuit structure netlist file of the target sub-circuit combination.

[0058] Because a single subcircuit in the subcircuit library can have multiple netlist files corresponding to different driving capabilities, even combinations of the same subcircuit can possess different driving capabilities. Therefore, this approach can generate standard cells with varying driving capabilities, expanding its applicability. Furthermore, by first determining multiple voltage circuits corresponding to the circuit structure of the standard cell to be drawn, the hardware description language of the standard cell can be satisfied. Then, the netlist file of the subcircuit's circuit structure is determined, ensuring that the driving capability of the final target subcircuit combination matches the driving capability of the standard cell to be drawn. Thus, the final target subcircuit combination is the circuit of the standard cell to be drawn, ensuring that the physical layout obtained subsequently based on this target subcircuit combination corresponds to the standard cell, improving the accuracy of this approach.

[0059] Optionally, at least one subcircuit that can be combined to obtain the circuit structure of the standard unit to be drawn can be extracted from the subcircuit library. The way to obtain the subcircuit of the target subcircuit combination can be: randomly combine the various subcircuit in the subcircuit library to obtain multiple initial subcircuit combinations, and then select the subcircuit combination whose number of transistors is consistent with the number of transistors included in the hardware description language and whose transistor connection method is consistent with the hardware description language.

[0060] Among the sub-circuit combinations obtained in this way, there may be multiple voltage circuit combinations that satisfy the hardware description language. Optionally, one sub-circuit combination can be selected as the target sub-circuit combination from these multiple sub-circuit combinations that satisfy the hardware description language.

[0061] For example, a sub-circuit combination can be randomly selected from the multiple sub-circuit combinations that satisfy the hardware description language as the target sub-circuit combination; or, the sub-circuit combination with the fewest sub-circuits can be selected as the target sub-circuit combination.

[0062] Alternatively, the circuit structure described in the hardware description language can be segmented first, and then the sub-circuit library can be matched with the multiple circuit structures obtained from the segmentation to determine the sub-circuit of the target sub-circuit combination.

[0063] There are multiple ways to segment the circuit structure described in the hardware description language. Therefore, for each segmentation method, a matching process can be performed from the sub-circuit library. This approach may result in multiple sub-circuit combinations. Optionally, one sub-circuit combination can be selected as the target sub-circuit combination from these multiple sub-circuit combinations that satisfy the hardware description language.

[0064] For example, a sub-circuit combination can be randomly selected from the multiple sub-circuit combinations that satisfy the hardware description language as the target sub-circuit combination; or, the sub-circuit combination with the fewest sub-circuits can be selected as the target sub-circuit combination.

[0065] Optionally, the specific implementation of obtaining the target circuit structure netlist file that matches the driving capability of the standard cell to be drawn from the circuit structure netlist file of at least one sub-circuit can be as follows: determine the driving capability of each sub-circuit in the target sub-circuit combination according to the driving capability of the standard cell to be drawn, and then determine the target circuit structure netlist file from the multiple circuit structure netlist files corresponding to the sub-circuit according to the driving capability of each sub-circuit.

[0066] Alternatively, obtaining the target circuit structure netlist file matching the driving capability of the standard cell to be drawn from the circuit structure netlist file of at least one sub-circuit can be achieved by: randomly combining the circuit structure netlist files corresponding to each sub-circuit included in the target sub-circuit combination to obtain multiple initial netlist files; then selecting the initial netlist file whose driving capability is the same as that of the standard cell to be drawn from the multiple initial netlist files as the netlist file of the target sub-circuit combination. Accordingly, the circuit structure netlist file of each sub-circuit included in the selected initial netlist file is the target circuit structure netlist file matching the driving capability of the standard cell to be drawn.

[0067] S200: Based on the target subcircuit combination, the layout of the standard cell to be drawn is obtained.

[0068] After obtaining the target subcircuit combination according to the above method, the layout of the standard cell to be drawn can be obtained in the following three ways.

[0069] In the first implementation method, the specific implementation method for obtaining the layout of the standard cell to be drawn based on the target sub-circuit combination can be: the layout of the standard cell to be drawn is generated by the automatic layout and routing tool according to the circuit structure netlist file of the target sub-circuit combination.

[0070] By utilizing existing automatic layout and routing tools that can draw layouts based on netlist files, the layout of standard cells to be drawn can be directly generated according to the circuit structure netlist file of the target subcircuit combination. This eliminates the need for manual drawing, improving the efficiency of obtaining standard cell layouts.

[0071] In the second implementation, each sub-circuit includes multiple physical layouts, which are generated based on the netlist files of each circuit structure of the sub-circuit. For each netlist file, N physical layouts are generated corresponding to N standard cell layout frameworks, where N is a positive integer. The specific method for obtaining the layout of the standard cell to be drawn based on the target sub-circuit combination can be as follows: First, obtain the target physical layouts of each sub-circuit in the target sub-circuit combination; the target physical layouts are physical layouts generated based on the netlist files of the target circuit structure that match the driving capability of the standard cell to be drawn. Then, according to the connection relationships between the sub-circuits specified in the netlist files of the circuit structure of the target sub-circuit combination, the target physical layouts of each sub-circuit are stitched together to form the layout of the standard cell to be drawn.

[0072] The standard cell layout frame can include the standard cell height and its height multiple. Different standard cell layout frames have different standard cell heights and / or height multiples.

[0073] For ease of understanding, this example uses N=2, where the target subcircuit combination includes subcircuit 1, subcircuit 2, and subcircuit 3. Subcircuit 1 corresponds to circuit structure netlist files 11 and 12, subcircuit 2 corresponds to circuit structure netlist files 21 and 22, and subcircuit 3 corresponds to circuit structure netlist files 31 and 32. If the circuit structure netlist files of the target subcircuit combination are constructed based on circuit structure netlist files 11, 21, and 31, then the layout of the standard cells to be drawn is obtained by splicing together the physical layout 11 corresponding to circuit structure netlist file 11, the physical layout 21 corresponding to circuit structure netlist file 21, and the physical layout 31 corresponding to circuit structure netlist file 31. This example is for ease of understanding only and should not be considered a limitation of this application.

[0074] Optionally, the N physical layouts corresponding to the circuit structure netlist file under the N standard cell layout frameworks can be drawn manually, or they can be automatically generated by an automatic layout and routing tool based on the circuit structure netlist file.

[0075] In one implementation, N is a constant greater than or equal to 2. The specific method of stitching the target physical layout of each sub-circuit into the layout of the standard cell to be drawn according to the connection relationship between the sub-circuits specified in the circuit structure netlist file of the target sub-circuit combination can be as follows: For N standard cell layout frames: stitch the target physical layouts of each sub-circuit corresponding to the same standard cell layout frame according to the connection relationship between the sub-circuits specified in the circuit structure netlist file of the target sub-circuit combination to obtain N layouts of the standard cell to be drawn.

[0076] For ease of understanding, with N=2, the circuit structure netlist files for the target sub-circuit combination are constructed based on circuit structure netlist file 1, circuit structure netlist file 2, and circuit structure netlist file 3. Under the first standard cell layout framework, circuit structure netlist file 1 corresponds to physical layout 11, circuit structure netlist file 2 corresponds to physical layout 21, and circuit structure netlist file 3 corresponds to physical layout 31. Under the second standard cell layout framework, circuit structure netlist file 1 corresponds to physical layout 12, circuit structure netlist file 2 corresponds to physical layout 22, and circuit structure netlist file 3 corresponds to physical layout 32.

[0077] Physical layouts 11, 21, and 31 are then combined to obtain a layout of the standard unit to be drawn within the first type of standard unit layout framework. Similarly, physical layouts 12, 22, and 32 are combined to obtain a layout of the standard unit to be drawn within the second type of standard unit layout framework. This results in two layouts for the standard unit to be drawn. This example is for illustrative purposes only and should not be construed as limiting the scope of this application.

[0078] In one implementation, after obtaining N layouts of the standard unit to be drawn, one layout can be selected from the N layouts as the final layout of the standard unit to be drawn.

[0079] Optionally, a layout can be randomly selected from N layouts of the standard unit to be drawn as the final layout of the standard unit to be drawn.

[0080] Alternatively, based on the feature data of each of the N layouts, the target layout whose feature data best matches the requirements of the standard cell to be drawn can be selected as the final layout of the standard cell to be drawn. Here, the feature data characterizes the circuit characteristics of the entire circuit corresponding to the layout.

[0081] The feature data of each of the N layouts of the standard unit to be drawn can be obtained from each layout, or it can be calculated from the feature data of all the target physical layouts corresponding to each layout. The feature data corresponding to the target physical layouts are obtained in advance based on the target physical layouts.

[0082] The specific methods for obtaining the feature data corresponding to the layout based on the layout, and the specific methods for calculating the feature data of the large circuit based on the feature data of multiple small circuits that make up the large circuit, are well known to those skilled in the art and will not be elaborated here for the sake of brevity.

[0083] Optionally, the feature data may include at least one of the following: layout area occupancy, number of virtual gates, parasitic resistance of each node in the subcircuit, parasitic capacitance, delay time corresponding to the gate node to the subcircuit port, toggle time corresponding to the gate node to the subcircuit port, dynamic power consumption corresponding to the gate node to the subcircuit port, and static power consumption corresponding to the gate node state.

[0084] Correspondingly, when selecting the target layout whose feature data best matches the requirements of the standard unit to be drawn from N layouts as the final layout of the standard unit to be drawn, the feature data can be one or more of the above-mentioned features, and there are no restrictions on them here.

[0085] In the third implementation, each subcircuit includes multiple physical layouts, which are generated based on the netlist files of each circuit structure of the subcircuit. For each circuit structure netlist file, N physical layouts are generated corresponding to N standard cell layout frames, where N is a positive integer. In this case, the specific method for obtaining the layout of the standard cell to be drawn based on the target subcircuit combination can be as follows: First, for each standard cell layout frame, based on the feature data of each subcircuit in the target subcircuit combination and the frame parameters of that standard cell layout frame, the feature data of the target subcircuit combination under that standard cell layout frame is determined; the feature data of the subcircuit characterizes the circuit characteristics of the subcircuit; the feature data of the target subcircuit combination characterizes the overall circuit characteristics of the target subcircuit combination. Then, the target feature data that best matches the requirements of the standard cell to be drawn is selected from the feature data of the target subcircuit combination under the N standard cell layout frames. Finally, the target physical layouts of each subcircuit corresponding to the target standard cell layout frame are spliced ​​together according to the connection relationships between the subcircuit in the circuit structure netlist file of the target subcircuit combination to obtain the layout of the standard cell to be drawn. Among them, the target standard unit layout framework is the standard unit layout framework corresponding to the target feature data.

[0086] For ease of understanding, with N=2, the circuit structure netlist files for the target sub-circuit combination are constructed based on circuit structure netlist file 1, circuit structure netlist file 2, and circuit structure netlist file 3. Under the first standard cell layout framework, circuit structure netlist file 1 corresponds to physical layout 11, circuit structure netlist file 2 corresponds to physical layout 21, and circuit structure netlist file 3 corresponds to physical layout 31. Under the second standard cell layout framework, circuit structure netlist file 1 corresponds to physical layout 12, circuit structure netlist file 2 corresponds to physical layout 22, and circuit structure netlist file 3 corresponds to physical layout 32.

[0087] Based on the characteristic data corresponding to physical layouts 11, 21, and 31, the characteristic data of the standard cell to be drawn under the first standard cell layout framework are calculated. Similarly, based on the characteristic data corresponding to physical layouts 12, 22, and 32, the characteristic data of the standard cell to be drawn under the second standard cell layout framework are calculated. If the characteristic data of the standard cell to be drawn under the second standard cell layout framework better matches the target characteristic data required for the standard cell to be drawn compared to the characteristic data of the standard cell to be drawn under the first standard cell layout framework, then the second standard cell layout framework is determined as the target standard cell layout framework. Therefore, physical layouts 12, 22, and 32 are spliced ​​together according to the connection relationships between subcircuits specified in the circuit structure netlist file of the target subcircuit combination to obtain the layout of the standard cell to be drawn. This example is only for ease of understanding and should not be construed as a limitation of this application.

[0088] In one implementation, after obtaining N layouts of the standard cells to be drawn, feature data of each layout can be calculated based on the feature data of all target physical layouts that make up that layout. Each of the N layouts, along with its corresponding feature data, is then stored in a preset standard cell library.

[0089] The feature data of the layout can be calculated using the feature data of the target physical layout, thus reducing the difficulty of calculating the feature data of the standard cells to be drawn. Simultaneously, storing each layout and its corresponding feature data in a pre-defined standard cell library facilitates direct retrieval of the layout and feature data of the standard cells to be drawn later, improving the user experience.

[0090] Optionally, the standard cell library also includes a hardware description language and circuit diagram for each standard cell.

[0091] Since the standard cell library also includes the hardware description language and circuit diagram for each standard cell, the standard cell library obtained by this solution can be applied to more scenarios, thus improving the applicability of this solution.

[0092] In one implementation, the subcircuit library can be constructed as follows: First, the circuit structure of each subcircuit is obtained; then, based on each circuit structure, multiple circuit structure netlist files are generated, wherein different circuit structure netlist files corresponding to the same circuit structure have different driving capabilities. Next, for each circuit structure netlist file, the physical layout of the corresponding subcircuit is obtained under each standard cell layout framework; wherein the standard cell layout framework represents different process parameters. And for each physical layout, feature data corresponding to that physical layout is generated.

[0093] The subcircuit library obtained using this method includes four main categories of data: subcircuit structure, circuit structure netlist file, physical layout, and feature data. For ease of understanding, as follows... Figure 2 As shown.

[0094] Optionally, the subcircuit circuit structure can be divided into two categories based on the type of transistor: P-transistor circuit structure and N-transistor circuit structure. For easier understanding, please refer to [link to relevant documentation]. Figure 3 , Figure 3 An implementation of a P-transistor circuit structure library and an N-transistor circuit structure library is shown. Figure 3 The subcircuit structure library shown is only one specific implementation shown in this application and should not be regarded as a limitation of this application.

[0095] Optionally, the physical layouts in the subcircuit library can be classified according to the standard cell layout framework, and physical layouts belonging to the same standard cell layout framework can be stored in the same dataset. Alternatively, multiple physical layouts belonging to the same subcircuit can be stored in the same dataset.

[0096] Optionally, for each circuit structure netlist file, the specific implementation of obtaining the physical layout of the corresponding sub-circuit under each standard cell layout framework can be: manually drawing the physical layout of the circuit structure netlist file under each standard cell layout framework; or, automatically generating the layout of the standard cells to be drawn according to the circuit structure netlist file using a layout placement and routing tool.

[0097] Optionally, the subcircuit library may also include a layout framework file, as well as a parasitic parameter file and a binary layout information file corresponding to each physical layout. The layout framework file, parasitic parameter file, and binary layout information file can all be obtained from the physical layout. Furthermore, the specific methods and principles for obtaining the layout framework file, parasitic parameter file, and binary layout information file from the physical layout are well known to those skilled in the art and will not be elaborated upon here for the sake of brevity.

[0098] Optionally, after obtaining the physical layout of the circuit structure netlist file under each standard cell layout framework, functional verification can be performed on each physical layout to determine whether the physical layout can be used normally.

[0099] Optionally, after obtaining the physical layout of the circuit structure netlist file under each standard cell layout framework, each physical layout can be optimized. The physical layout can be iterated according to the set optimization requirements until the final physical layout meets the set optimization requirements.

[0100] The type of optimization requirement can be one or more of the feature data mentioned above; there are no restrictions on the specific type of optimization requirement here.

[0101] The specific methods for optimizing the physical layout are well known to those skilled in the art, and will not be elaborated here for the sake of brevity.

[0102] To better understand the standard cell layout generation method described above, please refer to [link / reference]. Figure 4 , Figure 4 This is a flowchart illustrating a standard cell layout generation method shown in this application.

[0103] like Figure 4 As shown, at least one subcircuit that can be combined to obtain the circuit structure of the standard unit to be drawn is first extracted from the subcircuit library, and the subcircuit of the target subcircuit combination is obtained.

[0104] Then, from the circuit structure netlist file of at least one subcircuit, obtain the target circuit structure netlist file that matches the driving capability of the standard cell to be drawn.

[0105] Then, the target circuit structure netlist files of at least one sub-circuit are merged, and the connection relationships between at least one sub-circuit are added according to the circuit structure described by the hardware description language of the standard cell to be drawn, so as to obtain the circuit structure netlist file of the target sub-circuit combination.

[0106] Then obtain the target physical layout of each sub-circuit of the target sub-circuit combination.

[0107] Finally, for the N standard cell layout frameworks: the target physical layouts corresponding to the same standard cell layout framework in each sub-circuit are spliced ​​together according to the connection relationship between sub-circuits specified in the circuit structure netlist file of the target sub-circuit combination, to obtain N layouts of the standard cells to be drawn.

[0108] For each of the N layouts, the feature data of that layout is calculated based on the feature data of each of the target physical layouts that make up that layout.

[0109] Finally, based on the feature data of each of the N layouts, the target layout whose feature data best matches the requirements of the standard unit to be drawn is selected as the final layout of the standard unit to be drawn.

[0110] Based on the same technical concept, this application also provides a method for establishing a standard unit library, the process of which is as follows: Figure 5 As shown.

[0111] S300: Obtain the layout of the standard cells to be drawn.

[0112] The layout of the standard cell to be drawn is obtained through the aforementioned standard cell layout generation method. The specific method of obtaining the layout of the standard cell to be drawn through the aforementioned standard cell layout generation method has been clearly described above, and will not be repeated here for the sake of brevity.

[0113] S400: Based on the layout of each standard cell to be drawn and the hardware description language of each standard cell to be drawn, a standard cell library is constructed.

[0114] This can be achieved by associating the layout and hardware description language of the same standard cell to be drawn in the standard cell library; alternatively, by tagging the layout and hardware description language of the same standard cell to be drawn in the standard cell library with a corresponding label, and different standard cells to be drawn having different labels; or alternatively, by storing the layout and hardware description language of the same standard cell to be drawn in the standard cell library in the same folder, with each standard cell to be drawn corresponding to its own folder. These examples are for illustrative purposes only and should not be construed as limiting this application.

[0115] In one implementation, the subcircuit library further includes feature data for each physical layout of the subcircuit. Based on the obtained layout of each standard cell to be drawn and the hardware description language of each standard cell, the specific method for constructing the standard cell library can be as follows: First, for each standard cell layout to be drawn, feature data of the layout is calculated based on the feature data of all target physical layouts constituting that layout. Then, based on the obtained layout and feature data of each standard cell to be drawn, and the hardware description language of each standard cell to be drawn, the standard cell library is constructed.

[0116] The feature data of the layout is calculated by using the feature data of the target physical layout, which reduces the difficulty of calculating the feature data of the standard cells to be drawn. Each layout and its corresponding feature data are stored in a preset standard cell library, which facilitates the direct retrieval of the layout and feature data of the standard cells to be drawn later, thus improving the user experience.

[0117] In one implementation, before constructing the standard cell library based on the layout of each standard cell to be drawn and the hardware description language of each standard cell to be drawn, the circuit structure diagram of each standard cell to be drawn can be obtained first.

[0118] Accordingly, based on the layout of each standard cell to be drawn and the hardware description language of each standard cell to be drawn, the specific process of constructing the standard cell library can be as follows: based on the layout and feature data of each standard cell to be drawn, as well as the hardware description language and circuit structure diagram of each standard cell to be drawn, construct the standard cell library.

[0119] Since the standard cell library obtained by the construction includes the hardware description language and circuit structure diagram of the standard cell to be drawn, the standard cell library obtained by this solution can be applied to more scenarios, thereby improving the applicability of this solution.

[0120] To better understand the relationship between the subcircuit library and the standard cell library, please refer to [link / reference]. Figure 6 .

[0121] like Figure 6 As shown, the hardware description language of the standard cell to be drawn determines the combination relationship of its required subcircuits (including the circuit structure diagram and physical layout of the subcircuits). Then, the circuit structure diagram and physical layout of each standard cell to be drawn can be obtained by combining the circuit structure diagram and physical layout of the subcircuits. The subcircuit structures in the subcircuit library can include typical combinations of P-type transistors and typical combinations of N-type transistors.

[0122] After obtaining the circuit structure diagram and layout of the standard cell, the standard cell library can be obtained based on the circuit structure diagram, physical layout, and hardware description language of the standard cell.

[0123] The method of generating a standard cell library based on a subcircuit library can be represented as follows: Figure 7 As shown. The sub-circuits constituting the standard cell are determined based on the functional and driving capabilities required by the standard cell. Furthermore, the target standard cell layout framework is determined according to the requirements of the standard cell characteristic data. Specifically, the characteristic data of the layout formed by the physical layouts corresponding to each voltage circuit under the target standard cell layout framework satisfies the requirements of the standard cell characteristic data.

[0124] After determining the requirements for the characteristic data of the target standard cell, the physical layout of the standard cell can be obtained based on the physical layout of the sub-circuits corresponding to the standard cell within the layout framework of the target standard cell. Furthermore, the circuit structure diagram of the standard cell can be obtained based on the circuit structure diagrams of the sub-circuits corresponding to the standard cell.

[0125] Based on the same technical concept, this application also provides a sub-circuit library, which includes multiple voltage circuits.

[0126] Each subcircuit has at least one circuit structure netlist file, and multiple circuit structure netlist files corresponding to the same subcircuit have different driving capabilities; the same circuit structure netlist file corresponds to at least one physical layout under a standard cell layout framework.

[0127] Each subcircuit is a circuit composed of at least one transistor, and any standard unit can be obtained by splicing together at least one subcircuit from the subcircuit library.

[0128] In one implementation, the subcircuit library also includes feature data for each physical layout.

[0129] Each layout and its corresponding feature data are stored in a pre-defined standard cell library, which facilitates the direct retrieval of the layout and feature data of the standard cell to be drawn, thus improving the user experience.

[0130] The method for obtaining the characteristic data of the physical map has been clearly described above, and will not be repeated here for the sake of brevity.

[0131] In one implementation, the multiple voltage circuits in the subcircuit library are divided into an N-type transistor subcircuit library and a P-type transistor subcircuit library according to the type of transistors included in the subcircuit; wherein each subcircuit in the N-type transistor subcircuit library includes only N-type transistors, and each subcircuit in the P-type transistor subcircuit library includes only P-type transistors.

[0132] By dividing the multiple voltage circuits in the subcircuit library into N-type transistor subcircuit libraries and P-type transistor subcircuit libraries according to the type of transistor, it is easier to quickly find the corresponding subcircuit during subsequent use.

[0133] In one implementation, the subcircuit library also includes a circuit structure diagram for each subcircuit.

[0134] Since the subcircuit library also includes the circuit structure diagram of each subcircuit, users can quickly determine the circuit structure and function of each subcircuit through the circuit structure diagram in subsequent use, which facilitates subsequent use.

[0135] Based on the same technical concept, this application also provides a standard cell layout generation apparatus, such as... Figure 8 As shown, the standard cell layout generation device 100 includes a first processing module 110 and a second processing module 120.

[0136] The first processing module 110 is used to extract at least one sub-circuit from a preset sub-circuit library based on the hardware description language and driving capability of the standard unit to be drawn, to obtain the target sub-circuit combination corresponding to the standard unit to be drawn; wherein, the sub-circuit library includes multiple sub-circuits, each sub-circuit is a circuit composed of at least one transistor, and any standard unit can be obtained by splicing together at least one sub-circuit in the sub-circuit library; the driving capability of the target sub-circuit combination is the same as the driving capability of the standard unit to be drawn, and the circuit structure of the target sub-circuit combination is the same as the circuit structure described by the hardware description language.

[0137] The second processing module 120 is used to obtain the layout of the standard cell to be drawn based on the target sub-circuit combination.

[0138] Each subcircuit in the subcircuit library has at least one circuit structure netlist file, and multiple circuit structure netlist files corresponding to the same subcircuit have different driving capabilities; the target subcircuit combination includes: the subcircuit it has and the circuit structure netlist file of the entire target subcircuit combination; the first processing module 110 is specifically used to extract at least one subcircuit from the subcircuit library that can be combined to obtain the circuit structure of the standard unit to be drawn, to obtain the subcircuit of the target subcircuit combination; from the circuit structure netlist file of the at least one subcircuit, obtain the target circuit structure netlist file that matches the driving capability of the standard unit to be drawn; merge the target circuit structure netlist files of the at least one subcircuit, and add the connection relationship between the at least one subcircuit according to the circuit structure described by the hardware description language of the standard unit to be drawn, to obtain the circuit structure netlist file of the target subcircuit combination.

[0139] Each sub-circuit includes multiple physical layouts, and the multiple physical layouts are generated based on the circuit structure netlist files of each sub-circuit. For each circuit structure netlist file, N physical layouts corresponding to N standard cell layout frames are generated, where N is a positive integer. The second processing module 120 is specifically used to obtain the target physical layouts of each sub-circuit in the target sub-circuit combination. The target physical layout is a physical layout generated based on the target circuit structure netlist file that matches the driving capability of the standard cell to be drawn. According to the connection relationship between the sub-circuits specified in the circuit structure netlist file of the target sub-circuit combination, the target physical layouts of each sub-circuit are spliced ​​together to form the layout of the standard cell to be drawn.

[0140] N is a constant greater than or equal to 2; the second processing module 120 is specifically used for the following for the N standard cell layout frames: splicing the target physical layouts of each sub-circuit corresponding to the same standard cell layout frame according to the connection relationship between the sub-circuits specified in the circuit structure netlist file of the target sub-circuit combination, to obtain the N layouts of the standard cell to be drawn.

[0141] After obtaining N layouts of the standard unit to be drawn, the second processing module 120 is further configured to select the target layout whose feature data best matches the requirements of the standard unit to be drawn from the N layouts as the final layout of the standard unit to be drawn, based on the feature data of each of the N layouts; wherein, the feature data characterizes the circuit characteristics of the entire circuit corresponding to the layout.

[0142] Each sub-circuit includes multiple physical layouts, which are generated based on the netlist files of each circuit structure of the sub-circuit. For each circuit structure netlist file, N physical layouts are generated corresponding to N standard cell layout frames, where N is a positive integer. The second processing module 120 is specifically used to determine, for each standard cell layout frame, the characteristic data of the target sub-circuit combination under that standard cell layout frame, based on the characteristic data of each sub-circuit in the target sub-circuit combination and the frame parameters of that standard cell layout frame. The characteristic data of the sub-circuit characterizes the circuit characteristics of the sub-circuit. The feature data of the target sub-circuit combination characterizes the overall circuit characteristics of the target sub-circuit combination; from the feature data of the target sub-circuit combination under the N standard cell layout frameworks, the target feature data that best meets the requirements of the standard cell to be drawn is selected; the target physical layout of each sub-circuit corresponding to the target standard cell layout framework is spliced ​​according to the connection relationship between the sub-circuits specified in the circuit structure netlist file of the target sub-circuit combination to obtain the layout of the standard cell to be drawn; wherein, the target standard cell layout framework is the standard cell layout framework corresponding to the target feature data.

[0143] In one implementation, the feature data includes at least one of the following: layout area occupancy, number of virtual gates, parasitic resistance of each node in the subcircuit, parasitic capacitance, delay time corresponding to the gate node to the subcircuit port, toggle time corresponding to the gate node to the subcircuit port, dynamic power consumption corresponding to the gate node to the subcircuit port, and static power consumption corresponding to the gate node state.

[0144] The second processing module 120 is specifically used to generate the layout of the standard cell to be drawn based on the circuit structure netlist file of the target sub-circuit combination using the automatic layout and routing tool.

[0145] The standard cell layout generation apparatus 100 provided in this application embodiment has the same implementation principle and technical effect as the aforementioned standard cell layout generation method embodiment. For the sake of brevity, any parts not mentioned in the apparatus embodiment can be referred to the corresponding content in the aforementioned standard cell layout generation method embodiment.

[0146] Based on the same technical concept, this application also provides a standard unit library creation apparatus, such as... Figure 9 As shown, the standard unit library establishment device 200 includes an acquisition module 210 and a third processing module 220.

[0147] The acquisition module 210 is used to obtain the layout of the standard unit to be drawn according to the above standard unit layout generation method.

[0148] The third processing module 220 is used to construct a standard cell library based on the layout of each standard cell to be drawn and the hardware description language of each standard cell to be drawn.

[0149] The subcircuit library also includes feature data for each physical layout of the subcircuit. The third processing module 220 is specifically used to calculate the feature data of each standard cell to be drawn based on the feature data of each target physical layout that makes up the layout; and to construct the standard cell library based on the obtained layout and feature data of each standard cell to be drawn, as well as the hardware description language of each standard cell to be drawn.

[0150] Before constructing the standard cell library based on the layout and hardware description language of each standard cell to be drawn, the acquisition module 210 is also used to acquire the circuit structure diagram of each standard cell to be drawn. Correspondingly, the third processing module 220 is specifically used to construct the standard cell library based on the layout and feature data of each standard cell to be drawn, as well as the hardware description language and circuit structure diagram of each standard cell to be drawn.

[0151] Please see Figure 10 This is an electronic device 300 provided in an embodiment of this application. The electronic device 300 includes: a processor 310 and a memory 320.

[0152] The memory 320 and processor 310 are electrically connected directly or indirectly to each other to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. The memory 320 is used to store computer programs, such as those containing... Figure 8 The software functional modules shown are, namely, the standard cell layout generation device 100; and / or, storing... Figure 9 The software functional module shown is the standard cell library creation device 200. Both the standard cell layout generation device 100 and the standard cell library creation device 200 include at least one software functional module that can be stored in the memory 320 in the form of software or firmware, or embedded in the operating system (OS) of the electronic device 300.

[0153] The processor 310 is used to execute executable modules stored in the memory 320, such as software function modules or computer programs included in the standard cell layout generation device 100. At this time, the processor 310 is used to extract at least one sub-circuit from a preset sub-circuit library based on the hardware description language and driving capability of the standard cell to be drawn, to obtain a corresponding target sub-circuit combination for the standard cell to be drawn; wherein, the sub-circuit library includes multiple sub-circuits, each sub-circuit being a circuit composed of at least one transistor, and any standard cell can be obtained by splicing together at least one sub-circuit from the sub-circuit library; the driving capability of the target sub-circuit combination is the same as the driving capability of the standard cell to be drawn, and the circuit structure of the target sub-circuit combination is the same as the circuit structure described by the hardware description language; based on the target sub-circuit combination, the layout of the standard cell to be drawn is obtained.

[0154] Alternatively, the processor 310 can be used to execute executable modules stored in the memory 320, such as software functional modules or computer programs included in the standard cell library building device 200. In this case, the processor 310 is used to obtain the layout of the standard cells to be drawn according to the standard cell layout generation method; and to construct a standard cell library based on the obtained layout of each standard cell to be drawn and the hardware description language of each standard cell to be drawn.

[0155] The memory 320 can be, but is not limited to, RAM (Random Access Memory), ROM (Read Only Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electric Erasable Programmable Read-Only Memory), etc.

[0156] Processor 310 may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a CPU (Central Processing Unit), NP (Network Processor), etc.; it can also be a DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor, or processor 310 can be any conventional processor.

[0157] Among them, the aforementioned electronic devices 300 include, but are not limited to, personal computers, servers, etc.

[0158] This application also provides a computer-readable storage medium (hereinafter referred to as the storage medium) storing a computer program. When the computer program is run by a computer, such as the electronic device 300 described above, it executes the standard cell layout generation method shown above. The computer-readable storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory, a random access memory, a magnetic disk, or an optical disk.

[0159] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for generating a standard cell layout, characterized in that, include: Based on the hardware description language and driving capability of the standard unit to be drawn, at least one sub-circuit is extracted from a preset sub-circuit library to obtain the target sub-circuit combination corresponding to the standard unit to be drawn; wherein, the sub-circuit library includes multiple sub-circuits, each of which is a circuit composed of at least one transistor, and any standard unit can be obtained by splicing together at least one sub-circuit in the sub-circuit library; the driving capability of the target sub-circuit combination is the same as the driving capability of the standard unit to be drawn, and the circuit structure of the target sub-circuit combination is the same as the circuit structure described by the hardware description language; Based on the target sub-circuit combination, the layout of the standard cell to be drawn is obtained; Each subcircuit in the subcircuit library has at least one circuit structure netlist file, and the multiple circuit structure netlist files corresponding to the same subcircuit have different driving capabilities; the target subcircuit combination includes: the subcircuit it has and the circuit structure netlist file of the entire target subcircuit combination. Based on the hardware description language and driving capabilities of the standard unit to be drawn, at least one sub-circuit is extracted from a preset sub-circuit library to obtain the target sub-circuit combination corresponding to the standard unit to be drawn, including: Extract at least one subcircuit from the subcircuit library that can be combined to obtain the circuit structure of the standard unit to be drawn, and obtain the subcircuit of the target subcircuit combination. From the circuit structure netlist file of the at least one sub-circuit, obtain the target circuit structure netlist file that matches the driving capability of the standard cell to be drawn; The target circuit structure netlist files of the at least one sub-circuit are merged, and the connection relationships between the at least one sub-circuit are added according to the circuit structure described by the hardware description language of the standard unit to be drawn, so as to obtain the circuit structure netlist file of the target sub-circuit combination.

2. The method according to claim 1, characterized in that, Each sub-circuit includes multiple physical layouts, and the multiple physical layouts are generated based on the circuit structure netlist files of each sub-circuit. For each circuit structure netlist file, N physical layouts are generated corresponding to N standard cell layout frames, where N is a positive integer. Based on the target subcircuit combination, the layout of the standard cell to be drawn is obtained, including: Obtain the target physical layout of each sub-circuit of the target sub-circuit combination; the target physical layout is a physical layout generated based on the target circuit structure netlist file that matches the driving capability of the standard cell to be drawn; According to the connection relationships between subcircuits specified in the circuit structure netlist file of the target subcircuit combination, the target physical layouts of each subcircuit are stitched together to form the layout of the standard cell to be drawn.

3. The method according to claim 2, characterized in that, N is a constant greater than or equal to 2; According to the connection relationships between subcircuits specified in the circuit structure netlist file of the target subcircuit combination, the target physical layouts of each subcircuit are stitched together to form the layout of the standard cell to be drawn, including: For the N standard cell layout frameworks: the target physical layouts of each sub-circuit corresponding to the same standard cell layout framework are spliced ​​together according to the connection relationship between the sub-circuits specified in the circuit structure netlist file of the target sub-circuit combination to obtain N layouts of the standard cell to be drawn.

4. The method according to claim 3, characterized in that, After obtaining N layouts of the standard unit to be drawn, the method further includes: Based on the feature data of each of the N layouts, the target layout whose feature data best matches the requirements of the standard unit to be drawn is selected from the N layouts as the final layout of the standard unit to be drawn; wherein, the feature data characterizes the circuit characteristics of the entire circuit corresponding to the layout.

5. The method according to claim 3, characterized in that, After obtaining N layouts of the standard unit to be drawn, the method further includes: For each of the N layouts, the feature data of the layout is calculated based on the feature data of each of the target physical layouts that make up the layout. Each of the N layouts, along with the corresponding feature data, is stored in a pre-defined standard unit library.

6. The method according to claim 5, characterized in that, The standard cell library also includes the hardware description language and circuit diagram for each standard cell.

7. The method according to claim 1, characterized in that, Each sub-circuit includes multiple physical layouts, and the multiple physical layouts are generated based on the circuit structure netlist files of each sub-circuit. For each circuit structure netlist file, N physical layouts are generated corresponding to N standard cell layout frames, where N is a positive integer. Based on the target subcircuit combination, the layout of the standard cell to be drawn is obtained, including: For each standard cell layout framework, based on the characteristic data of each sub-circuit of the target sub-circuit combination and the framework parameters of the standard cell layout framework, the characteristic data of the target sub-circuit combination under the standard cell layout framework are determined; the characteristic data of the sub-circuit represents the circuit characteristics of the sub-circuit; the characteristic data of the target sub-circuit combination represents the overall circuit characteristics of the target sub-circuit combination. Select the target feature data that best matches the requirements of the standard cell to be drawn from the feature data of the target sub-circuit combination under the N standard cell layout frameworks; The target physical layout of the corresponding target standard cell layout frame in each sub-circuit is spliced ​​together according to the connection relationship between the sub-circuits specified in the circuit structure netlist file of the target sub-circuit combination to obtain the layout of the standard cell to be drawn. The target standard unit layout framework is the standard unit layout framework corresponding to the target feature data.

8. The method according to claim 4 or 7, characterized in that, The feature data includes at least one of the following: layout area occupancy, number of virtual gates, parasitic resistance and parasitic capacitance of each node in the subcircuit, delay time corresponding to the gate node to the subcircuit port, toggle time corresponding to the gate node to the subcircuit port, dynamic power consumption corresponding to the gate node to the subcircuit port, and static power consumption corresponding to the gate node state.

9. The method according to claim 1, characterized in that, Based on the target subcircuit combination, the layout of the standard cell to be drawn is obtained, including: The layout-based automatic placement and routing tool generates the layout of the standard cells to be drawn according to the circuit structure netlist file of the target sub-circuit combination.

10. A method for establishing a standard unit library, characterized in that, include: The layout of the standard cell to be drawn is obtained according to the method described in any one of claims 1-9; Based on the layout of each standard cell to be drawn and the hardware description language of each standard cell to be drawn, a standard cell library is constructed.

11. The method according to claim 10, characterized in that, The subcircuit library also includes feature data for each physical layout of the subcircuit. Based on the obtained layout of each standard cell to be drawn and the hardware description language of each standard cell to be drawn, a standard cell library is constructed, including: For each standard unit to be drawn, the feature data of the layout is calculated based on the feature data of each of the target physical layouts that make up the layout. Based on the layout and feature data of each standard cell to be drawn, and the hardware description language of each standard cell to be drawn, the standard cell library is constructed.

12. The method according to claim 11, characterized in that, Before constructing the standard cell library based on the layout of each standard cell to be drawn and the hardware description language of each standard cell to be drawn, the method further includes: Obtain the circuit structure diagram of each standard unit to be drawn; Accordingly, based on the layout of each standard cell to be drawn and the hardware description language of each standard cell to be drawn, a standard cell library is constructed, including: Based on the layout and feature data of each standard cell to be drawn, as well as the hardware description language and circuit structure diagram of each standard cell to be drawn, the standard cell library is constructed.

13. A subcircuit library, characterized in that, include: Multiple subcircuits, each subcircuit having at least one circuit structure netlist file, and the multiple circuit structure netlist files corresponding to the same subcircuit having different driving capabilities; the same circuit structure netlist file corresponds to at least one physical layout under a standard cell layout framework. Each of the sub-circuits is a circuit composed of at least one transistor, and any standard cell can be obtained by splicing together at least one sub-circuit from the sub-circuit library; the sub-circuit is used in the standard cell layout generation method as described in any one of claims 1-9.

14. The subcircuit library according to claim 13, characterized in that, The subcircuit library also includes feature data for each physical layout.

15. The subcircuit library according to claim 13, characterized in that, The multiple voltage circuits in the subcircuit library are divided into N-type transistor subcircuit libraries and P-type transistor subcircuit libraries according to the transistor types included in the subcircuit; wherein, each subcircuit in the N-type transistor subcircuit library includes only N-type transistors, and each subcircuit in the P-type transistor subcircuit library includes only P-type transistors.

16. The subcircuit library according to claim 13, characterized in that, The subcircuit library also includes a circuit diagram for each subcircuit.

17. A standard cell layout generation apparatus, characterized in that, include: The first processing module is used to extract at least one sub-circuit from a preset sub-circuit library based on the hardware description language and driving capability of the standard unit to be drawn, thereby obtaining the target sub-circuit combination corresponding to the standard unit to be drawn; wherein, the sub-circuit library includes multiple sub-circuits, each sub-circuit being a circuit composed of at least one transistor, and any standard unit can be obtained by splicing together at least one sub-circuit in the sub-circuit library; the driving capability of the target sub-circuit combination is the same as the driving capability of the standard unit to be drawn, and the circuit structure of the target sub-circuit combination is the same as the circuit structure described by the hardware description language; The second processing module is used to obtain the layout of the standard cell to be drawn based on the target sub-circuit combination; Each subcircuit in the subcircuit library has at least one circuit structure netlist file, and the multiple circuit structure netlist files corresponding to the same subcircuit have different driving capabilities; the target subcircuit combination includes: the subcircuit it has and the circuit structure netlist file of the entire target subcircuit combination. The first processing module is specifically used for: extracting at least one subcircuit from the subcircuit library that can be combined to obtain the circuit structure of the standard unit to be drawn, thereby obtaining the subcircuit of the target subcircuit combination; obtaining a target circuit structure netlist file that matches the driving capability of the standard unit to be drawn from the circuit structure netlist file of the at least one subcircuit; merging the target circuit structure netlist files of the at least one subcircuit, and adding the connection relationship between the at least one subcircuit according to the circuit structure described by the hardware description language of the standard unit to be drawn, thereby obtaining the circuit structure netlist file of the target subcircuit combination.

18. A standard unit library creation device, characterized in that, include: The acquisition module is used to obtain the layout of the standard cell to be drawn according to the method described in any one of claims 1-9; The third processing module is used to construct a standard cell library based on the layout of each standard cell to be drawn and the hardware description language of each standard cell to be drawn.

19. An electronic device, characterized in that, include: A memory and a processor, wherein the memory and the processor are connected; The memory is used to store programs; The processor is configured to invoke a program stored in the memory to execute the method as described in any one of claims 1-12.

20. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed by a computer, performs the method as described in any one of claims 1-12.

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