Multiple graphics method, electronic device and computer readable storage medium

Abstract

Embodiments of the present disclosure relate to a multiple patterning method, an electronic device, and a computer-readable storage medium. The method includes: exposing a first mask and a second mask for forming a via layer to form a photolithographic via pattern, wherein at least the first mask is alternately provided with a light-transmitting portion and a non-light-transmitting portion extending along a first direction according to a minimum design rule, and the second mask is alternately provided with a light-transmitting portion and a non-light-transmitting portion extending along a second direction perpendicular to the first direction; transferring the photolithographic via pattern to a corresponding first hard mask by etching to form a first via portion; etching the second hard mask under the first hard mask through a third mask so that the first via portion corresponding to the via layer in the layout among the multiple first via portions extends to the second hard mask to form a via; forming a wiring layer based on the layout of the wiring layer, and the layouts of the wiring layer and the via layer are designed based on the minimum design rule. The technology disclosed in the present disclosure can achieve a larger process window and higher overlay accuracy.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to integrated circuits, and more particularly, to a multi-patterning method, an electronic device, and a computer-readable storage medium. Background Art

[0002] Computational lithography is an important driving force for the continued development of graphic miniaturization technology since the 1990s. Computational lithography aims to break through the hardware limitations of the minimum exposure size by improving software technologies such as resolution while keeping the hardware environment of existing lithography equipment unchanged, which has greatly promoted the development of advanced semiconductor processes.

[0003] In photolithography technology, when using a photolithography machine with the same wavelength, the size of the graphics on the layout that can be successfully resolved by the through-hole layer and the size of the graphics on the layout that can be successfully resolved by the wiring layer are inconsistent. Due to the difference in lithography resolution between the through-hole layer and the wiring layer, the through-hole layer cannot directly match the spacing of the wiring layer in the design. As a result, it is necessary to pay attention to this mismatch in the design and perform more complex operations in the process to solve the problem. Multi-Patterning Technologies (MPT) technology is introduced in the traditional solution to solve this problem. Traditional double patterning technology requires the layout to be split, and in the lithography process, light source mask joint optimization is required to obtain the best process window. There are defects such as complex process and high requirements for subsequent etching process. Summary of the invention

[0004] According to example embodiments of the present disclosure, a multiple patterning scheme is provided to at least partially overcome the above or other potential drawbacks.

[0005] According to one aspect of the present disclosure, a multiple patterning method is provided. The method includes: exposing a first mask and a second mask for forming the via layer to form a photolithographic via pattern, wherein at least the first mask is alternately provided with a light-transmitting portion and a non-light-transmitting portion extending along a first direction according to the minimum design rule, and the second mask is alternately provided with a light-transmitting portion and a non-light-transmitting portion extending along a second direction perpendicular to the first direction; transferring the photolithographic via pattern to a corresponding first hard mask by etching to form a first via portion; etching the second hard mask under the first hard mask through a third mask, so that the first via portion corresponding to the via layer in the layout of the via layer in the plurality of the first via portions extends to the second hard mask to form a via; and forming a wiring layer based on the layout of the wiring layer, wherein the layout of the wiring layer and the layout of the via layer are designed based on the minimum design rule. The embodiments of the present disclosure can achieve a larger process window and higher overlay accuracy by arranging the wiring layer and the via layer according to the minimum design rules and setting two masks for forming vias, and can also improve the integration of the circuit and effectively reduce the energy consumption of the chip.

[0006] According to the second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor; and a memory coupled to the processor, the memory having instructions stored therein, and the instructions, when executed by the processor, cause the device to perform an action, the action including: exposing a first mask and a second mask for forming a via layer to form a photolithographic via pattern, wherein at least the first mask is alternately provided with a light-transmitting portion and a non-light-transmitting portion extending along a first direction according to a minimum design rule, and the second mask is alternately provided with a light-transmitting portion and a non-light-transmitting portion extending along a second direction perpendicular to the first direction; transferring the photolithographic via pattern to a corresponding first hard mask by etching to form a first via portion; etching the second hard mask under the first hard mask through a third mask, so that the first via portion corresponding to the via layer in the layout of the via layer in the plurality of first via portions extends into the second hard mask to form a via; and forming a wiring layer based on the layout of the wiring layer, wherein the layout of the wiring layer and the layout of the via layer are designed based on the minimum design rule.

[0007] In some embodiments, respectively exposing a first mask and a second mask for forming a through-hole layer to form a photolithographic through-hole pattern includes: applying a negative development technique to the exposed first mask and the second mask to form a photolithographic through-hole pattern in the first photoresist layer, wherein there is no etching process between the exposure of the first mask and the exposure of the second mask.

[0008] In some embodiments, transferring the photolithographic through-hole pattern to the corresponding first hard mask by etching to form a first through-hole portion includes: etching the stop layer with a first etchant to transfer the photolithographic through-hole pattern in the first photoresist layer to the stop layer, wherein the first etchant does not etch the second hard mask, and the stop layer serves as the first hard mask.

[0009] In some embodiments, etching the second hard mask below the first hard mask through the third mask includes: setting a second photoresist layer corresponding to the through-hole layer in the layout as a third mask on the first hard mask; and etching the second hard mask through the second photoresist layer so that the first through-hole portion extends into the second hard mask to form a through-hole.

[0010] In some embodiments, etching the second hard mask through the second photoresist layer includes etching the additional layer using a second etchant to form a through hole, wherein the second etchant does not etch the first hard mask and the additional layer serves as a second hard mask.

[0011] In some embodiments, the light-transmitting portions and the non-light-transmitting portions in the first mask and the second mask are both rectangular shapes with the same size.

[0012] In some embodiments, the area defined by the patterns in the third mask corresponds to the area of ​​the via layer in the layout, wherein the area defined by at least one pattern in the third mask corresponds to more than two photolithography via patterns.

[0013] In some embodiments, the material forming the second hard mask includes at least one of the following: SiON; Si3N4.

[0014] According to a third aspect of the present disclosure, a semiconductor structure is provided, which includes: a substrate; a dielectric layer formed on the substrate, a front-end metal layer formed in the dielectric layer; an additional layer formed on the dielectric layer; a stop layer formed on the additional layer; a back-end metal layer formed on the stop layer; and a through-hole layer formed to penetrate the stop layer and the additional layer and connect the front-end metal layer and the back-end metal layer.

[0015] In some embodiments, the via layer is formed by: performing a first etching on the stop layer using a first etchant to transfer the via pattern on the first photoresist layer to the stop layer to form a first via portion, wherein the first etchant does not etch the additional layer; and performing a second etching on the additional layer using a second etchant so that a first via portion among the plurality of first via portions corresponding to the via layer in the layout extends to the top of the front metal layer to form a through hole, wherein the second etchant does not etch the stop layer.

[0016] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the program is executed by a processor, the method according to the first aspect of the present disclosure is implemented.

[0017] It will be understood from the following description that the technical solution of the present disclosure can achieve a larger process window and higher overlay accuracy, and can also improve the integration of circuits and effectively reduce chip energy consumption.

[0018] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the disclosure, nor is it intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of the structure of preparing through holes in a traditional manner is shown;

[0020] Figure 2 right Figure 1 A schematic diagram of a structure in which a photolithography process is performed on the structure;

[0021] Figure 3 A schematic diagram showing an example environment in which embodiments of the present disclosure can be implemented;

[0022] Figure 4 A flowchart of a multiple graphics method according to some embodiments of the present disclosure is shown;

[0023] Figure 5 A schematic diagram of a layout of a wiring layer arranged according to minimum design rules according to some embodiments of the present disclosure is shown;

[0024] Figure 6 A schematic diagram of a first mask for forming a through hole according to some embodiments of the present disclosure is shown;

[0025] Figure 7 A schematic diagram of a second mask for forming a through hole according to some embodiments of the present disclosure is shown;

[0026] Figure 8 A schematic diagram showing a through hole formed on a photoresist layer after exposure according to some embodiments of the present disclosure;

[0027] Fig. 9 According to some embodiments of the present disclosure, Figure 8 A schematic diagram of providing a hard mask on the through hole described in ;

[0028] Fig.10 A schematic diagram showing a wiring layer formed on a photoresist layer by photolithography according to some embodiments of the present disclosure;

[0029] Fig.11 The present invention shows some embodiments of the present invention. Fig.10 A schematic diagram of a final wiring layer and a through-hole layer formed after etching the wiring layer shown;

[0030] Fig.12 A schematic diagram of an initial structure for preparing a through-hole structure according to some embodiments of the present disclosure is shown;

[0031] Fig.13 The present invention shows some embodiments of the present invention. Fig.12 A schematic diagram of a structure formed after the structure shown is processed;

[0032] Fig.14 The present invention shows some embodiments of the present invention. Fig.13 A schematic diagram of a structure formed after the structure shown is processed;

[0033] Fig.15 The present invention shows some embodiments of the present invention. Fig.14 A schematic diagram of the structure finally formed after the structure shown is processed;

[0034] Fig.16 A schematic diagram regarding spacing is shown;

[0035] Fig.17 A block diagram of a computing device capable of implementing various embodiments of the present disclosure is shown.

[0036] In the various drawings, the same or corresponding reference numerals represent the same or corresponding parts. DETAILED DESCRIPTION

[0037] The principles of the present disclosure will be described below with reference to the various exemplary embodiments shown in the accompanying drawings. It should be understood that the description of these embodiments is only to enable those skilled in the art to better understand and further implement the present disclosure, and is not intended to limit the scope of the present disclosure in any way. It should be noted that similar or identical reference numerals may be used in the figures where feasible, and similar or identical reference numerals may represent similar or identical functions. Those skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods described herein may be adopted without departing from the principles of the present disclosure described herein.

[0038] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects.

[0039] As mentioned earlier, in photolithography technology, when using a photolithography machine with the same wavelength (such as a 193nm light source photolithography machine for wet lithography), the size of the graphics on the layout that can be successfully resolved (with sufficient process window) for the through-hole layer and the size of the graphics on the layout that can be successfully resolved for the line / space layer are inconsistent. For example, for the line layer with a process node of 28nm, the resolvable size is 45nm / 45nm (pitch=90nm), while the actual resolved size of the through-hole layer will be 65nm / 62nm (pitch=127nm), and the actual resolved size of the through-hole layer with equal potential (the through holes are connected to the same wire and thus have equal potential) can be 65nm / 34nm. Therefore, as is well known in the industry, it is difficult to make holes of the same size while a certain line width can be achieved for the line / space. Refer to the following. Fig.16 Further description is given.

[0040] Fig.16 A schematic diagram of the spacing is shown. Fig.16 As shown in the figure, the dark stripes represent the wires (conductors) and the light stripes represent the distance between the wires. The pitch of the wires is Fig.16 The distance indicated by P in is the distance of one cycle. In addition, Fig.16 Four holes are shown, denoted by H1, H2, H3 and H4. The spacing between holes H1 and H2 is L1+L2. As mentioned earlier, for the 28nm process node, the spacing of the connection is 90nm, and the resolvable size is 45nm / 45nm (pitch=90nm). The actual resolvable size of the through-hole layer will be 65nm / 62nm (pitch=127nm). For the equipotential through-hole layer, the actual resolvable size is 65nm / 34nm, while the line is 45+45nm. Among them, 65nm is the size of the hole, and 34nm is the distance between the two holes. If the potential is not equal, the spacing is equal to 99 times the square root of 2.

[0041] like Fig.16As shown in FIG. 1 , if the resolvable size of the connection is 45nm / 45nm, the conventional solution cannot resolve H1 and H3. In other words, the conventional solution cannot resolve Fig.16 Through holes H1 and H3 are made at the positions shown in . For through holes H1 and H2 on the same conductor (i.e., equipotential), the spacing between them is 65nm+34nm, i.e., 99nm, which is greater than 90nm. For through holes on different conductors (i.e., non-equipotential), the spacing should be at least √2 times the spacing between the two when the potential is equal, i.e., Fig.16 As shown, they are arranged in a manner such that H1 and H4 are in a diagonal position.

[0042] The difference in lithography resolution between the via layer and the wiring layer (also called the lead layer) is caused by optical effects. For example, for a certain wavelength, when the relevant feature size is small to a certain extent, the via becomes more difficult to resolve, that is, the signal of the via decays faster as the hole shrinks, resulting in a very large loss of its entire process window, making it difficult to make the hole.

[0043] Due to the difference in lithography resolution between the via layer and the wiring layer, in actual design, the via layer cannot directly match the spacing of the wiring layer, that is, the two cannot be set to the same spacing. As a result, it is necessary to pay attention to this mismatch in design and perform more complex operations in the process to solve this problem.

[0044] The common solution to the problem in the industry is to introduce multiple patterning technologies, such as lithography and etching technology (Litho Etch Litho Etch, referred to as LELE) and double patterning technology (Double-Patterning Technologies, referred to as DPT). In this case, the previous one-lithography and one-etching process will be changed to two-lithography and two-etching processes. Moreover, in a single exposure, the through hole actually still needs to be 65nm in size, which is not very friendly to the overlay accuracy (the LELE technology itself has high requirements for overlay accuracy) and has high requirements for subsequent etching processes. In addition, the traditional double patterning technology requires the layout to be split, and in the lithography process, the light source mask needs to be jointly optimized to obtain the best process window (the process window of the through hole layer is usually smaller).

[0045] Figure 1 FIG. 2 shows a schematic diagram of the structure of the through hole prepared in the traditional way. Figure 1 As shown, the bottom of the structure is a substrate 102 , a SIO2 layer 104 is located on the substrate 102 , and a stop layer 106 is located above the SIO2 layer.

[0046] See also Figure 2 , Figure 2 Yes Figure 1 Schematic diagram of the structure of the etching process. Figure 2 As shown, a portion of the stop layer 106 is etched away to form an opening 108 in the middle.

[0047] In the conventional scheme, the mask used to form the hole is usually a plurality of square patterns set in the mask. By exposing through the plurality of square patterns, the hole is directly formed in the subsequent etching process. Due to the optical effect, this method cannot form a through hole with the minimum design rule size. Specifically, the optical signal at the edge of the square pattern in the mask is severely attenuated, resulting in the inability to form a through hole with the minimum design rule size. In the conventional scheme, it is usually necessary to set the pitch between the two through holes to twice the square root of the minimum design rule. This makes it impossible to obtain a higher pattern density.

[0048] In view of this, the present disclosure aims to provide an improved solution.

[0049] Some embodiments of the present disclosure provide an improved multiple patterning method. The method includes: exposing a first mask and a second mask for forming the via layer to form a photolithographic via pattern, wherein at least the first mask is alternately provided with a light-transmitting portion and a non-light-transmitting portion extending along a first direction according to the minimum design rule, and the second mask is alternately provided with a light-transmitting portion and a non-light-transmitting portion extending along a second direction perpendicular to the first direction; transferring the photolithographic via pattern to a corresponding first hard mask by etching to form a first via portion; etching the second hard mask under the first hard mask through a third mask, so that the first via portion corresponding to the via layer in the layout of the via layer among the plurality of the first via portions extends into the second hard mask to form a via; and forming the wiring layer based on the layout of the wiring layer, wherein the layout of the wiring layer and the layout of the via layer are designed based on the minimum design rule. The embodiment of the present disclosure arranges the wiring layer and the via layer according to the minimum design rules, and sets two masks for forming vias, which can achieve a larger process window and higher overlay accuracy, and can also improve the integration of the circuit and effectively reduce chip energy consumption.

[0050] For the through hole layer that needs to be processed according to the solution of the present disclosure, the first mask and the second mask can be universal; and the through hole layer can cooperate with the lead layer to achieve higher density interconnection and improve the pattern density.

[0051] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0052] Figure 3 Schematic diagram of an example environment 300 in which embodiments according to the present disclosure can be implemented. Figure 3As shown, the example environment 300 includes a computing device 310 and a client 320 .

[0053] In some embodiments, the computing device 310 may interact with the client 320. For example, the computing device 310 may receive an input message from the client 320 and output a feedback message to the client 320. In some embodiments, the input message from the client 320 may be layout data. The computing device 310 may perform corresponding mathematical operations on the layout data and output corresponding operation results to the client 320.

[0054] In some embodiments, computing device 310 may include, but is not limited to, a personal computer, a server computer, a handheld or laptop device, a mobile device (such as a mobile phone, a personal digital assistant (PDA), a media player, etc.), consumer electronics, a minicomputer, a mainframe computer, cloud computing resources, etc.

[0055] It should be understood that the structure and function of the example environment 300 are described for exemplary purposes only and are not intended to limit the scope of the subject matter described herein. The subject matter described herein can be implemented in different structures and / or functions. The environment is merely illustrative and is not intended to limit the application environment of the embodiments of the present disclosure.

[0056] In order to explain the principle of the present disclosure more clearly, the following will refer to Figure 4 Let's describe it in more detail.

[0057] Figure 4 A flow chart of a multiple patterning method 400 according to some embodiments of the present disclosure is shown.

[0058] At frame 402, a first mask and a second mask for forming a through-hole layer are exposed respectively to form a photolithographic through-hole pattern, wherein at least the first mask is alternately provided with light-transmitting portions and non-light-transmitting portions extending along a first direction according to a minimum design rule, and the second mask is alternately provided with light-transmitting portions and non-light-transmitting portions extending along a second direction perpendicular to the first direction.

[0059] Each process node will have a minimum design rule, which is applicable to the corresponding process level. For example, for the 22nm process node, the minimum design rule specifies that the size of the small squares of the 22nm metal connection is 42.5nm*42.5nm. In other words, the minimum design rule of the 22nm process node is 42.5nm. For the 28nm process node, the minimum design rule specifies that the size of the small squares of the 28nm metal connection is 45nm*45nm. In other words, the minimum design rule of the 28nm process node is 45nm. In some embodiments of the present disclosure, arranging the winding according to the corresponding minimum design rule can avoid the problem of different resolutions of the connection and the through hole. In a narrow sense, "winding" generally refers to the layout design of the lead layer, so sometimes the lead layer is also called the "winding layer", and in a broad sense, "winding" refers to the design of the lead layer and the through hole layer at the same time. In some embodiments of the present disclosure, winding can be understood in a broad sense. Resolution is generally the minimum size that can be made in the process.

[0060] In some embodiments, the layout of the via layer is designed according to the minimum design rules. Correspondingly, the layout of the wiring layer is also designed according to the minimum design rules. Figure 5 describe.

[0061] See also Figure 5 , Figure 5 FIG. 1 shows a schematic diagram of a layout of a wiring layer arranged according to minimum design rules according to some embodiments of the present disclosure. Figure 5 As shown, there are shown a plurality of small squares (also referred to as grid points) 502. The size of each small square is the minimum design rule. For a 22nm process node, the size of the small square is 42.5nm*42.5nm. Figure 5 The middle wiring layer 504 is arranged along the grid points, in other words, coincides with the small squares in each row or column rather than partially coincident or located at the boundary between adjacent small squares.

[0062] like Figure 5 As shown, the upper and lower parts of the wires are separated by a row of grid points, rather than by two or more rows, which is a manifestation of the minimum design rule. In fact, such a lead layer is relatively easy to implement, but such a through-hole layer is not easy to implement, so there will be more problems in the process and design. In the scheme of the embodiment of the present disclosure, the through-hole layer can also be squeezed into the minimum design rule. As described in detail later, in some embodiments of the present disclosure, by arranging the windings according to the corresponding minimum value rules, the resolution of the connection lines and holes can be made to the same size.

[0063] In some embodiments, a negative tone development (NTD) technique may be applied to the exposed first mask and the second mask to form a photolithographic through hole pattern in the first photoresist layer (also referred to as a photoresist layer), wherein there is no etching process between the exposure of the first mask and the exposure of the second mask. Figure 6 and Figure 7 Further description.

[0064] Reference Figure 6 , Figure 6 FIG. 4 is a schematic diagram showing a first mask 600 for forming a through hole according to some embodiments of the present disclosure. Figure 6 As shown, corresponding to Figure 5 The wiring layer 504 shown in FIG. 5 , the first mask 600 includes a plurality of stripes extending in the longitudinal direction (first direction) and arranged alternately. In some embodiments, the white stripes 604 are light-transmitting stripes, which may be referred to as light-transmitting portions, and the black stripes 602 are non-light-transmitting stripes, which may be referred to as non-light-transmitting portions.

[0065] Reference Figure 7 , Figure 7 Schematic diagram of a second mask 700 for forming through holes according to some embodiments of the present disclosure is shown. In some embodiments, the second mask 700 may have a pattern of the same shape and size as the first mask 600. The difference is that the stripes of the two extend in a vertical direction, that is, the stripes of the second mask 700 extend in the horizontal direction (second direction).

[0066] In some embodiments, the patterns of at least one of the first mask 600 and the second mask 700 may be arranged according to the minimum design rule. In some embodiments, the patterns in both the first mask 600 and the second mask 700 may be arranged according to the minimum design rule. When both are arranged according to the minimum design rule, a square through-hole shape may be obtained; when one of the patterns is arranged according to the minimum design rule, for example, a rectangular through-hole shape may be obtained instead of a square through-hole shape, which is suitable for certain specific applications.

[0067] In some embodiments, Figure 6 and Figure 7 As shown, the light-transmitting portions and the non-light-transmitting portions in the first mask and the second mask are both rectangular in shape with the same size. Figure 6 and Figure 7 The first mask and the second mask described in the above-mentioned method can be realized at a low price because they only include a long strip shape.

[0068] In addition, as is known in the industry, for holes, the mask usually includes multiple holes, the surroundings of the holes are opaque, and the edges of the holes attenuate light very quickly, resulting in a large loss of process window. For a linear mask, light attenuation is linear, and the process window loss is very small. Therefore, in the embodiment of the present disclosure, by adopting the above-mentioned first mask and second mask, a higher density through-hole pattern can be obtained compared to the traditional solution without defects such as bridging. This will be further described later.

[0069] In some embodiments, negative development technology may be used to expose the first mask 600 and the second mask 700 twice in succession, i.e., no etching is performed in between, which is equivalent to Litho Litho Etch (LLE). In the NTD process, the photoresist material is strengthened (polymerized or cross-linked) by light, and the developer will only dissolve the area not exposed to light. That is, the exposed area is retained, while the unexposed area is dissolved.

[0070] In some embodiments, the first mask and the second mask are exposed using the characteristics of NTD to obtain a desired through-hole pattern. In some embodiments, a more special pattern structure can be established by combining some special design techniques with the number of exposures, but generally speaking, two exposures are sufficient.

[0071] In the above embodiments, the NTD process is used as an example for description, but the embodiments of the present disclosure are not limited thereto. For example, the positive development technology is used, and the first mask and the second mask are adjusted accordingly.

[0072] In some embodiments, by providing a mask including a stripe pattern to convert the defined holes into defined lines, the process window will be much larger and more stable.

[0073] After two consecutive exposures, the final result is as follows Figure 8 See the figure shown. Figure 8 , Figure 8 FIG. 1 is a schematic diagram showing a through-hole pattern formed on a photoresist layer after exposure according to some embodiments of the present disclosure. Figure 8 The through hole pattern shown is a through hole 802 pattern displayed on the photoresist layer, which can be called a photolithography through hole pattern. The spacing between each through hole is the minimum design rule. For example, for a 28nm process node, the spacing between each through hole is 90nm.

[0074] In the traditional scheme, during the overlap process, it is necessary to take into account two directions at the same time to align the holes. In some embodiments of the present disclosure, when doing overlay, as long as one of the two masks is aligned in the first and second directions respectively, the original alignment problem in the multiple exposure technology can be avoided. In some embodiments of the present disclosure, by using two masks of the NTD process, the defined holes can be finally determined. Specifically, by crossing the two masks, the intersection of two straight lines (stripes to be precise) defines a point (hole). Therefore, it is only necessary to consider the movement of each mask in one direction separately. In this way, the accuracy of adjustment can be improved and the difficulty of adjustment can be reduced.

[0075] The through hole formed in the traditional solution is usually circular. In fact, the mask pattern of the through hole is usually square, but the circular shape is formed due to the optical effect during the exposure process. In the present disclosure, two crossed masks are used to overcome the influence of exposure in the traditional method and obtain a square through hole. Since the through hole is changed from a circular shape to a square shape, the area of ​​the through hole increases by 27% (compared to a circle with the same diameter), which is equivalent to a 27% increase in conductivity, thereby improving the conductivity.

[0076] At block 404 , the photolithographic via pattern is transferred into a corresponding first hard mask by etching to form a first via portion.

[0077] In some embodiments, the stop layer may be etched using a first etchant to transfer the photolithographic via pattern in the first photoresist layer into the stop layer, wherein the first etchant does not etch the second hard mask and the stop layer serves as the first hard mask.

[0078] See also Figure 8 , Figure 8 The pattern in the image can be transferred to the corresponding first-layer hard mask (HardMask) by etching, and then the through-hole information transfer definition is performed. The first-layer hard mask can be, for example, a stop layer. The stop layer can be used to define Figure 8 The photolithography pattern shown in FIG. Fig.13 Describe this.

[0079] At block 406 , the second hard mask below the first hard mask is etched through a third mask such that a first via portion of the plurality of first via portions corresponding to a via layer in the layout of the via layer extends into the second hard mask to form a via.

[0080] In some embodiments, a second photoresist layer corresponding to the via layer in the layout can be set as a third mask on the first hard mask; and the second hard mask is etched through the second photoresist layer so that the first via portion extends into the second hard mask to form a via.

[0081] In some embodiments, etching the second hard mask through the second photoresist layer may include etching the second hard mask using a second etchant to form a through hole, wherein the second etchant does not etch the first hard mask.

[0082] Reference Fig. 9 , Fig. 9 According to some embodiments of the present disclosure, Figure 8 Schematic diagram of setting a third mask on the through hole pattern described in . Fig. 9 As shown, the third mask 902 is disposed on a portion of the through-hole pattern. The third mask 902 may be, for example, a photolithography mask. By etching the third mask 902, the hard mask corresponding to the hole to be actually opened may be etched to form the corresponding through-hole. This will be further described later. Fig. 9 As shown, the area defined by the pattern in the third mask 902 corresponds to the area of ​​the through-hole layer in the layout, wherein at least one photolithographic pattern (eg Fig. 9 The area defined by the central portion 902 corresponds to more than two photolithography through-hole patterns. It should be noted that the process requirements at this time are much lower than directly opening holes in the hard mask. Fig. 9 The patterns indicated by 902 in the central portion can collectively define the desired through-hole pattern, i.e., the through-holes do not need to be defined by shapes that precisely correspond to the individual through-holes. Because the second etchant does not etch the stop layer in the subsequent etching, only the additional layer below the etched portion of the stop layer (the first through-hole portion) is etched, thereby forming a through-hole. Therefore, the process window is significantly increased.

[0083] It can be seen that in some embodiments, by using two horizontal and vertical stripe masks that can be commonly used in the back-end process, plus a photolithography mask (third mask) with relatively low process requirements, a higher density layout that was previously unachievable can be achieved.

[0084] See also Fig.12 , Fig.12 Schematic diagram of the initial structure for preparing a through-hole structure according to some embodiments of the present disclosure is shown. Fig.12As shown, the bottom of the structure is a semiconductor substrate 1202. The semiconductor substrate 1202 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, etc. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide. In addition, the semiconductor substrate may be a structure composed of a single layer of material layers, or a stacked structure, such as a silicon / germanium silicon stack. In addition, the semiconductor substrate may be an ion-doped substrate, which may be P-type doped or N-type doped. A plurality of semiconductor devices may also be formed in the semiconductor substrate.

[0085] Above the semiconductor substrate 1202 is a dielectric layer 1204, which may be, for example, SIO2. Above the dielectric layer 1204 is an additional layer (Add-Layer) 1206, which may be a thin film layer. Above the additional layer 1206 is a stop layer (Stop-layer) 1208. In some embodiments, the additional layer 1206 may be SiON or Si3N4, etc., which is not limited in the present disclosure. Compared with the conventional solution, in some embodiments of the present disclosure, an additional layer 1206, i.e., a thin film structure, is added. By providing the additional layer 1206, the electrical performance of the device is basically not affected. However, this can improve the shape of the formed through hole and increase the conductivity accordingly, which will be further described later.

[0086] Fig.13 The present invention shows some embodiments of the present invention. Fig.12 Schematic diagram of the structure formed after etching the structure shown in FIG. Fig.13 As shown, two grooves 1210 are formed on the stop layer 1208 by, for example, etching. When etching the stop layer 1208, the etchant (which may be referred to as the first etchant) may only etch the stop layer without etching the additional layer 1206, thereby forming a Fig.13 Among the two grooves 1210 of the shape shown, the groove 1210 on the left side can be called a first through hole portion. Fig.13 The groove 1210 shown corresponds to Figure 8 The photolithographic through hole pattern 802 in FIG.

[0087] See also Fig.14 , Fig.14 The present invention shows some embodiments of the present invention. Fig.13 Schematic diagram of the structure formed after etching the structure shown in FIG. Fig.14As shown, the additional layer 1206 below the groove 1210 on the left is etched by an etchant (which may be referred to as a second etchant), and the additional layer 1206 is used here as a second hard mask for defining a through hole. Specifically, in this process, a second photoresist layer may be provided on the stop layer 1208 to etch the second hard mask. The additional layer 1206 is made of a material different from that of the stop layer 1208. The second etchant may be appropriately selected so that the second etchant does not etch the stop layer 1208, but only etches the additional layer 1206. After this etching, the groove 1210 on the left extends downward and terminates at the top of the layer 1204, thereby forming a through hole 1212. By using the additional layer 1206, a through hole with a good profile can be obtained.

[0088] Fig.15 The present invention shows some embodiments of the present invention. Fig.14 The structure shown in FIG. 1 is a schematic diagram of a semiconductor structure 1500 formed after the structure shown in FIG. Fig.15 It can be seen that the through hole 1212 is filled with copper. This can be obtained by performing a subsequent wiring layer etching process. The through hole 1212 is connected to the lower line 1502. The line 1502 can be formed in the previous process. The line 1502 extends perpendicular to the screen. Fig.15 It can be seen that the semiconductor structure includes a front-end winding layer, a via layer and a back-end winding layer. The front-end winding layer is also called the front-end metal layer, and the back-end winding layer is also called the back-end metal layer. It can be seen that the via layer includes vias and some other layers. Finally, Fig.15 The groove 1210 shown in FIG. 1 is formed as a redundant portion. Since the stop layer 1208 is usually very thin, the depth of the groove 1210 is very shallow. Therefore, this portion will not affect the performance of the semiconductor structure.

[0089] Through Fig.15 The structure shown can increase the density of effective patterns in the device, thereby improving the integration of the entire integrated circuit.

[0090] Back to Figure 4 At block 408, a wiring layer is formed based on the layout of the wiring layer. As mentioned above, the layout of the wiring layer and the layout of the via layer are designed based on minimum design rules. The wiring layer can be formed using any conventional method. Fig.10 and 11 Give a description.

[0091] See also Fig.10 , Fig.10 A schematic diagram showing a wiring layer formed on a photoresist layer by photolithography according to some embodiments of the present disclosure is shown. Fig.10 FIG. 1002 shows a wiring layer diagram having Figure 5 The same shape as the wiring layer shown.

[0092] Fig.11 The present invention shows some embodiments of the present invention. Fig.10 The schematic diagram of the final wiring layer 1102 and the via layer 1104 formed on the wafer after the wiring layer is etched is shown. From this figure, it can be seen that both the wiring and the via can be arranged according to the minimum design rules, thereby achieving the matching of the via layer and the wiring layer.

[0093] Some embodiments of the present disclosure provide a multiple patterning method. It should be noted that the examples given in the above embodiments are only for illustrating the solutions of the embodiments of the present disclosure, and are not intended to limit the solutions of the present disclosure.

[0094] An electronic device is also disclosed in an embodiment of the present disclosure. The electronic device includes: a processor; and a memory coupled to the processor, the memory having instructions stored therein, and when the instructions are executed by the processor, the device performs actions, the actions including: exposing a first mask and a second mask for forming the via layer to form a photolithographic via pattern, wherein at least the first mask is alternately provided with a light-transmitting portion and a non-light-transmitting portion extending along a first direction according to the minimum design rule, and the second mask is alternately provided with a light-transmitting portion and a non-light-transmitting portion extending along a second direction perpendicular to the first direction; transferring the photolithographic via pattern to a corresponding first hard mask by etching to form a first via portion; etching the second hard mask under the first hard mask through a third mask, so that the first via portion corresponding to the via layer in the layout of the via layer in the plurality of the first via portions extends into the second hard mask to form a via; and forming the wiring layer based on the layout of the wiring layer, wherein the layout of the wiring layer and the layout of the via layer are designed based on the minimum design rule.

[0095] A semiconductor structure is also disclosed in an embodiment of the present disclosure, and the structure includes: a substrate; a dielectric layer formed on the substrate, a front-end metal layer formed in the dielectric layer; an additional layer formed on the dielectric layer; a stop layer formed on the additional layer; a back-end metal layer formed on the stop layer; and a through-hole layer formed to penetrate the stop layer and the additional layer and connect the front-end metal layer and the back-end metal layer.

[0096] The embodiment of the present disclosure also discloses a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the multiple graphic processing method according to the embodiment of the present disclosure is implemented.

[0097] It should be understood that the embodiments shown in the drawings are only for schematically illustrating the solutions of some embodiments of the present disclosure and are not intended to limit the present disclosure. The embodiments of the present disclosure may also have various other forms.

[0098] In some embodiments of the present disclosure, the through-hole layer can be made to match the spacing of the wiring layer. At the same time, since the two masks involved in the through-hole layer only have a single direction (X or Y), a simple light source mask joint optimization method can be used to optimize the resolution of this layer. At the same time, when overlaying, since the X and Y directions of the subsequent process only need to align one of the two masks, the original alignment problem in the multiple exposure technology can be avoided.

[0099] In the embodiments of the present disclosure, a larger process window (from defining a smaller via layer to defining a wiring layer and a larger via layer) and better overlay accuracy are achieved through a simple double patterning scheme. At the same time, since the via is changed from a circular shape to a square shape, the area of ​​the via is increased (compared to a circular shape with the same diameter), which is equivalent to increasing the conductivity, thereby effectively reducing the chip energy consumption. In addition, due to the increase in pattern density, the effective chip area can be increased.

[0100] Fig.17 A schematic block diagram of an electronic device according to some exemplary embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0101] like Fig.17 As shown, the device 1700 includes a CPU 1701, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1702 or a computer program loaded from a storage unit 1708 into a random access memory (RAM) 1703. In the RAM 1703, various programs and data required for the operation of the device 1700 can also be stored. The CPU 1701, the ROM 1702, and the RAM 1703 are connected to each other via a bus 1704. An input / output (I / O) interface 1705 is also connected to the bus 1704.

[0102] Multiple components in the device 1700 are connected to the I / O interface 1705, including: an input unit 1706, such as a keyboard, a mouse, etc.; an output unit 1707, such as various types of displays, speakers, etc.; a storage unit 1708, such as a disk, an optical disk, etc.; and a communication unit 1709, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1709 allows the device 1700 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0103] The various processes and processing described above, such as method 400, may be executed by CPU 1701. For example, in some embodiments, method 400 may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as storage unit 1708. In some embodiments, part or all of the computer program may be loaded and / or installed on device 1700 via ROM 1702 and / or communication unit 1709. When the computer program is loaded into RAM 1703 and executed by CPU 1701, one or more steps in method 400 described above may be performed.

[0104] The scheme according to the embodiment of the present disclosure may be a method, an apparatus, a system and / or a computer program product. The computer program product may include a computer-readable storage medium on which computer-readable program instructions for executing various aspects of the present disclosure are loaded. The computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. The computer-readable program instructions may be downloaded from the computer-readable storage medium to various computing / processing devices, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network and / or a wireless network.

[0105] Various embodiments of the present disclosure have been described above, and the above descriptions are exemplary and are only optional embodiments of the present disclosure, not exhaustive, and are not intended to limit the present disclosure. Although the claims in this application have been formulated for specific combinations of features, it should be understood that the scope of the present disclosure also includes any novel features or any novel combination of features disclosed herein, whether or not it relates to the same scheme in any claim currently claimed for protection. The applicant hereby informs that new claims may be formulated into these features and / or combinations of these features during the examination of this application or in any further application derived therefrom.

[0106] The terms used in this article are selected to best explain the principles of each embodiment, practical application or technical improvement in the market, or to enable other ordinary technicians in the field to understand the embodiments disclosed herein. For those skilled in the art, the present disclosure may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A multiple patterning method comprising: Exposing a first mask and a second mask for forming a through-hole layer respectively to form a photolithographic through-hole pattern, wherein at least the first mask is alternately provided with light-transmitting portions and light-impermeable portions extending along a first direction according to a minimum design rule, and the second mask is alternately provided with light-transmitting portions and light-impermeable portions extending along a second direction perpendicular to the first direction; transferring the photolithographic via pattern into a corresponding first hard mask by etching to form a first via portion; Etching the second hard mask below the first hard mask through a third mask so that a first through-hole portion corresponding to a through-hole layer in the layout of the through-hole layer among the plurality of first through-hole portions extends into the second hard mask to form a through-hole; as well as A wiring layer is formed based on the layout of the wiring layer, wherein the layout of the wiring layer and the layout of the through-hole layer are designed based on the minimum design rule.

2. The method according to claim 1, wherein respectively exposing a first mask and a second mask for forming the via layer to form a photolithographic via pattern comprises: A negative development technique is applied to the exposed first mask and the second mask to form the photolithographic through hole pattern in the first photoresist layer, wherein there is no etching process between the exposure of the first mask and the exposure of the second mask.

3. The method according to claim 2, wherein transferring the photolithographic via pattern into the corresponding first hard mask by etching to form the first via portion comprises: The stop layer is etched using a first etchant to transfer the photolithographic through hole pattern in the first photoresist layer to the stop layer, wherein the first etchant does not etch the second hard mask, and the stop layer serves as the first hard mask.

4. The method according to claim 1, wherein etching the second hard mask below the first hard mask through a third mask comprises: Disposing a second photoresist layer corresponding to the through-hole layer in the layout as the third mask on the first hard mask; as well as The second hard mask is etched through the second photoresist layer so that the first via portion extends into the second hard mask to form the via.

5. The method according to claim 4, wherein etching the second hard mask through the second photoresist layer comprises: The additional layer is etched using a second etchant to form the via, wherein the second etchant does not etch the first hard mask and the additional layer serves as the second hard mask. 6 . The method according to claim 1 , wherein the light-transmitting portions and the non-light-transmitting portions in the first mask and the second mask are both rectangular shapes having the same size.

7. The method according to claim 1, wherein: The area defined by the patterns in the third mask corresponds to the area of ​​the through-hole layer in the layout, wherein the area defined by at least one pattern in the third mask corresponds to more than two of the photolithography through-hole patterns.

8. The method according to any one of claims 1 to 7, wherein a material forming the second hard mask comprises at least one of the following: SiON; Si3N4.

9. A semiconductor structure comprising: substrate; A dielectric layer is formed on the substrate, wherein a front-end metal layer is formed in the dielectric layer; an additional layer formed on the dielectric layer; a stop layer formed on the additional layer; A back-end metal layer is formed on the stop layer; as well as a via layer formed to penetrate the stop layer and the additional layer and connect the front-end metal layer and the back-end metal layer; The through-hole layer is formed by: Performing a first etching on the stop layer using a first etchant to transfer the through hole pattern on the first photoresist layer into the stop layer to form a first through hole portion, wherein the first etchant does not etch the additional layer; as well as The additional layer is second-etched using a second etchant so that a first via portion corresponding to the via layer in the layout among the plurality of first via portions extends to the top of the front-end metal layer to form the via, wherein the second etchant does not etch the stop layer.

10. The semiconductor structure according to claim 9, wherein the substrate is one of the following: Silicon substrate, germanium substrate, silicon germanium substrate, silicon on insulator substrate, germanium on insulator substrate.

11. The semiconductor structure according to claim 9, wherein the substrate is a substrate comprising one of the following elements: Gallium arsenide, indium phosphide or silicon carbide.

12. An electronic device comprising: processor; as well as A memory coupled to the processor, the memory having instructions stored therein, the instructions causing the device to perform actions when executed by the processor, the actions comprising: Exposing a first mask and a second mask for forming a through-hole layer respectively to form a photolithographic through-hole pattern, wherein at least the first mask is alternately provided with light-transmitting portions and light-impermeable portions extending along a first direction according to a minimum design rule, and the second mask is alternately provided with light-transmitting portions and light-impermeable portions extending along a second direction perpendicular to the first direction; transferring the photolithographic via pattern into a corresponding first hard mask by etching to form a first via portion; Etching the second hard mask below the first hard mask through a third mask so that a first through-hole portion corresponding to a through-hole layer in the layout of the through-hole layer among the plurality of first through-hole portions extends into the second hard mask to form a through-hole; and A wiring layer is formed based on the layout of the wiring layer, wherein the layout of the wiring layer and the layout of the through-hole layer are designed based on the minimum design rule.

13. The electronic device according to claim 12, wherein respectively exposing a first mask and a second mask for forming the via layer to form a photolithographic via pattern comprises: A negative development technique is applied to the exposed first mask and the second mask to form the photolithographic through hole pattern in the first photoresist layer, wherein there is no etching process between the exposure of the first mask and the exposure of the second mask.

14. The electronic device of claim 13, wherein transferring the photolithographic via pattern into the corresponding first hard mask by etching to form the first via portion comprises: The stop layer is etched using a first etchant to transfer the photolithographic through hole pattern in the first photoresist layer to the stop layer, wherein the first etchant does not etch the second hard mask, and the stop layer serves as the first hard mask.

15. The electronic device according to claim 12, wherein etching the second hard mask below the first hard mask through a third mask comprises: Disposing a second photoresist layer corresponding to the through-hole layer in the layout as the third mask on the first hard mask; as well as The second hard mask is etched through the second photoresist layer so that the first via portion extends into the second hard mask to form the via.

16. The electronic device of claim 15, wherein etching the second hard mask through the second photoresist layer comprises: The additional layer is etched using a second etchant to form the via, wherein the second etchant does not etch the first hard mask and the additional layer serves as the second hard mask. 17 . The electronic device according to claim 12 , wherein the light-transmitting portions and the non-light-transmitting portions in the first mask and the second mask are both rectangular shapes having the same size.

18. The electronic device according to claim 12, wherein: The area defined by the patterns in the third mask corresponds to the area of ​​the through-hole layer in the layout, wherein the area defined by at least one pattern in the third mask corresponds to more than two of the photolithography through-hole patterns.

19. The electronic device according to any one of claims 12 to 18, wherein a material forming the second hard mask comprises at least one of the following: SiON; Si3N4.

20. A computer-readable storage medium having machine-executable instructions stored thereon, which, when executed by a processor, enables the processor to implement the method according to any one of claims 1 to 8.

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