Method, device, equipment and medium for compensating wafer surface morphology for photolithography deviation

Abstract

The present application discloses a method, device, equipment and medium for lithography deviation compensation of wafer surface morphology, and relates to the field of wafer lithography compensation technology, including: obtaining a lithography target pattern for a wafer to be compensated for lithography operation based on a design layout of the wafer to be compensated; selecting a deviation compensation value corresponding to the wafer surface morphology information of the wafer to be compensated from a preset wafer surface morphology deviation compensation rule table according to the wafer surface morphology information in the design layout; the preset wafer surface morphology deviation compensation rule table is a table generated by a model containing different wafer surface morphology information, morphology deviation factors of post-lithography photoresist three-dimensional morphology information caused by different wafer surface morphology information, and corresponding deviation compensation values; edge movement of a graphic in a lithography target pattern is performed according to the deviation compensation value to obtain a compensated lithography target pattern. The deviation compensation value obtained in the preset wafer surface morphology deviation compensation rule table generated by the model is more accurate.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer photolithography compensation, and in particular to a method, device, equipment and medium for photolithography deviation compensation of wafer surface topography. Background Art

[0002] In the photolithography process of large-scale integrated circuit manufacturing, the surface topography of the wafer (wafer topography) will significantly affect the light intensity distribution in the photoresist, thereby affecting the critical dimensions and three-dimensional morphology after photolithography, causing potential defects.

[0003] At present, the model-based chip surface morphology deviation compensation method has obvious defects in accuracy, practicality and program running speed. Compared with the case without chip surface morphology, the strict optical model simulation considering the chip surface morphology is very time-consuming and cannot be applied in actual production. Therefore, in the model-based chip surface morphology deviation compensation process, an approximate optical model is used to disassemble the chip surface morphology graphics according to the corresponding materials, and the corresponding approximate light intensity is calculated for the disassembled graphics respectively, and then the light intensity calculated from different layers is linearly superimposed to obtain the final light intensity distribution. Compared with the general optical proximity correction model, this approximate model has a large number of additional parameters, and the parameters need to be calibrated according to the chip measurement data before use.

[0004] In summary, how to achieve simple, accurate and effective compensation for the lithography deviation caused by the wafer surface morphology of the wafer is a technical problem to be solved in this field. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide a method, device, equipment and medium for compensating for lithography deviation of wafer surface topography, which can realize simple, accurate and effective compensation for lithography deviation caused by wafer surface topography. The specific scheme is as follows:

[0006] In a first aspect, the present application discloses a method for compensating for lithography deviation of wafer surface topography, comprising:

[0007] Acquiring a photolithography target pattern for performing a photolithography operation on the wafer to be compensated based on a design layout of the wafer to be compensated;

[0008] According to the line width value of the ion implantation layer, the spacing value of the ion implantation layer, and the spacing value between the wafer surface topography layer and the ion implantation layer in the design layout, a deviation compensation value corresponding to the wafer surface topography information of the wafer to be compensated is selected from a preset wafer surface topography deviation compensation rule table; the preset wafer surface topography deviation compensation rule table contains deviation compensation values ​​corresponding to topography deviation factors of different wafer surface topography information and three-dimensional topography information of photoresist after photolithography caused by different wafer surface topography information;

[0009] The edge of the pattern in the lithography target pattern is moved according to the deviation compensation value to obtain a compensated lithography target pattern.

[0010] Optionally, before selecting the deviation compensation value corresponding to the wafer surface morphology information of the wafer to be compensated from a preset wafer surface morphology deviation compensation rule table according to the ion implantation layer line width value, the ion implantation layer spacing value, and the spacing value between the wafer surface morphology layer and the ion implantation layer in the design layout, the method further includes:

[0011] Designing different types of first wafer surface topography test patterns including ion implantation layers and corresponding wafer surface topography layers;

[0012] Generate a test mask of the first wafer surface topography test pattern; the test mask includes an ion implantation layer test mask and a wafer surface topography layer test mask;

[0013] Selecting a modeling pattern for optical proximity correction and containing different wafer surface topography geometric features from the test mask;

[0014] Running an ion implantation layer photolithography process on a wafer according to the modeled pattern to collect measurement data of the modeled pattern;

[0015] Optimizing the established lithography model according to the measurement data of the modeling graph to obtain a target lithography model for generating photoresist information of different depths corresponding to different wafer surface topography;

[0016] Using the target lithography model to simulate each selected second wafer surface topography test pattern to obtain a corresponding simulation result;

[0017] Constructing a preset wafer surface topography deviation compensation rule table using the simulation results and corresponding wafer surface topography information;

[0018] Wherein, the first wafer surface topography test pattern and the second wafer surface topography test pattern both include a first pattern without wafer surface topography geometric features and a second pattern with different wafer surface topography geometric features.

[0019] Optionally, the step of running an ion implantation layer lithography process on a wafer according to the modeled pattern to collect measurement data of the modeled pattern includes:

[0020] An ion implantation layer lithography process is performed on a wafer according to the modeling pattern to collect relevant size parameters of each element of the modeling pattern as key dimensions and a cross-sectional scanning electron microscopic image of the modeling pattern.

[0021] Optionally, the step of optimizing the established lithography model according to the measurement data of the modeling graph to obtain a target lithography model for generating photoresist information of different depths corresponding to different wafer surface topography comprises:

[0022] The vertical diffusion length and photoresist module parameters in the established lithography model are optimized according to the critical dimensions of the modeled figure and the cross-sectional scanning electron microscopy image of the modeled figure to obtain a target lithography model for generating photoresist information of different depths corresponding to different chip surface morphologies.

[0023] Optionally, before optimizing the established lithography model according to the measurement data of the modeling graph to obtain a target lithography model for generating photoresist information of different depths corresponding to different wafer surface topography, the method further includes:

[0024] Using the three-dimensional optical module of the initial photolithography model to simulate the surface morphology test patterns of each wafer, so as to obtain a target three-dimensional optical module for outputting the light intensity distribution information after vertical diffusion in the photoresist;

[0025] Inputting the light intensity distribution information after vertical diffusion into the photoresist module of the initial photolithography model, so as to perform three-dimensional photoresist image generation training on the photoresist module to obtain a target photoresist module;

[0026] A lithography model is constructed based on the target three-dimensional optical module and the target photoresist module.

[0027] Optionally, simulating each selected second wafer surface topography test pattern using the target lithography model to obtain a corresponding simulation result includes:

[0028] Using the target photolithography model to simulate each selected second wafer surface topography test pattern to obtain a corresponding first three-dimensional photoresist image without wafer surface topography geometric features and a second three-dimensional photoresist image with different wafer surface topography geometric features;

[0029] Correspondingly, the use of the simulation results and the corresponding wafer surface topography information to construct a preset wafer surface topography deviation compensation rule table includes:

[0030] Determine a single-sided wafer surface topography deviation compensation value using a difference between an average critical dimension of the second three-dimensional photoresist image and an average critical dimension of the first three-dimensional photoresist image;

[0031] A preset wafer surface topography deviation compensation rule table is constructed according to each of the single-sided wafer surface topography deviation compensation values ​​and the corresponding wafer surface topography information.

[0032] Optionally, before determining the single-sided wafer surface topography deviation compensation value by using the difference between the average critical dimension of the second three-dimensional photoresist image and the average critical dimension of the first three-dimensional photoresist image, the method further includes:

[0033] Setting the sampling step size based on the thickness information of the standing wave period of the photoresist;

[0034] Starting from the bottom of the photoresist constructed based on the three-dimensional photoresist image, taking a z plane every sampling step to obtain a plurality of z planes;

[0035] The critical dimensions corresponding to each of the z planes are acquired, and all the critical dimensions are averaged to obtain average critical dimensions of the three-dimensional photoresist image.

[0036] In a second aspect, the present application discloses a lithography deviation compensation device for wafer surface topography, comprising:

[0037] A pattern design module, used for obtaining a lithography target pattern for performing a lithography operation on the wafer to be compensated based on a design layout of the wafer to be compensated;

[0038] A compensation determination module is used to select a deviation compensation value corresponding to the wafer surface morphology information of the wafer to be compensated from a preset wafer surface morphology deviation compensation rule table according to the ion implantation layer line width value, the ion implantation layer spacing value, and the spacing value between the wafer surface morphology layer and the ion implantation layer in the design layout; the preset wafer surface morphology deviation compensation rule table contains deviation compensation values ​​corresponding to morphology deviation factors of different wafer surface morphology information and three-dimensional morphology information of photoresist after photolithography caused by different wafer surface morphology information;

[0039] The pattern adjustment module is used to perform edge movement on the graphics in the lithography target pattern according to the deviation compensation value to obtain a compensated lithography target pattern.

[0040] In a third aspect, the present application discloses an electronic device, comprising:

[0041] Memory, used to store computer programs;

[0042] The processor is used to execute the computer program to implement the steps of the aforementioned disclosed method for compensating for lithography deviation of wafer surface topography.

[0043] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the aforementioned method for compensating for lithography deviations of wafer surface morphology are implemented.

[0044] It can be seen that the present application discloses a method for compensating for lithographic deviations of wafer surface morphology, including: obtaining a lithographic target pattern for a wafer to be compensated for lithographic operation based on a design layout of the wafer to be compensated; selecting a deviation compensation value corresponding to the wafer surface morphology information of the wafer to be compensated from a preset wafer surface morphology deviation compensation rule table according to the line width value of the ion implantation layer, the spacing value of the ion implantation layer, and the spacing value between the wafer surface morphology layer and the ion implantation layer in the design layout; the preset wafer surface morphology deviation compensation rule table contains the corresponding deviation compensation values ​​under the morphology deviation factors of different wafer surface morphology information and the three-dimensional morphology information of the photoresist after lithography caused by different wafer surface morphology information; and performing edge movement on the graphics in the lithographic target pattern according to the deviation compensation value to obtain the compensated lithographic target pattern. It can be seen that the present application can significantly improve the accuracy and consistency of the lithographic pattern and reduce pattern distortion and error by accurately compensating for the deviation caused by the wafer surface morphology. At the same time, because the preset chip surface morphology deviation compensation rule table contains different chip surface morphology information and the deviation compensation values ​​of multiple influencing factors of the photoresist three-dimensional morphology information under different chip surface morphology information, the deviation compensation value obtained from the table is more accurate when performing deviation compensation. At the same time, because the present invention pre-sets a preset chip surface morphology deviation compensation rule table, the compensation time is greatly reduced during the photolithography deviation compensation process of the chip surface morphology. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0046] Figure 1 A flow chart of a method for compensating for lithography deviation of wafer surface topography disclosed in the present application;

[0047] Figure 2 A wafer layer whose surface morphology is a uniform epitaxial silicon layer disclosed in the present application;

[0048] Figure 3 A wafer layer with a uniform silicon oxide surface morphology disclosed in the present application;

[0049] Figure 4 A complex pattern wafer layer comprising epitaxial silicon and silicon oxide disclosed in the present application;

[0050] Figure 5 A test pattern without a wafer surface topography layer disclosed in the present application;

[0051] Figure 6 A test pattern including a wafer surface topography layer disclosed in the present application;

[0052] Figure 7 A diagram of a method for measuring an average critical dimension from a cross-sectional profile after simulation disclosed in the present application;

[0053] Figure 8 A schematic diagram of the structure of a lithography deviation compensation device for wafer surface topography disclosed in the present application;

[0054] Fig. 9 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0056] In the photolithography process of large-scale integrated circuit manufacturing, the feature size of the ion implant layer is large and the process window is relatively large, but the surface morphology of the wafer brings additional challenges to the photolithography process of the ion implant layer. The surface morphology of the wafer will significantly affect the light intensity distribution in the photoresist, and then affect the critical dimensions and three-dimensional morphology after photolithography, causing potential defects. Therefore, in the process of generating the mask data of the ion implant layer, it is necessary to compensate for the influence of the wafer surface morphology on the critical dimensions, so that the critical dimensions after photolithography are as close to the target dimensions as possible.

[0057] At present, the model-based chip surface morphology deviation compensation method has obvious defects in accuracy, practicality and program running speed. Compared with the case without chip surface morphology, the strict optical model simulation considering the chip surface morphology is very time-consuming and cannot be applied in actual production. Therefore, in the model-based chip surface morphology deviation compensation process, an approximate optical model is used to disassemble the chip surface morphology graphics according to the corresponding materials, and the corresponding approximate light intensity is calculated for the disassembled graphics respectively, and then the light intensity calculated from different layers is linearly superimposed to obtain the final light intensity distribution. Compared with the general optical proximity correction model, this approximate model has a large number of additional parameters, and the parameters need to be calibrated according to the chip measurement data before use.

[0058] To this end, the present invention provides a lithography deviation compensation solution for wafer surface topography, which can achieve simple, accurate and effective compensation for the lithography deviation caused by the wafer surface topography.

[0059] Reference Figure 1 As shown, an embodiment of the present invention discloses a method for compensating for lithography deviation of wafer surface topography, comprising:

[0060] Step S11: obtaining a lithography target pattern for performing a lithography operation on the wafer to be compensated based on the design layout of the wafer to be compensated.

[0061] In this embodiment, when semiconductor wafers are manufactured, silicon substrates are usually used as the basic materials in semiconductor manufacturing, usually high-purity single-crystal silicon wafers. It provides support for the subsequent construction of various electronic components and circuits thereon. Then a corresponding layer of silicon material is formed on the silicon substrate, generally epitaxial silicon or silicon oxide, or a composite material of epitaxial silicon and silicon oxide. This layer of silicon material has a specific crystal structure and electrical properties to meet specific device performance requirements. Then there is a photoresist layer, which is used in the photolithography process. Through specific exposure and development processes, the photoresist can form a pattern corresponding to the design pattern. This helps to accurately transfer the circuit design to the material layer below. When light is irradiated to a specific area of ​​the photoresist, its chemical properties change and it is dissolved or retained during the development process, thereby forming the desired pattern. A top anti-reflection layer is usually set on the photoresist layer to reduce the reflection of light on the surface during the photolithography process through the ion implantation layer, thereby improving the resolution and accuracy of the photolithography. It enables light to penetrate the photoresist more evenly and reduce unnecessary interference and scattering. As Figure 2 As shown in FIG. 1 , the silicon material layer on the silicon substrate is a wafer layer structure of a uniform epitaxial silicon layer, wherein the epitaxial silicon is a layer of silicon material formed on the silicon substrate by an epitaxial growth process. Figure 3 As shown in FIG. 1 , the silicon material layer on the silicon substrate is a wafer layer structure in which the silicon oxide layer is a uniform silicon oxide layer, wherein the silicon oxide is a silicon oxide film formed on the surface of the silicon substrate by thermal oxidation or chemical vapor deposition. Figure 4 The figure shows the wafer layer structure in which the silicon material layer on the silicon substrate is a complex pattern layer (including uneven epitaxial silicon and silicon oxide). It can be seen that the surface morphology of the wafer layer (mainly the uneven morphology of the composite silicon material under the photoresist layer and between the silicon substrate) will have a significant impact on the photolithography process. Therefore, the designed photolithography target pattern is subjected to deviation compensation processing according to the wafer surface morphology.

[0062] In this embodiment, a photolithography target pattern of the wafer to be compensated under the design layout is obtained, that is, a post-photolithography target pattern of the ion implantation layer.

[0063] Step S12: selecting a deviation compensation value corresponding to the wafer surface morphology information of the wafer to be compensated from a preset wafer surface morphology deviation compensation rule table according to the ion implantation layer line width value, the ion implantation layer spacing value, and the spacing value between the wafer surface morphology layer and the ion implantation layer in the design layout; the preset wafer surface morphology deviation compensation rule table includes deviation compensation values ​​corresponding to morphology deviation factors of different wafer surface morphology information and three-dimensional morphology information of photoresist after lithography caused by different wafer surface morphology information.

[0064] In this embodiment, the wafer surface topography layer is a silicon oxide layer. Figure 5 As shown, due to Figure 5 Design a layout for test patterns without wafer surface topography layers, thus enabling Figure 5 Get the ion implantation layer line width value W in the design layout 1 , the ion implantation layer spacing value S between the ion implantation layers 1 , and facing Figure 6 The test pattern design layout containing the wafer surface topography layer in the wafer surface topography layer can obtain the wafer surface topography layer pattern width W 2 (Wherein, the width of the wafer surface topography layer pattern W 2 It is the variable that has the smallest impact on the lithography deviation. Therefore, when compensating for the lithography deviation, this variable information is ignored). The distance S between the ion implantation layer and the wafer surface topography layer 2 Therefore, when facing a design layout with a wafer surface topography layer, it is necessary to obtain W in the design layout. 1 S 1 S 2 Information, select the corresponding deviation compensation value from the preset chip surface morphology deviation compensation rule table.

[0065] In this embodiment, before selecting the deviation compensation value corresponding to the wafer surface morphology information of the wafer to be compensated from the preset wafer surface morphology deviation compensation rule table according to the ion implantation layer line width value, the ion implantation layer spacing value, and the spacing value between the wafer surface morphology layer and the ion implantation layer in the design layout, it also includes: designing different types of first wafer surface morphology test patterns including ion implantation layers and corresponding wafer surface morphology layers; generating a test mask for the first wafer surface morphology test pattern; the test mask including an ion implantation layer test mask and a wafer surface morphology layer test mask; selecting a modeling pattern for optical proximity correction and including different wafer surface morphology geometric features from the test mask; and performing the modeling according to the modeling. The pattern runs an ion implantation layer lithography process on a wafer to collect the measurement data of the modeled pattern; the established lithography model is optimized according to the measurement data of the modeled pattern to obtain a target lithography model for generating photoresist information of different depths corresponding to different wafer surface morphologies; the target lithography model is used to simulate each selected second wafer surface morphology test pattern to obtain corresponding simulation results; a preset wafer surface morphology deviation compensation rule table is constructed using the simulation results and the corresponding wafer surface morphology information; wherein the first wafer surface morphology test pattern and the second wafer surface morphology test pattern both include a first pattern without wafer surface morphology geometric features and a second pattern with different wafer surface morphology geometric features. It can be understood that the first wafer surface morphology test pattern is designed first. The test pattern includes an ion implantation layer and a corresponding wafer surface morphology related layer, such as an active layer or a silicon oxide layer. The design of the ion implantation layer pattern is similar to a standard optical proximity correction test pattern. For the same ion implantation layer pattern, it is necessary to include a pattern without a wafer surface morphology layer and a pattern with different wafer surface morphology layer geometric features, such as Figure 5 and Figure 6 shown. Figure 6 The one-dimensional test pattern shown contains four geometric features: the line width W of the ion implantation layer 1 、Ion implantation layer spacing S 1 , the line width W of the chip surface morphology layer 2 and the distance S between the wafer surface topography layer and the ion implantation layer 2 After the design of the first wafer surface morphology test pattern is completed, the corresponding test mask is generated, including the test mask of the ion implantation layer and the surface morphology related layer. Then, the modeling pattern is selected from the test mask. In addition to the commonly used modeling pattern for optical proximity correction, the modeling pattern must also cover different wafer surface morphology geometric features, especially the spacing S between different wafer surface morphology layers and ion implantation layers. 2Then run the standard ion implantation layer lithography process and collect the measurement data of the modeled pattern on the post-lithography wafer.

[0066] In this embodiment, the ion implantation layer lithography process is run on the wafer according to the modeling pattern to collect the measurement data of the modeling pattern, including: running the ion implantation layer lithography process on the wafer according to the modeling pattern to collect the relevant size parameters of each element of the modeling pattern as the critical dimension and the cross-sectional scanning electron microscopy image of the modeling pattern. It can be understood that in addition to the critical dimensions (Critical Dimension, i.e. CD) of all modeling patterns, the measurement data also needs to include cross-sectional scanning electron microscopy (Cross-sectional SEM) images of a small number of modeling patterns to verify the model's prediction of the three-dimensional photoresist morphology.

[0067] In the present embodiment, the photolithography model established according to the measurement data of the modeling figure is optimized to obtain a target photolithography model for generating photoresist information of different depths corresponding to different wafer surface topography, including: optimizing the vertical diffusion length and photoresist module parameters in the photolithography model established according to the critical size of the modeling figure and the cross-sectional scanning electron microscopic image of the modeling figure to obtain a target photolithography model for generating photoresist information of different depths corresponding to different wafer surface topography. It is understandable that the module parameters of the vertical diffusion length L and the target photoresist module are optimized according to the critical size of all modeling figures obtained and the cross-sectional scanning electron microscopic image of a small amount of modeling figures. The optimization of module parameters is similar to the method for optimizing the existing optical proximity correction model parameters, and will not be repeated here.

[0068] In this embodiment, before the established lithography model is optimized according to the measurement data of the modeling figure to obtain the target lithography model for generating photoresist information of different depths corresponding to different chip surface morphologies, it also includes: using the three-dimensional optical module of the initial lithography model to simulate each chip surface morphology test figure to obtain a target three-dimensional optical module for outputting the light intensity distribution information after vertical diffusion in the photoresist; inputting the light intensity distribution information after vertical diffusion into the photoresist module of the initial lithography model so as to perform three-dimensional photoresist image generation training on the photoresist module to obtain the target photoresist module; and constructing a lithography model based on the target three-dimensional optical module and the target photoresist module. It can be understood that the initial lithography model is constructed based on the three-dimensional optical module and the photoresist module. Specifically, the three-dimensional optical module is a strict physical model used to calculate the three-dimensional light intensity distribution of the modeling figure. The physical model can be applied to the simulation of a complex chip surface morphology. Commonly used modeling algorithms include Finite-Difference Time-Domain (FDTD) and Rigorous Coupled Wave Analysis (RCWA). The three-dimensional optical module constructed by the physical model is trained according to the selected modeling algorithm and the wafer surface morphology test pattern to obtain the target three-dimensional optical module. It should be pointed out that the calculation in this step is time-consuming. Therefore, after the design of the wafer surface morphology test pattern is completed, the subsequent modeling pattern selection and model construction work can be started. After the mask manufacturing, running the lithography-related processes and wafer data measurement are completed, the three-dimensional light intensity distribution calculation of the modeling pattern has been completed, which will not affect the entire task cycle. After obtaining the light intensity distribution in the photoresist After that, the light intensity distribution after vertical diffusion is obtained according to the following formula: :

[0069] ;

[0070] in, represents the vertical diffusion length, represents convolution, Represents three-dimensional space coordinates.

[0071] Furthermore, based on the obtained light intensity distribution after vertical diffusion , establish a photoresist module, which is consistent with the one used in the optical proximity correction model. According to the light intensity distribution after vertical diffusion and the target photoresist module to obtain a three-dimensional photoresist image , as shown in the following formula:

[0072] ;

[0073] in, Indicates the distribution of light intensity The calculated photoresist model term j, express The corresponding linear coefficient is It represents the threshold of the target three-dimensional photoresist module. The post-lithography profile can be obtained through the three-dimensional photoresist image and the threshold.

[0074] In this embodiment, the target photolithography model is used to simulate each selected second chip surface morphology test pattern to obtain corresponding simulation results, including: using the target photolithography model to simulate each selected second chip surface morphology test pattern to obtain a corresponding first three-dimensional photoresist image without chip surface morphology geometric features and a second three-dimensional photoresist image with different chip surface morphology geometric features; accordingly, the simulation results and the corresponding chip surface morphology information are used to construct a preset chip surface morphology deviation compensation rule table, including: using the difference between the average critical size of the second three-dimensional photoresist image and the average critical size of the first three-dimensional photoresist image to determine a single-sided chip surface morphology deviation compensation value; and constructing a preset chip surface morphology deviation compensation rule table according to each of the single-sided chip surface morphology deviation compensation values ​​and the corresponding chip surface morphology information. It can be understood that after obtaining the target photolithography model including the target three-dimensional optical module and the target photoresist module, the target photolithography model is used to model and simulate the selected second chip surface morphology test pattern. It should be noted that in order to ensure coverage, the number of the second chip surface morphology test patterns is much larger than the number of the first chip surface morphology test patterns. Then, the target photolithography model is used to simulate the second chip surface morphology test pattern to obtain a simulated three-dimensional photoresist image. Since the second chip surface morphology test pattern covers test patterns without chip surface morphology geometric features and test patterns with different chip surface morphology geometric features, the simulated result is the first three-dimensional photoresist image and the second three-dimensional photoresist image. Then, according to the difference between the average critical dimensions of each of the two three-dimensional photoresist images, the unilateral deviation compensation value is determined. The formula for determining the unilateral deviation compensation value is as follows:

[0075] ;

[0076] in, represents the average critical dimension of the second three-dimensional photoresist pattern, represents an average critical dimension of the first three-dimensional photoresist image.

[0077] A plurality of two-dimensional tables are constructed according to different wafer morphology characteristic variables corresponding to the unilateral deviation compensation values ​​to construct a preset wafer surface morphology deviation compensation rule table.

[0078] In this embodiment, before determining the single-sided wafer surface morphology deviation compensation value using the difference between the average critical dimension of the second three-dimensional photoresist image and the average critical dimension of the first three-dimensional photoresist image, it also includes: setting a sampling step based on the thickness information of the standing wave period of the photoresist; taking a z plane every said sampling step from the bottom of the photoresist constructed based on the three-dimensional photoresist image to obtain a plurality of z planes; obtaining the critical dimensions corresponding to each of said z planes, and averaging all said critical dimensions to obtain the average critical dimensions of said three-dimensional photoresist image. It can be understood that, if Figure 7 As shown, the thickness of one standing wave period of the photoresist is set to t 0 , with t 0 / (2*N) is the sampling step length, where N is a positive integer. Starting from the bottom of the photoresist, a z plane is taken every other step length, and the corresponding key dimension value on the z plane is obtained. Finally, the average value of all the key dimensions obtained is calculated, which is the average key dimension. It should be noted that when selecting t 0 / (2*N) is the sampling step length, which ensures that the maximum and minimum values ​​of the key dimensions of the cross section are captured, ensuring the reliability of the data.

[0079] Step S13: performing edge movement on the pattern in the lithography target pattern according to the deviation compensation value to obtain a compensated lithography target pattern.

[0080] In this embodiment, the compensated lithography target pattern is obtained by running the deviation compensation program and moving the edge of the lithography target pattern according to the deviation compensation value selected from the table. If the deviation compensation value indicates that the line width corresponding to a certain edge of a target pattern polygon needs to be increased by a certain value, the deviation compensation program will move the edge to the outside of the polygon by a corresponding distance accordingly. This polygon edge movement is automatically completed in the computer software to ensure the accuracy and efficiency of the compensation.

[0081] It can be seen that the present invention uses the measurement data of a relatively small number of graphics to calibrate the model (target lithography model), and then simulates a large number of graphics based on the calibrated model to obtain the deviation compensation value, which greatly improves the efficiency of table building and the coverage of table building sampling; at the same time, a strict optical model is used with vertical diffusion and a calibrated optical proximity correction photoresist model, and wafer data is used for training to ensure the accuracy of the model, which greatly improves the accuracy and consistency of the lithography deviation simulation of different wafer surface morphology graphics. Finally, the compensation value is calculated based on the average critical dimension, which further improves the accuracy of the deviation compensation.

[0082] It can be seen that the present application discloses a method for compensating for lithographic deviations of wafer surface morphology, including: obtaining a lithographic target pattern for a wafer to be compensated for lithographic operation based on a design layout of the wafer to be compensated; selecting a deviation compensation value corresponding to the wafer surface morphology information of the wafer to be compensated from a preset wafer surface morphology deviation compensation rule table according to the line width value of the ion implantation layer, the spacing value of the ion implantation layer, and the spacing value between the wafer surface morphology layer and the ion implantation layer in the design layout; the preset wafer surface morphology deviation compensation rule table contains the corresponding deviation compensation values ​​under the morphology deviation factors of different wafer surface morphology information and the three-dimensional morphology information of the photoresist after lithography caused by different wafer surface morphology information; and performing edge movement on the graphics in the lithographic target pattern according to the deviation compensation value to obtain the compensated lithographic target pattern. It can be seen that the present application can significantly improve the accuracy and consistency of the lithographic pattern and reduce pattern distortion and error by accurately compensating for the deviation caused by the wafer surface morphology. At the same time, because the preset chip surface morphology deviation compensation rule table contains different chip surface morphology information and the deviation compensation values ​​of multiple influencing factors of the photoresist three-dimensional morphology information under different chip surface morphology information, the deviation compensation value obtained from the table is more accurate when performing deviation compensation. At the same time, because the present invention pre-sets the preset chip surface morphology deviation compensation rule table, the compensation time is greatly reduced during the photolithography deviation compensation process of the chip surface morphology.

[0083] Reference Figure 8 As shown, the present invention accordingly discloses a lithography deviation compensation device for wafer surface topography, comprising:

[0084] The pattern design module 11 is used to obtain a lithography target pattern for performing a lithography operation on the wafer to be compensated based on a design layout of the wafer to be compensated;

[0085] The compensation determination module 12 is used to select a deviation compensation value corresponding to the wafer surface morphology information of the wafer to be compensated from a preset wafer surface morphology deviation compensation rule table according to the ion implantation layer line width value, the ion implantation layer spacing value, and the spacing value between the wafer surface morphology layer and the ion implantation layer in the design layout; the preset wafer surface morphology deviation compensation rule table contains deviation compensation values ​​corresponding to the morphology deviation factors of the three-dimensional morphology information of the photoresist after lithography caused by different wafer surface morphology information;

[0086] The pattern adjustment module 13 is used to perform edge shifting on the graphics in the lithography target pattern according to the deviation compensation value to obtain a compensated lithography target pattern.

[0087] It can be seen that the present application discloses a method of obtaining a lithography target pattern for a wafer to be compensated for a lithography operation based on a design layout of the wafer to be compensated; selecting a deviation compensation value corresponding to the wafer surface morphology information of the wafer to be compensated from a preset wafer surface morphology deviation compensation rule table according to the line width value of the ion implantation layer, the spacing value of the ion implantation layer, and the spacing value between the wafer surface morphology layer and the ion implantation layer in the design layout; the preset wafer surface morphology deviation compensation rule table contains deviation compensation values ​​corresponding to the morphology deviation factors of the three-dimensional morphology information of the photoresist after lithography caused by different wafer surface morphology information and different wafer surface morphology information; and performing edge movement on the graphics in the lithography target pattern according to the deviation compensation value to obtain the compensated lithography target pattern. It can be seen that the present application can significantly improve the accuracy and consistency of the lithography pattern and reduce pattern distortion and error by accurately compensating for the deviation caused by the wafer surface morphology. At the same time, because the preset chip surface morphology deviation compensation rule table contains different chip surface morphology information and the deviation compensation values ​​of multiple influencing factors of the photoresist three-dimensional morphology information under different chip surface morphology information, the deviation compensation value obtained from the table is more accurate when performing deviation compensation. At the same time, because the present invention pre-sets the preset chip surface morphology deviation compensation rule table, the compensation time is greatly reduced during the photolithography deviation compensation process of the chip surface morphology.

[0088] Furthermore, the present application also discloses an electronic device. Fig. 9 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be considered as any limitation on the scope of use of the present application.

[0089] Fig. 9 A schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the lithography deviation compensation method for the wafer surface morphology disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0090] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0091] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0092] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0093] Among them, the operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device 20, so as to realize the operation and processing of the massive data 223 in the memory 22 by the processor 21, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the lithography deviation compensation method of the wafer surface morphology performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks. In addition to data transmitted from an external device received by the electronic device, the data 223 can also include data collected by its own input and output interface 25.

[0094] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the aforementioned disclosed method for compensating the lithography deviation of the wafer surface morphology is implemented. The specific steps of the method can be referred to the corresponding contents disclosed in the aforementioned embodiments, and will not be repeated here.

[0095] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0096] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application. The steps of the method or algorithm described in conjunction with the embodiments disclosed herein can be implemented directly with hardware, a software module executed by a processor, or a combination of the two. The software module can be placed in a random access memory RAM (Random Access Memory), memory, read-only memory ROM (Read Only Memory), electrically programmable EPROM (Electrically Programmable Read Only Memory), electrically erasable programmable EEPROM (ElectricErasable Programmable Read Only Memory), register, hard disk, removable disk, CD-ROM (CompactDisc-Read Only Memory), or any other form of storage medium known in the technical field.

[0097] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0098] The scheme provided by the present invention is introduced in detail above. Specific examples are used in this article to illustrate the principle and implementation mode of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for compensating for lithography deviation of wafer surface topography, characterized in that: include: Acquiring a photolithography target pattern for performing a photolithography operation on the wafer to be compensated based on a design layout of the wafer to be compensated; According to the line width value of the ion implantation layer, the spacing value of the ion implantation layer, and the spacing value between the wafer surface topography layer and the ion implantation layer in the design layout, a deviation compensation value corresponding to the wafer surface topography information of the wafer to be compensated is selected from a preset wafer surface topography deviation compensation rule table; the preset wafer surface topography deviation compensation rule table contains deviation compensation values ​​corresponding to topography deviation factors of different wafer surface topography information and three-dimensional topography information of photoresist after photolithography caused by different wafer surface topography information; Performing edge movement on a pattern in the lithography target pattern according to the deviation compensation value to obtain a compensated lithography target pattern; Before selecting the deviation compensation value corresponding to the wafer surface topography information of the wafer to be compensated from a preset wafer surface topography deviation compensation rule table according to the ion implantation layer line width value, the ion implantation layer spacing value, and the spacing value between the wafer surface topography layer and the ion implantation layer in the design layout, the method further includes: Designing different types of first wafer surface topography test patterns including ion implantation layers and corresponding wafer surface topography layers; Generate a test mask of the first wafer surface topography test pattern; the test mask includes an ion implantation layer test mask and a wafer surface topography layer test mask; Selecting a modeling pattern for optical proximity correction and containing different wafer surface topography geometric features from the test mask; Running an ion implantation layer photolithography process on a wafer according to the modeled pattern to collect measurement data of the modeled pattern; Optimizing the established lithography model according to the measurement data of the modeling graph to obtain a target lithography model for generating photoresist information of different depths corresponding to different wafer surface topography; Using the target lithography model to simulate each selected second wafer surface topography test pattern to obtain a corresponding simulation result; Constructing a preset wafer surface topography deviation compensation rule table using the simulation results and corresponding wafer surface topography information; Among them, the first chip surface morphology test pattern and the second chip surface morphology test pattern both include a first pattern without chip surface morphology geometric features and a second pattern with different chip surface morphology geometric features; the second chip surface morphology test pattern is a test pattern selected for establishing a preset chip surface morphology deviation compensation rule table.

2. The method for compensating wafer surface lithography deviation according to claim 1, characterized in that: The step of running an ion implantation layer photolithography process on a wafer according to the modeled pattern to collect measurement data of the modeled pattern includes: An ion implantation layer lithography process is performed on a wafer according to the modeling pattern to collect relevant size parameters of each element of the modeling pattern as key dimensions and a cross-sectional scanning electron microscopic image of the modeling pattern.

3. The method for compensating wafer surface lithography deviation according to claim 2, characterized in that: The method of optimizing the established lithography model according to the measurement data of the modeling graph to obtain a target lithography model for generating photoresist information of different depths corresponding to different wafer surface topography comprises: The vertical diffusion length and photoresist module parameters in the established lithography model are optimized according to the critical dimensions of the modeled figure and the cross-sectional scanning electron microscopy image of the modeled figure to obtain a target lithography model for generating photoresist information of different depths corresponding to different chip surface morphologies.

4. The method for compensating wafer surface lithography deviation according to claim 1, characterized in that: Before optimizing the established lithography model according to the measurement data of the modeling graph to obtain a target lithography model for generating photoresist information of different depths corresponding to different wafer surface topography, the method further includes: Using the three-dimensional optical module of the initial photolithography model to simulate the surface morphology test patterns of each wafer, so as to obtain a target three-dimensional optical module for outputting the light intensity distribution information after vertical diffusion in the photoresist; Inputting the light intensity distribution information after vertical diffusion into the photoresist module of the initial photolithography model, so as to perform three-dimensional photoresist image generation training on the photoresist module to obtain a target photoresist module; A lithography model is constructed based on the target three-dimensional optical module and the target photoresist module.

5. The method for compensating wafer surface lithography deviation according to claim 1, characterized in that: The method of simulating each selected second wafer surface topography test pattern using the target lithography model to obtain a corresponding simulation result includes: Using the target photolithography model to simulate each selected second wafer surface topography test pattern to obtain a corresponding first three-dimensional photoresist image without wafer surface topography geometric features and a second three-dimensional photoresist image with different wafer surface topography geometric features; Correspondingly, the use of the simulation results and the corresponding wafer surface topography information to construct a preset wafer surface topography deviation compensation rule table includes: Determine a single-sided wafer surface topography deviation compensation value using a difference between an average critical dimension of the second three-dimensional photoresist image and an average critical dimension of the first three-dimensional photoresist image; A preset wafer surface topography deviation compensation rule table is constructed according to each of the single-sided wafer surface topography deviation compensation values ​​and the corresponding wafer surface topography information.

6. The method for compensating the lithography deviation of the wafer surface morphology according to claim 5, characterized in that: Before determining the single-sided wafer surface topography deviation compensation value by using the difference between the average critical dimension of the second three-dimensional photoresist image and the average critical dimension of the first three-dimensional photoresist image, the method further includes: Setting the sampling step size based on the thickness information of the standing wave period of the photoresist; Starting from the bottom of the photoresist constructed based on the three-dimensional photoresist image, taking a z plane every sampling step to obtain a plurality of z planes; The critical dimensions corresponding to each of the z planes are acquired, and all the critical dimensions are averaged to obtain average critical dimensions of the three-dimensional photoresist image.

7. A device for compensating wafer surface morphology for photolithography deviation, characterized in that: include: A pattern design module, used for obtaining a lithography target pattern for performing a lithography operation on the wafer to be compensated based on a design layout of the wafer to be compensated; A compensation determination module is used to select a deviation compensation value corresponding to the wafer surface morphology information of the wafer to be compensated from a preset wafer surface morphology deviation compensation rule table according to the ion implantation layer line width value, the ion implantation layer spacing value, and the spacing value between the wafer surface morphology layer and the ion implantation layer in the design layout; the preset wafer surface morphology deviation compensation rule table contains deviation compensation values ​​corresponding to morphology deviation factors of different wafer surface morphology information and three-dimensional morphology information of photoresist after photolithography caused by different wafer surface morphology information; A pattern adjustment module, used for performing edge movement on a pattern in the lithography target pattern according to the deviation compensation value to obtain a compensated lithography target pattern; The wafer surface topography photolithography deviation compensation device is used to design different types of first wafer surface topography test patterns including ion implantation layers and corresponding wafer surface topography layers; Generating a test mask of the first wafer surface topography test pattern; The test mask includes an ion implantation layer test mask and a wafer surface topography layer test mask; a modeling pattern for optical proximity correction and including different wafer surface topography geometric features is selected from the test mask; Running an ion implantation layer lithography process on a wafer according to the modeling pattern to collect measurement data of the modeling pattern; optimizing the established lithography model according to the measurement data of the modeling pattern to obtain a target lithography model for generating photoresist information of different depths corresponding to different wafer surface topography; The target lithography model is used to simulate each selected second chip surface morphology test pattern to obtain corresponding simulation results; the simulation results and the corresponding chip surface morphology information are used to construct a preset chip surface morphology deviation compensation rule table; wherein the first chip surface morphology test pattern and the second chip surface morphology test pattern both include a first pattern without chip surface morphology geometric features and a second pattern with different chip surface morphology geometric features; the second chip surface morphology test pattern is a test pattern selected for establishing a preset chip surface morphology deviation compensation rule table.

8. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor is used to execute the computer program to implement the steps of the method for compensating the lithography deviation of the wafer surface morphology as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: Used to store computer programs; wherein, when the computer program is executed by a processor, the steps of the method for compensating the lithography deviation of the wafer surface morphology as described in any one of claims 1 to 6 are implemented.

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