Dual-core heterogeneous distributed system controller, redundant control system and method

Abstract

The present invention discloses a dual-core heterogeneous distributed system controller, a redundant control system and a method, and relates to the technical field of control systems. It includes an X86 architecture processor and an FPGA architecture processor, the FPGA architecture processor includes a plurality of on-chip external logic blocks, the X86 architecture processor and the plurality of on-chip external logic blocks of the FPGA architecture processor are respectively connected, and the on-chip external logic blocks are used to be mapped to the IO space of the X86 architecture processor. The dual-core heterogeneous distributed system controller of the present invention adopts the interaction mode of the X86 processor and the FPGA processor, the FPGA processor can realize customization for different requirements, the signal processing efficiency is higher, and the communication interface is expandable, and the hardware cost is also low. The redundant logic design of the FPGA processor in the redundant control system solves the problem of paralysis of the nuclear power control system caused by the simultaneous failure of the redundant communication of the two machines.

Description

Technical Field

[0001] The present invention belongs to the technical field of control systems, and in particular to a distributed system controller, a redundant control system and a method based on dual-core heterogeneity. Background Art

[0002] Distributed Control System, or DCS system controller for short. In the current domestic DCS system nuclear power plants, the I / O processor CommControl™ chip of the FCP270 controller module is implemented in a customized application-specific integrated circuit (ASIC). The chip integrates an X86 processor and multiple on-chip peripheral logic blocks to control external devices. TM Chip manufacturers have basically stopped production, existing devices and spare parts are seriously aged, and the supply of dedicated integrated circuit chips is difficult, which cannot meet the requirements of long-term stable operation of nuclear power plants.

[0003] In addition, in order to ensure the long-term stable operation of the system, the DCS system is equipped with redundancy. One controller acts as the host to provide data services to the outside world, and the other acts as a slave, running the same application as the host. When the host fails, the slave will take over the control and become the master station to continue communicating with peripheral devices. The two machines perform redundant control in a master-slave manner, which greatly reduces the probability of control system paralysis in nuclear power plants, but it still cannot avoid the problem of nuclear power plant control system paralysis caused by failures of both controllers at the same time. Summary of the invention

[0004] The object of the present invention is to provide a dual-core heterogeneous distributed system controller, redundant control system and method, wherein the dual-core heterogeneous distributed system controller adopts the interaction between X86 processor and FPGA processor to realize and replace the functions of the above-mentioned ASIC chip. The FPGA processor can realize customization for different needs, and the signal processing efficiency is higher than that of modifying the software program, and the communication interface is expandable, and the hardware cost is also low. In addition, the redundant logic design of the FPGA processor in the redundant control system solves the problem of nuclear power control system paralysis caused by the simultaneous failure of the original FCP270 dual-machine redundant communication.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] A first aspect of the present invention provides a dual-core heterogeneous distributed system controller.

[0007] A dual-core heterogeneous distributed system controller includes an X86 architecture processor and an FPGA architecture processor, wherein the FPGA architecture processor includes multiple on-chip external logic blocks, the X86 architecture processor is respectively connected to the multiple on-chip external logic blocks of the FPGA architecture processor, and the on-chip external logic blocks are used to be mapped to the IO space of the X86 architecture processor.

[0008] As an optional technical solution, the plurality of on-chip peripheral logic blocks are respectively used to connect to external devices.

[0009] As an optional technical solution, the on-chip peripheral logic block includes two HDLC modules, a UART module, a FIOC module and a DUAL TONE module. The two HDLC modules are connected to the X86 architecture processor via a data bus, and the UART module, FIOC module, DUAL TONE module are connected to the X86 architecture processor via a data bus and an address bus respectively.

[0010] As an optional technical solution, the on-chip peripheral logic block is connected to the X86 architecture processor via chip selection and read-write control connection lines.

[0011] As an optional technical solution, the HDLC module is a high-level data link control interface module, which is used to interact with the X86 architecture processor through interruption; the UART module is an asynchronous transceiver communication module, which interacts with the X86 architecture processor through polling; the DUAL TONE module is a dual-tone multi-frequency communication module, which is used to control an external frequency modulation circuit.

[0012] As an optional technical solution, the X86 architecture processor is externally connected with FLASH and SRAM memories, and the FLASH and SRAM memories are used to be mapped to the memory address space of the X86 architecture processor.

[0013] As an optional technical solution, the FLASH, SRAM memory and the X86 architecture processor are connected via a data bus, an address bus, and chip selection and read-write control connection lines.

[0014] A second aspect of the present invention provides a redundant control system.

[0015] A redundant control system, comprising two dual-core heterogeneous distributed system controllers as described in the first aspect, wherein one distributed system controller serves as a host, and the other distributed system controller serves as a slave, wherein the CPU of the host is connected to the FPGA of the host and the FPGA of the slave respectively, and the CPU of the slave is connected to the FPGA of the slave and the FPGA of the host respectively, and the host and the slave communicate via RS485;

[0016] The FPGA of the slave is used to monitor the CPU status of the host and the CPU status of the slave respectively, and when the CPU of the host and the CPU of the slave fail at the same time, an alarm message with the highest priority is issued;

[0017] The FPGA of the host is used to release the control instructions in the internal cache before the CPU failure when the CPU of the host and the CPU of the slave fail at the same time, and to run the original instructions stored in itself to stabilize the current control state.

[0018] As an optional technical solution, the FPGA of the slave machine is also used to notify the slave machine's CPU to take back the initiative of peripheral device control, restart the failed host CPU, switch the master and slave machines through RS485, and send out an alarm signal when it detects that only the host machine's CPU has failed.

[0019] A third aspect of the present invention provides a redundancy control method.

[0020] The redundant control method includes the FPGA of the slave machine monitoring the CPU status of the master machine and the CPU status of the slave machine respectively:

[0021] When the CPU of the host and the CPU of the slave fail at the same time, the FPGA of the slave sends out the highest priority alarm information; at this time, the FPGA of the host completes the release of the control instructions in the internal cache before the CPU failure, and runs the original instructions stored in itself to stabilize the current control state;

[0022] When the FPGA of the slave detects that only the CPU of the host fails, it notifies the CPU of the slave to take back the initiative of controlling the peripheral devices, restarts the failed host CPU, switches the master and slave through RS485, and sends out an alarm signal.

[0023] The present invention has the following beneficial effects:

[0024] 1. The present invention provides a dual-core heterogeneous distributed system controller, redundant control system and method, wherein the dual-core heterogeneous distributed system controller uses an X86 processor and an FPGA processor to interact to realize and replace the functions of the ASIC chip in the existing nuclear power control system. The FPGA processor can be customized for different needs, and the signal processing efficiency is higher than modifying the software program, and the communication interface is expandable, and the hardware cost is also low. The controller can be used in applications with high system performance requirements and has broad application prospects.

[0025] 2. In the redundant control system of the present invention, one distributed system controller serves as a host and the other distributed system controller serves as a slave. The CPU of the host is connected to the FPGA of the host and the FPGA of the slave respectively, and the CPU of the slave is connected to the FPGA of the slave and the FPGA of the host respectively, thereby realizing self-connection and interconnection of the status monitoring of the host CPU and the slave CPU, and realizing effective monitoring when one of the controllers fails or both controllers fail.

[0026] 3. In the redundant control system of the present invention, the FPGA of the slave monitors the CPU status of the host and the CPU status of the slave respectively. When the CPU of the host and the CPU of the slave fail at the same time, the highest priority alarm information is issued; when it is detected that only the CPU of the host fails, the CPU of the slave is notified to take back the initiative of peripheral device control, restart the failed host CPU, switch the master and slave through RS485, and issue an alarm signal. The redundant logic design of the FPGA processor solves the problem of nuclear power control system paralysis caused by the simultaneous failure of the redundant communication of the original FCP270 dual machines.

[0027] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0029] Figure 1 The hardware connection block diagram of the AM186EM processor of the first embodiment.

[0030] Figure 2 This is a memory address mapping diagram based on byte addressing of the AM186EM processor of Example 1.

[0031] Figure 3 This is an IO memory mapping diagram based on byte addressing of the AM186EM processor of Example 1.

[0032] Figure 4 It is a structural block diagram of the AM186EM processor of Example 1.

[0033] Figure 5 This is a diagram of the interaction architecture between the AM186EM processor and the FPGA processor in Example 1.

[0034] Figure 6This is a diagram of the dual-machine redundant interaction architecture of the distributed system controller of Example 2. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] Embodiment 1:

[0037] See also Figure 3 and Figure 5 As shown, this embodiment provides a distributed system controller based on dual-core heterogeneity, including an X86 architecture processor and an FPGA architecture processor, the FPGA architecture processor including multiple on-chip external logic blocks, the X86 architecture processor and the multiple on-chip external logic blocks of the FPGA architecture processor are respectively connected, and the multiple on-chip external logic blocks are respectively used to connect external devices; the on-chip external logic blocks are used to be mapped to the IO space of the X86 architecture processor.

[0038] In this embodiment, the processor based on FPGA architecture uses XC6SLX9-2 device, and uses Verilog HDL hardware description language for circuit design, which is mainly used to realize the logic block functions of the original ASIC chip. Figure 5 As shown, the on-chip peripheral logic block may specifically include two HDLC modules, a UART module, a FIOC module and a DUAL TONE module. The two HDLC modules are respectively an HDLC0 module and an HDLC1 module. The HDLC0 module and the HDLC1 module are connected to the X86 architecture processor via a data bus. The UART module, the FIOC module, and the DUAL TONE module are connected to the X86 architecture processor via a data bus and an address bus respectively.

[0039] exist Figure 5 In the figure, there are two vertical lines inside the FPGA chip (one is a long line and the other is a short line). The long line represents the on-chip data bus and the short line represents the on-chip address bus. Each internal functional module obtains data from the on-chip data bus and the on-chip address bus, and feeds data back to these two buses. The two functional modules of HDLC, HDLC0 module and HDLC1 module, do not need to communicate through the on-chip address bus, but only communicate data on the on-chip data bus.

[0040] In this embodiment, the X86 architecture processor selected is the AM186EM processor, and the internal logic of the FPGA controls the two sets of buses to communicate with the externally connected AM186EM processor.

[0041] In addition, it can be understood that the on-chip peripheral logic block is also connected to the X86 architecture processor via chip select and read / write control connection lines. Figure 5 As shown, the FPGA architecture processor and the X86 architecture processor are also connected through chip select signal 0, chip select signal 1, chip select signal 4, write enable, read enable and address latch.

[0042] Furthermore, AM186 and FPGA communicate through register mapping. During normal operation of the system, AM186 processor sends instructions to FPGA through address bus, data bus and command bus. After receiving the instructions, FPGA needs to correctly parse them, identify whether they are command codes or data codes and perform corresponding actions. Figure 5 As shown, the implementation of each logic block is briefly described:

[0043] FIOC module: parses instructions through the state machine to indirectly control the fault-tolerant comparison FPGA and some external programmable ports (such as crystal oscillator clock switching function).

[0044] UART module: It is an asynchronous transceiver communication module. It interacts with the X86 architecture processor through polling and uses parity check to ensure the quality of data transmission. During data transmission, the state machine controls the assembly and parsing process of the frame structure. Both the transmitter and the receiver use FIFO technology to implement data buffering.

[0045] HDLC module: It is a high-level data link control interface module. It interacts with the X86 architecture processor through interrupts. It uses CRC check to ensure the correctness of data transmission. During the data transmission process, a state machine is used to control the generation and analysis of frames. Each frame of data is transmitted with NRZI encoding and decoding, which improves the security of information. Both sending and receiving use FIFO as the data buffer to better achieve rate matching.

[0046] DUAL TONE module: a dual-tone multi-frequency communication module used to control external frequency modulation circuits.

[0047] Figure 5In the figure, the DUAL TONE module is connected to the external device through the output signal; the UART module is connected to the external device through the input signal and the output signal, and is used for information interaction with the external device; the FIOC module is connected to the external device through the input signal 0, the input signal 1 and the output signal, and is used for information interaction with the external device; the HDLC0 and HDLC1 modules are connected to the external device through the input signal and the output signal, and are used for information interaction with the external device.

[0048] like Figure 3 As shown, the on-chip peripheral logic block is used to be mapped to the IO space of the X86 architecture processor. Figure 3 It is a memory map for addressing IO.

[0049] Figure 3 The whole is divided into three parts: left, middle and right. The data on the left is the addressing address, representing the upper and lower limits of the addressing of each area in the middle; each row in the middle represents a different module; the data on the right is the chip select signal of each module in the middle.

[0050] Figure 3 From bottom to top, each row in the middle represents a different module and its corresponding IO addressing area:

[0051] HDLC0 and HDLC1 modules: This module is a High-level Data Link Control (HDLC) interface module. 0 and 1 represent two different channels.

[0052] Among them, the IO addressing area corresponding to the HDLC0 module is 0000h-0020h; the IO addressing area corresponding to the HDLC1 module is 0020h-0040h.

[0053] SYSTEM REGISTERS module: This module is the system register configuration module. This module has no external interface and is mainly used to store some system configuration information. The IO addressing area corresponding to the SYSTEM REGISTERS module is 0040h-0050h.

[0054] CONSOLE, UART1, and UART2 are three universal asynchronous receiver / transmitter (UART) modules. The CONSOLE module is special, and it also belongs to the UART protocol, but this interface is only used for dual-machine redundant communication between DCS controllers, so it is not named UART0, but CONSOLE (control); UART1 and UART2 are two universal asynchronous receiver / transmitter communication modules. 1 and 2 represent two different channels.

[0055] The IO addressing areas corresponding to CONSOLE, UART1, and UART2 are 0050h-0060h, 0060h-0070h, and 0070h-0080h respectively.

[0056] DUAL TONE is a dual-tone multi-frequency communication module, which is mainly used to control some special external frequency modulation circuits. The corresponding IO addressing area is 0080h-0090h.

[0057] The UNUSED area is usually not used and is a spare area. The corresponding IO addressing area is 0090h-00B0h.

[0058] ANALOG I / O CONTROL BLOCK0 and ANALOG I / O CONTROL BLOCK1 modules are analog interface control modules that control external analog interfaces.

[0059] The IO addressing areas corresponding to the ANALOG I / O CONTROL BLOCK0 and ANALOG I / O CONTROL BLOCK1 modules are 0100h-0180h and 0180h-0200h respectively.

[0060] PIN CONFIG REG module: This module is the pin configuration register module. This module has no external interface and stores some interface configuration information. The IO addressing area corresponding to the PIN CONFIG REG module is 0200h-0240h.

[0061] DISCRETE I / O WATCHDOG CHANNEL&STATUS INDICATORS module: This module is mainly used for digital discrete port control, watchdog channel control and status indication related content.

[0062] The IO addressing area corresponding to the DISCRETE I / O WATCHDOG CHANNEL&STATUS INDICATORS module is 0240h-0280h.

[0063] PULSE COUNTER ARRAY module: It is a pulse counting array module. This module is used to record the number of times a specific pulse occurs. The corresponding IO addressing area is 0280h-0300h.

[0064] RESERVED IPCB and UNUSED modules are the same, both are reserved blank areas, no functions are included in these areas. The IO addressing area corresponding to the upper UNUSED module is 0300h-FF00h, and the IO addressing area corresponding to the RESERVED IPCB module is FF00h.

[0065] The pcs_n0~pcs_n6 on the right are the chip select signals of each module. When you need to operate the corresponding functional module, you need to use the chip select signal to select the module function. The following chip select is used as the basis:

[0066] When you need to operate the HDLC0, HDLC1, SYSTEM REGISTERS, CONSOLE, UART1, and UART2 modules, the chip select signal used is pcs_n0;

[0067] When the DUAL TONE module needs to be operated, the chip select signal used is pcs_n1;

[0068] When the ANALOG I / O CONTROL BLOCK0 module needs to be operated, the chip select signal used is pcs_n2;

[0069] When the ANALOG I / O CONTROL BLOCK1 module needs to be operated, the chip select signal used is pcs_n3;

[0070] When you need to operate the PIN CONFIG REG, DISCRETE I / O WATCHDOG CHANNEL&STATUSINDICATORS modules, the chip select signal used is pcs_n4;

[0071] When the PULSE COUNTER ARRAY module needs to be operated, the chip select signal used is pcs_n5;

[0072] When the reserved RESERVED IPCB and UNUSED modules need to be operated, the chip select signal used is pcs_n6.

[0073] Figure 3 In the figure, the 64Kbytes on the far right represent the total addressing depth of the IO interface; the 8 bits above represent the horizontal width of each address during IO addressing. The START ADDRESS in the upper left corner represents the start address, and the Peripheral chip select signal in the upper right corner represents the peripheral chip select signal.

[0074] like Figure 1As shown, in order to realize the function of acquiring and storing instructions, the X86 architecture processor of this embodiment is also connected to FLASH and SRAM memories outside, and the FLASH and SRAM memories are used to be mapped to the memory address space of the X86 architecture processor. FLASH is Figure 1 The Flash PROM and SRAM memory in Figure 1 Static RAM in.

[0075] The processor based on X86 architecture in this embodiment uses AM186EM processor, and the FLASH, SRAM memory and X86 architecture processor are connected through data bus, address bus, chip selection and read-write control connection lines. AM186EM itself has rich interface units such as two-way DMA, three timers, six-way interrupts, etc. for developers to design and debug.

[0076] Furthermore, Figure 1 The names and functions of the pins of the AM186EM processor are as follows:

[0077] X1 and X2 are the connection ports of 40MHz crystal oscillator, which are used to input the crystal oscillator signal required for the normal operation of the processor;

[0078] 40-MHz Crystal is a 40MHz crystal oscillator;

[0079] The WHB and WLB signals are high byte (High) and low byte (Low) write enable signals. Flash PROM and Static RAM are divided into high byte and low byte. The AM186EM processor uses these two signals to control the write enable of these external memories.

[0080] A19-A0 is the address output bus. AM186EM processor outputs the corresponding operation address to the external Flash and Static RAM.

[0081] AD15-AD0 is a bidirectional data bus. The AM186EM processor outputs data to the external memory through this bus, and reads data from the external memory through this bus.

[0082] RD is the read enable signal. AM186EM processor controls the read enable of external memory through this port. All external memories share one read enable.

[0083] UCS and LCS are chip select enable signals of external memory. UCS chip select is used to select two FLASH chips, and LCS is used to select two Static RAM chips.

[0084] Serial Port is a serial port. Its connected TXD and RXD signals are two serial communication signal lines. TXD is used to send data and RXD is used to receive data.

[0085] RS-232 Level Converter refers to a serial port converter, which is used to match the standard level specified by the serial port protocol.

[0086] Figure 1 In the embodiment, the number of Flash PROM and Static RAM memories are both two, and both are provided with WE pin, Address pin, Data pin, OE pin and CS pin.

[0087] For Flash PROM:

[0088] The WE pin indicates that the WE pin of one Flash PROM is connected to the WHB pin of the AM186EM processor; the WE pin of the other Flash PROM is connected to the WLB pin of the AM186EM processor;

[0089] The Address pins are all connected to the A19-A0 pins of the AM186EM processor;

[0090] The Data pin is connected to the AD15-AD0 pin of the AM186EM processor;

[0091] The OE pin is connected to the RD pin of the AM186EM processor;

[0092] The CS pin is connected to the UCS pin of the AM186EM processor.

[0093] For Static RAM:

[0094] The WE pin indicates that the WE pin of one Static RAM is connected to the WHB pin of the AM186EM processor; the WE pin of another Static RAM is connected to the WLB pin of the AM186EM processor;

[0095] The Address pins are all connected to the A19-A0 pins of the AM186EM processor;

[0096] The Data pin is connected to the AD15-AD0 pin of the AM186EM processor;

[0097] The OE pin is connected to the RD pin of the AM186EM processor;

[0098] The CS pin is connected to the LCS pin of the AM186EM processor.

[0099] like Figure 2 As shown, Figure 2 The FLASH and SRAM in the middle part represent the FLASH and SRAM memories externally connected to the X86 architecture processor, respectively, and UNUSED means unused. Figure 2 The 00000, 3FFFF, E0000, and FFFFF in the stack column on the left side represent the boundaries of the addressing addresses of each area.

[0100] like Figure 2 As shown in the figure, when addressing SRAM, the addressing address can only be in the range of 00000~3FFFF; when addressing FLASH, the addressing address can only be in the range of E0000~FFFFF. The addresses between 3FFFF and E0000 are not used.

[0101] Figure 2 The 256K and 128K on the middle right are the addressing depths of the SRAM area and the FLASH area, representing the vertical depth of the storage capacity of these two areas. Figure 2 The 8 bits in the upper middle represent that the data stored at each address is 8 bits wide, which represents the horizontal width of the storage capacity of the SRAM and FLASH areas. The horizontal width multiplied by the vertical depth is the storage capacity of the area.

[0102] Figure 2 The 1M on the right is the total addressing depth of the AM186EM external memory (even if a part of it is not used), which means that if you want to operate the external memory, the operating space should not be higher than 1M (FFFFF is 2 20 =1M).

[0103] Figure 2 and Figure 3 The form is the same but the content is different. Figure 2 Represents the addressing map that needs to be referenced when operating the external memory; Figure 3 Represents the addressing diagram that needs to be referred to when operating the external IO interface.

[0104] like Figure 4As shown in FIG. 1 , it is a block diagram of the structure of the AM186EM processor. The AM186EM processor includes a clock and power management module, an interrupt control unit, a time control unit, a direct memory read unit, a programmable interface unit, an asynchronous serial interface, a synchronous serial interface, a chip select unit, an execution unit, and a bus interface unit, wherein the bus interface unit also includes a refresh control unit, and the chip select unit also includes a PSRAM control unit. The above clock and power management module, interrupt control unit, time control unit, direct memory read unit, programmable interface unit, asynchronous serial interface, synchronous serial interface, chip select unit, and bus interface unit are all configured through control registers. The internal control bus of AM186EM (the white arrow bus in the figure) connects the control registers of these modules to control these modules.

[0105] The time control unit includes a maximum count B register, a maximum count A register and a 16-bit count register; the direct memory read unit includes a 20-bit source pointer, a 20-bit destination pointer and a 16-bit count register.

[0106] Starting from the upper left corner and going clockwise, each lead pin is explained. A horizontal line above the pin name indicates that the signal is valid at a low level, and no horizontal line indicates that the signal is valid at a high level. Pins distinguished by a backslash / are multi-function pins, that is, a pin can be configured for different uses. This embodiment is designed as the default configuration, and only the pin function before the backslash / is used.

[0107] X1, X2: Crystal oscillator input pins. External crystal oscillator provides basic input clock for AM186EM CPU operation.

[0108] CLKOUTA, CLKOUTB: Clock output pins. Clock output by the clock module. AM186EM chip outputs clock output pins for external devices.

[0109] INT4~INT0: Interrupt input signal. The pins used when external devices are connected and sent to the AM186EM chip external interrupt.

[0110] INTA0, INTA1: Pins for interrupt priority connection when AM186EM is cascaded.

[0111] IRQ: The highest priority external interrupt pin when AM186EM is cascaded as the main controller.

[0112] SELECT: When AM186EM is cascaded, the interrupt selection pin needs to be fed back to the upper controller.

[0113] NMI: non-maskable external interrupt, the highest priority interrupt pin.

[0114] TMRIN0, TMRIN1: timer input ports.

[0115] TMROUT0, TMROUT1: timer output ports.

[0116] DRQ0, DRQ1: DMA response signals. Signals used by external devices to communicate with the internal DMA controller.

[0117] PIO31~PIO0: Programmable external IO ports. They can be configured into ports with different functions according to different usage scenarios.

[0118] TXD, RXD: external input and output ports of the asynchronous serial interface module. TXD is the sending port, and RXD is the receiving port.

[0119] SDATA: External data line of synchronous serial interface module.

[0120] SDEN0, SDEN1: Synchronous serial interface module transmission enable signal.

[0121] SCLK: Synchronous clock signal of the synchronous serial interface module.

[0122] PCS6-0: external interface module chip select signal, corresponding to Figure 3 pcs_n6~pcs_n0 in.

[0123] A1, A2: AM186EM default address latch. Latch the previous value when the external interface function is not used.

[0124] UCS, LCS: chip select signals of external memory. Figure 1 Controls the chip select of Flash PROM and Static RAM.

[0125] MCS3~MCS0: Chip select signal of spare storage unit.

[0126] ONCE0, ONCE1: The pins used by AM186EM to indicate its status to the outside during reset.

[0127] RFSH: When AM186EM is connected to a memory that needs to be automatically refreshed, it provides a timing refresh signal pin to the external memory.

[0128] RD: Bus read enable signal.

[0129] WHB, WLB: Write enable signals for the high and low bytes of the bus. WHB controls the high byte write, and WLB controls the low byte write. This write enable signal is used for memory write control.

[0130] WR: Bus write enable signal. This write enable signal is used for IO function module control.

[0131] BHE: High and low byte enable signal. Used to select high byte or low byte when decoding CPU instructions.

[0132] ADEN: AM186EM pin signal indicating the address cycle during reset.

[0133] ALE: Address latch enable signal. Used to latch address data on the AD bus.

[0134] AD15-AD0: Address, data bus. Transmit address and data information.

[0135] A19-A0: Address bus. Latched on the AD bus through the ALE signal.

[0136] UZI: Upper zero indication. This signal can be used to expand the address bus.

[0137] S6, S2-S0: Mode selection signal. Indicates whether the current bus cycle is a storage cycle or a control cycle.

[0138] HOLD, HLDA: bus control signal, bus control response signal. Communicate with peripherals through these two signal lines to obtain or give up bus control.

[0139] DEN, DT / R: Data enable and indication. When the current bus cycle is a storage cycle, this group of signals indicates the current status.

[0140] ARDY, SRDY: asynchronous ready and synchronous ready indication signals. Related to the operation of asynchronous serial port module and synchronous serial port module.

[0141] CLKDIV2: This is the pin indicating that the internal clock of AM186EM is divided by two. It is usually used during debugging.

[0142] RES: Reset signal. The signal required to reset the Am186EM CPU.

[0143] VCC, GND: power supply and ground.

[0144] like Figure 4 As shown, the connection relationship between the above-mentioned module units and pins is as follows:

[0145] Clock and power management module connections: X1, X2, CLKOUTA, CLKOUTB, VCC, GND;

[0146] Interrupt control unit connection: INT4~INT0, INTA0, INTA1, IQR, SELECT, NMI;

[0147] Time control unit connections: TMRIN0, TMRIN1, TMROUT0, TMROUT1;

[0148] Direct memory read unit connections: DRQ0, DRQ1;

[0149] Programmable interface unit connection: PIO31-PIO0;

[0150] Asynchronous serial interface connection: TXD, RXD;

[0151] Synchronous serial interface connection: SDATA, SDEN0, SDEN1, SCLK;

[0152] Chip select unit connection: PCS6-0, A1, A2, UCS, LCS, MCS3~MCS0, ONCE0, ONCE1, RFSH;

[0153] Bus interface unit connections: RD, WHB, WLB, WR, BHE, ADEN, ALE, AD15-AD0, A19-A0, UZI, S6, S2-S0, HOLD, HLDA, DEN, DT / R, ​​ARDY, SRDY, CLKDIV2.

[0154] Overall, if Figure 5 As shown, the FLASH, SRAM memory and the X86 architecture processor are connected via a data bus, an address bus, and chip select and read / write control connection lines.

[0155] This embodiment provides a dual-core heterogeneous distributed system controller, which uses an X86 processor and an FPGA processor to interact to implement the functions of the aforementioned ASIC chip. The FPGA processor can be customized for different needs, and the signal processing efficiency is higher than modifying the software program, and the communication interface is expandable, and the hardware cost is also low. The controller can be used in applications with high system performance requirements, such as in nuclear power plant systems, and has broad application prospects.

[0156] Embodiment 2:

[0157] This embodiment designs a redundant control system for dual-machine communication based on an FPGA processor, and monitors the status of the CPU in the master and slave controllers in real time through the ctrl bus, which is mainly used to implement a response mechanism when one of the controllers fails or both controllers fail. The redundant logic design of the FPGA processor solves the problem of the original FCP270 dual-machine redundant communication failing at the same time, which causes the nuclear power control system to be paralyzed.

[0158] Redundant control systems, such as Figure 6 As shown, it includes two distributed system controllers based on dual-core heterogeneity described in Example 1, wherein one distributed system controller serves as a host, and the other distributed system controller serves as a slave, the CPU of the host is connected to the FPGA of the host and the FPGA of the slave respectively, the CPU of the slave is connected to the FPGA of the slave and the FPGA of the host respectively, and the host and the slave communicate via RS485; the FPGA of the host and the FPGA of the slave are connected to peripheral devices respectively;

[0159] The FPGA of the slave is used to monitor the CPU status of the host and the CPU status of the slave respectively, and when the CPU of the host and the CPU of the slave fail at the same time, an alarm message with the highest priority is issued;

[0160] The FPGA of the host is used to release the control instructions in the internal cache before the CPU failure when the CPU of the host and the CPU of the slave fail at the same time, and run the original instructions stored in itself to stabilize the current control state;

[0161] The FPGA of the slave is also used to notify the CPU of the slave to take back the initiative of peripheral device control, restart the failed host CPU, switch the master and slave through RS485, and send out an alarm signal when it detects that only the CPU of the host fails.

[0162] The two controllers communicate with each other via the standard circuit RS485 to determine the master and slave. The CPU of the master is connected to the FPGA of the slave via the ctrl1 bus, and the CPU of the slave is connected to the FPGA of the master via the ctrl2 bus.

[0163] During normal operation, the distributed system controller issues instructions to the FPGA through the CPU, and then the FPGA caches the instructions before controlling the peripheral circuits. During the control process, the FPGA monitors the status of the current device CPU in real time, and at the same time monitors the status of the CPU in another distributed system controller through the interconnected ctrl bus. If one of the CPU controllers fails, the FPGA parts of both devices will receive a fault signal.

[0164] Take the host CPU failure as an example. If the host CPU fails during normal operation, the slave FPGA will immediately notify the slave CPU, take back the initiative to control the peripheral devices, and restart the failed distributed system controller host through the ctrl1 control signal bus. At this time, the RS485 handshake bus signal changes. According to the protocol, the master and slave of the two devices are switched, and the original slave controls the peripheral devices and sends an alarm signal to the human-computer interaction system to prompt the staff to perform fault identification and repair.

[0165] When both machines fail at the same time, the FPGAs of both devices will receive a message that both CPUs are faulty. At this time, the FPGA will no longer restart the faulty distributed system controller host, because both controllers have failed and it is meaningless to switch between the master and slave. At this time, the FPGA of the distributed system controller host will complete the release of the control instructions in the internal cache before the CPU failure, and then run the original instructions stored in the FPGA to stabilize the current control state; when detecting the simultaneous failure, the FPGA of the distributed system controller slave will immediately issue the highest priority alarm information to prompt the staff to carry out subsequent processing.

[0166] Compared with the original DCS controller FCP270, this embodiment separates the control logic and the redundant logic, so that it can cope with the situation when two redundant controllers fail at the same time. It has high reliability and is suitable for the working environment of nuclear power control that requires a high safety factor.

[0167] Embodiment three:

[0168] This embodiment provides a redundancy control method.

[0169] The redundant control method includes the FPGA of the slave machine monitoring the CPU status of the master machine and the CPU status of the slave machine respectively:

[0170] When the CPU of the host and the CPU of the slave fail at the same time, the FPGA of the slave sends out the highest priority alarm information; at this time, the FPGA of the host completes the release of the control instructions in the internal cache before the CPU failure, and runs the original instructions stored in itself to stabilize the current control state;

[0171] When the FPGA of the slave detects that only the CPU of the host fails, it notifies the CPU of the slave to take back the initiative of controlling the peripheral devices, restarts the failed host CPU, switches the master and slave through RS485, and sends out an alarm signal.

[0172] In the description of this specification, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0173] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A redundant control system, characterized in that: It includes two dual-core heterogeneous distributed system controllers, one of which is used as a host and the other as a slave. The CPU of the host is connected to the FPGA of the host and the FPGA of the slave respectively, the CPU of the slave is connected to the FPGA of the slave and the FPGA of the host respectively, and the host and the slave communicate via RS485. The FPGA of the slave is used to monitor the CPU status of the host and the CPU status of the slave respectively, and when the CPU of the host and the CPU of the slave fail at the same time, an alarm message with the highest priority is issued; The FPGA of the host is used to release the control instructions in the internal cache before the CPU failure when the CPU of the host and the CPU of the slave fail at the same time, and run the original instructions stored in itself to stabilize the current control state; The dual-core heterogeneous distributed system controller includes an X86 architecture processor and an FPGA architecture processor, the FPGA architecture processor includes a plurality of on-chip external logic blocks, the X86 architecture processor is connected to the plurality of on-chip external logic blocks of the FPGA architecture processor respectively, and the on-chip external logic blocks are used to be mapped to the IO space of the X86 architecture processor; The X86 architecture processor is externally connected with FLASH and SRAM memories, and the FLASH and SRAM memories are used to be mapped to the memory address space of the X86 architecture processor; in, The IO addressing area corresponding to the HDLC0 module is 0000h-0020h; the IO addressing area corresponding to the HDLC1 module is 0020h-0040h; The IO addressing area corresponding to the SYSTEM REGISTERS module is 0040h-0050h; The IO addressing areas corresponding to CONSOLE, UART1, and UART2 are 0050h-0060h, 0060h-0070h, and 0070h-0080h respectively; The IO addressing area corresponding to DUAL TONE is 0080h-0090h; The IO addressing areas corresponding to the ANALOG I / O CONTROL BLOCK0 and ANALOG I / O CONTROL BLOCK1 modules are 0100h-0180h and 0180h-0200h respectively; the ANALOG I / O CONTROL BLOCK0 and ANALOG I / O CONTROLBLOCK1 modules are analog interface control modules that control external analog interfaces; The IO addressing area corresponding to the PIN CONFIG REG module is 0200h-0240h; the PIN CONFIG REG module is a pin configuration register module that stores interface configuration information; The IO addressing area corresponding to the DISCRETE I / O WATCHDOG CHANNEL&STATUS INDICATORS module is 0240h-0280h; The CHANNEL&STATUS INDICATORS module performs digital discrete port control, door channel control and status indication; The IO addressing area corresponding to the PULSE COUNTER ARRAY module is 0280h-0300h; the PULSE COUNTER ARRAY module is a pulse counting array module that records the number of times a specific pulse occurs; The IO addressing area corresponding to the UNUSED module is 0300h-FF00h and 0090h-00B0h, and the IO addressing area corresponding to the RESERVED IPCB module is FF00h.

2. A redundant control system according to claim 1, characterized in that: The plurality of on-chip peripheral logic blocks are respectively used for connecting external devices.

3. A redundant control system according to claim 1, characterized in that: The on-chip peripheral logic block includes two HDLC modules, a UART module, a FIOC module and a DUAL TONE module. The two HDLC modules are connected to the X86 architecture processor via a data bus, and the UART module, the FIOC module, the DUAL TONE module are connected to the X86 architecture processor via a data bus and an address bus respectively.

4. A redundant control system according to claim 3, characterized in that: The on-chip peripheral logic block is connected to the X86 architecture processor via chip selection and read-write control connection lines.

5. A redundant control system according to claim 3, characterized in that: The HDLC module is a high-level data link control interface module, which is used to interact with the X86 architecture processor through interruption; the UART module is an asynchronous transceiver communication module, which interacts with the X86 architecture processor through polling; the DUAL TONE module is a dual-tone multi-frequency communication module, which is used to control an external frequency modulation circuit.

6. A redundant control system according to claim 1, characterized in that: The FLASH, SRAM memory and X86 architecture processor are connected via a data bus, an address bus, and chip selection and read-write control connection lines.

7. A redundant control system according to claim 1, characterized in that: The FPGA of the slave is also used to notify the CPU of the slave to take back the initiative of peripheral device control, restart the failed host CPU, switch the master and slave through RS485, and send out an alarm signal when it detects that only the CPU of the host fails.

8. A redundant control method, characterized in that: A redundant control system as claimed in any one of claims 1 to 7 is used, wherein the FPGA of the slave monitors the CPU status of the host and the CPU status of the slave respectively: When the CPU of the host and the CPU of the slave fail at the same time, the FPGA of the slave sends out the highest priority alarm information; at this time, the FPGA of the host completes the release of the control instructions in the internal cache before the CPU failure, and runs the original instructions stored in itself to stabilize the current control state; When the FPGA of the slave detects that only the CPU of the host fails, it notifies the CPU of the slave to take back the initiative of controlling the peripheral devices, restarts the failed host CPU, switches the master and slave through RS485, and sends out an alarm signal.

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