A multi-neural network system based on memristor array and its construction method

Abstract

The present invention builds a memristor array through weight freezing, which is particularly suitable for RRAM shared arrays. We enhance the correlation between multiple independent neural network models and expand the convolution module that needs to be designed separately in the traditional solution to a shared design. This means that an RRAM weight array can participate in the calculation of multiple tasks, thereby improving the resource utilization of the neural network accelerator architecture, thereby realizing the construction of in-memory computing shared modules in the in-memory computing architecture, which can not only optimize the hardware resource configuration, but also reduce the design cost, thereby providing a more efficient and economical solution for deploying multiple neural network models for multi-tasking.

Description

Technical Field

[0001] The present invention relates to the field of in-memory computing of memristor arrays, and in particular to a multi-neural network system based on a memristor array and a construction method thereof, and is particularly suitable for non-volatile memories such as RRAM arrays. Background Art

[0002] With the rapid development of artificial intelligence technology, we have entered a new data-driven era, in which the complexity and computing requirements of neural networks continue to rise. However, the traditional von Neumann computing architecture has encountered a performance bottleneck due to the frequent data exchange between the processor and the memory, commonly known as the "memory wall". This limitation is particularly problematic when processing large-scale data sets, and the bandwidth and energy consumption of data transmission have become significant obstacles, limiting the development potential of high-performance processors.

[0003] To meet these challenges, integrated storage and computing chip design has become a key technical direction to promote the advancement of neural network computing capabilities. In this context, resistive random access memory (RRAM) technology, with its non-volatility and ability to process data directly in storage cells, shows great potential for building efficient neural network architectures. Unlike traditional storage devices, RRAM undergoes a change in resistance state under the action of a specific voltage excitation signal. With the help of this electrical characteristic, the high and low voltage levels are represented by the digital "1" and "0", respectively, and the high and low resistance states of the device are represented by "0" and "1", respectively. Combined with Ohm's law, the current flowing through the device is collected and quantified to obtain the digital multiplication calculation result. When RRAM is expanded into a crossbar array, the integrated multiply-accumulate (MAC) computing capability can support complex matrix operations, which is crucial for weight calculation and data transfer in neural networks. The RRAM-based storage and computing integrated architecture is expected to break through the limitations of traditional computing models through the innovative integration of circuit and system design, provide strong support for hardware accelerator design in terms of performance improvement and energy efficiency optimization, and have a far-reaching impact on the development of AI technology.

[0004] Although RRAM technology has shown great potential as an emerging storage solution, its large-scale integrated manufacturing still faces many technical challenges. Therefore, developing specific small neural networks or formulating corresponding network deployment optimization strategies has important practical value for building and exploring physical circuits. In the current conventional deployment strategy, each convolutional layer is generally equipped with an independent in-memory computing core. Although this approach has advantages in modularity and independence, it has limitations in resource utilization efficiency and cost-effectiveness. Summary of the invention

[0005] In view of the problems existing in the prior art, the present invention provides a multi-neural network system based on a memristor array, characterized in that: the RRAM array includes a controller, a plurality of computing modules and a post-processing module;

[0006] Building a neural network model A and a neural network model B based on the controller, the multiple computing modules and the post-processing module;

[0007] The convolution layer a of the neural network model A and the corresponding convolution layer b in the neural network model B are shared modules, and the shared modules use the same computing module;

[0008] The controller loads the trained parameters related to the convolution layer a in the neural network model A into the convolution layer b, so that the convolution layer a and the convolution layer b maintain consistent parameters.

[0009] Preferably, the convolution layer a and the convolution layer b are the first convolution layers of the neural network model A and the neural network model B, respectively.

[0010] Preferably, in the convolution layer a and the convolution layer b, functions are used to control the number of input channels, the number of output channels, the convolution kernel size and the convolution step size data to be consistent and unchanged.

[0011] Preferably, an intra-core detection signal is set in the computing module of the shared module.

[0012] Preferably, the relevant parameters of the neural network model A and the neural network model B are updated by the following formula:

[0013] w t+1 =w t -a▽J(w t );

[0014] where w t is the parameter value of the tth step, a is the learning rate, ▽J(w t ) is the gradient of the loss function with respect to the parameters. When weight freezing is applied, the gradient of some parameters can be set to zero.

[0015] Preferably, the shared module can be expanded into multiple modules.

[0016] The present invention also provides a method for constructing the above system, the method comprising the following steps:

[0017] Step S1: Building different neural network models A and B for different image processing tasks;

[0018] Step S2: Based on the first-stage training model and taking the parameters of the neural network model A as a benchmark, the attributes of the convolutional layer b parameters of the neural network model B to be frozen are set so that these parameters will not calculate the gradient during back propagation;

[0019] Step S3: Loading the trained parameters related to the convolution layer a in the neural network model A into the convolution layer b, so that the convolution layer a and the convolution layer b maintain the same parameters;

[0020] Step S4: After the neural network model A and the neural network model B are trained, the frozen parameters of the two models are compared to see whether they have not been updated during the training process, so as to verify the freezing effect.

[0021] The present invention also provides a control method for the above system, the method comprising the following steps:

[0022] S1: setting an intra-core detection signal in a computing module in the shared module;

[0023] S2: Designing detection signal A and detection signal B in the last fully connected layer modules of the neural network model A and the neural network model B to monitor the completion of different tasks;

[0024] S3: The neural network model A can receive a new task when and only when the detection signal in the core is idle and the detection signal A indicates that the neural network model A has completed the previous task; the neural network model B can receive a new task when and only when the detection signal in the core is idle and the detection signal B indicates that the neural network model B has completed the previous task.

[0025] Compared with the prior art solutions, the present invention has at least the following beneficial effects:

[0026] 1) By freezing the weights and building a shared memristor array, we have enhanced the correlation between multiple independent neural network models and expanded the convolution modules that need to be designed separately in the traditional solution to a shared design. This means that a memristor array can participate in the calculation of multiple tasks, thereby improving the resource utilization of the neural network accelerator architecture, thereby realizing the construction of in-memory computing shared modules in the in-memory computing architecture, which can not only optimize the hardware resource configuration, but also reduce the design cost, thus providing a more efficient and economical solution for deploying multiple neural network models for multi-tasking;

[0027] 2) When using the RRAM array for multiplication and accumulation calculations, peripheral circuits are required for processing, such as digital / analog conversion, shift weighting, and intermediate data cache circuits. Although there are many research methods dedicated to circuit area optimization, it is still difficult to avoid. The shared memory computing core module designed by the present invention includes an RRAM array and peripheral circuits, which can directly reduce the repeated configuration of the weight array and peripheral circuits, effectively reduce the system area and design cost, and is therefore suitable for deploying multiple neural network models on limited hardware resources;

[0028] 3) The present invention provides a task scheduling control design based on weight array sharing, which can effectively manage multi-task processing by setting detection signals and congestion logic design in the shared module. This design combined with the weight sharing design enables developers to flexibly adjust the neural network structure and task scheduling control according to actual needs, which is conducive to more efficient neural network model deployment and maximized multi-task parallel processing, showing a certain degree of application scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a mapping diagram of the convolution kernel of the present invention on the RRAM array;

[0030] Figure 2 This is the architecture diagram of the RRAM-based storage and computing integrated neural network accelerator of the present invention;

[0031] Figure 3 It is the existing technology that is based on the traditional method of multi-network deployment;

[0032] Figure 4 It is a multi-network deployment based on the weight freezing method of the present invention;

[0033] Figure 5 It is an in-memory computing framework that can be adjusted according to actual application requirements of the present invention.

[0034] The present invention is further described in detail below. However, the following examples are only simplified examples of the present invention and do not represent or limit the scope of protection of the present invention. The scope of protection of the present invention shall be subject to the claims. DETAILED DESCRIPTION

[0035] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific implementation methods.

[0036] In the design of in-memory computing neural network accelerator based on RRAM array, in order to maximize the utilization of storage units, the size of each RRAM weight array is adjusted according to the structure of the convolution kernel. Figure 1As shown, it is a mapping diagram of the convolution kernel of the present invention on the RRAM array; multiple three-dimensional convolution kernels are fully expanded into one-dimensional vectors, and these vectors are stored in the conductance value of the RRAM device. At the same time, the input feature map is also expanded in the same way as the input voltage. This mapping strategy allows different columns in the RRAM array to store different convolution kernels, so that the results of multiple convolution kernels at the same sliding window position can be calculated in parallel in a single clock cycle, and the input feature maps of different sliding window positions can be processed in multiple clock cycles, and finally the convolution calculation of one convolution layer is realized. Assuming that a convolution layer contains m×n×s×s weight data, each data is quantized to N bits, the corresponding weight array based on binary RRAM requires (m×N) columns and (n×s×s) rows of devices.

[0037] According to the built RRAM weight array, the peripheral circuit modules required for calculation, such as digital / analog conversion circuit, shift weight circuit and intermediate data cache circuit, are configured to form an in-memory computing core circuit. Figure 2 The figure shows the architecture diagram of the RRAM-based storage and computing integrated neural network accelerator of the present invention; the complete neural network accelerator architecture usually includes multiple computing blocks (CIM Tiles), control modules (Controller) and post-processing modules (Post-process) and other auxiliary modules to support the complete functions of the accelerator. For convolutional neural networks, the "number of layers" in convolutional neural networks is different in different applications. Usually, convolutional layers and fully connected layers containing only RRAM arrays are used as neural network layers, so that the number of layers of the convolutional neural network can be more reasonably matched with the number of computing blocks.

[0038] According to the above accelerator architecture design, when multiple neural network models are to be deployed, more dedicated in-memory computing cores need to be designed and optimized. This modular design is customized for the specific needs of different layers, but the task objects, convolutional layer structures, and weight data training results of different network models are different. Configuring in-memory computing cores for each layer separately also means an increase in cost, and when performing similar or identical computing tasks, hardware resources will be repeatedly configured, which further reduces resource utilization.

[0039] In view of the defect in the prior art that the in-memory computing core requires a dedicated design and cannot be reused, the present invention provides a training method and system for different CNN model structures using a weight freezing design, which shares the in-memory computing core circuit while ensuring the calculation accuracy and precision, thereby reducing the consumption of peripheral circuit resources, and providing a feasible strategy for deploying hardware acceleration of multiple neural networks.

[0040] Taking the first layer weight data of the fixed model as an example, the implementation of the technical method of the present invention specifically includes the following three steps:

[0041] Step 1: Building convolutional neural network models for different image processing tasks

[0042] In the data preparation stage, different convolutional neural network architectures need to be built for different image processing tasks. The difference of the present invention is that the first convolution layer structure of the CNN model to be deployed is completely consistent. When performing convolution operations, the depth of the convolution kernel matches the number of channels of the input feature map. Taking the handwritten digit recognition task (MNIST) and the handwritten letter recognition task (EMNIST) as examples, the input feature maps of both are single-channel 28×28 size.

[0043] (1) Under the PyTorch framework, build at least two CNN models A and B for the MNIST and EMNIST datasets respectively. It can also be multiple neural network models. The embodiment is described with two models. In the design of the first convolution layer of the two models, a function is used to control the number of input channels, the number of output channels, the convolution kernel size, and the convolution step size data to be consistent and unchanged. The subsequent network layers do not need to set the same structure and can be adjusted appropriately;

[0044] (2) Use the same quantization method and quantization bit number for the trained models A and B, and modify the model structure in step (1) according to the accuracy test results after quantization to ensure that the final training test and quantization test results meet the expected standards.

[0045] Step 2: Use weight freezing to fix the first layer weight data of the model

[0046] Weight freezing is a technique in deep learning model training, which is usually used to fix some or all weight parameters in the later stages of model training to prevent them from being updated in the subsequent training. This strategy can help the model converge stably and improve generalization ability in some cases, which can be explained by the parameter update process in the optimization problem.

[0047] Assume that the minimization loss function is J(w), where w is the set of all weight parameters of the model. The optimization problem can usually be expressed as: .in is the optimal parameter set that minimizes the loss function J(w). In the conventional training process, we calculate the gradient of the loss function with respect to the parameters and use the gradient descent method to update the parameters w. This update process can be expressed as follows:

[0048] w t+1 =w t -a▽J(w t );

[0049] where w tis the parameter value of the tth step, a is the learning rate, ▽J(w t ) is the gradient of the loss function with respect to the parameters. When weight freezing is applied, the gradients of some parameters can be set to zero to prevent them from being modified during the update process. Suppose you want to freeze the parameter set W f , the update process can be modified as follows:

[0050]

[0051] In this way, during the training process, the parameter set W f The parameters of will remain unchanged and will not be updated, while other parameters will continue to be updated in the usual way. In this stage, this method will be used to fix the weight data of the first convolution layer of models A and B to achieve the association and unification of network models at the software level. In actual applications, you can choose the parameters that need to be frozen according to the structure of the model and the training results.

[0052] (1) Based on the first stage training model, the parameters of model A are used as the benchmark. The attributes of the first convolutional layer parameters of model B that need to be frozen are set so that these parameters will not calculate the gradient during back propagation. When redefining the optimizer, only the parameters that need to be updated are passed to the optimizer to avoid updating the frozen parameters;

[0053] (2) Use the function to load the first layer weight data of model A into the first convolution layer of model B, so that the parameters of the first convolution layer of model B obtained by retraining are consistent with the parameters of the first convolution layer of model A. The same freezing and transfer process is performed in the quantization training, so that the parameters of the quantized model can remain the same as set.

[0054] (3) After training, print out the weight values ​​and compare whether the frozen parameters of the two models have not been updated during the training process to verify the freezing effect. During the training process of (1) and (2) above, adjustments can be made according to actual needs. For example, more layers can be frozen hierarchically according to the depth and complexity of the model, and more shared modules can be set according to actual conditions and needs.

[0055] Step 3: Task scheduling control design based on weight array sharing

[0056] After completing the weight array sharing preparation stage, the quantized convolution kernel weight data will be written row by row into the RRAM array for storage through the control of the peripheral digital logic circuit. According to the established network structure, multiple in-memory computing core circuits are interconnected to obtain an in-memory computing architecture that can realize multi-tasking. In order to avoid congestion of data flow in the shared array, the present invention introduces an efficient task scheduling function into the multi-tasking system architecture to ensure that the calculation of network models A and B can proceed smoothly, so that the sharing mechanism and stability of the entire system are optimized.

[0057] (1) In the first-layer shared memory computing core module, an intra-core detection signal is set. The intra-core detection signal is divided into idle, high congestion risk, model A is performing convolution calculation, and model B is performing convolution calculation;

[0058] (2) When the in-core detection signal is received, indicating that the risk of internal data congestion is high, it indicates that the shared module has received computing requests from multiple tasks at the same time. Set the task priority according to the specific application scenario requirements, and store the tasks waiting to be executed by designing a buffer queue to ensure that more important or urgent computing tasks can be executed first. Once the tasks requested at the same time are processed and the in-core detection signal is idle, the shared module can continue normal computing work;

[0059] (3) Design detection signals A and B in the last fully connected layer modules of CNN models A and B to monitor the completion of different tasks. When a test feature map is calculated, the corresponding detection signal is kept high for a period of time and then pulled low so that the task scheduling control module can receive and process the signal changes in time;

[0060] (4) Model A can receive new feature map data from the MNIST dataset only when the core detection signal is idle and detection signal A indicates that model A has completed the previous task. Model B can receive new feature map data from the EMNIST dataset only when the core detection signal is idle and detection signal B indicates that model B has completed the previous task. This allows models A and B to be calculated in parallel without data congestion.

[0061] Taking the shared first convolutional layer as an example, Figure 3 The existing technology is based on the traditional method of multi-network deployment. Figure 4 This is a multi-network deployment based on the weight freezing method of the present invention. Under this multi-task processing framework, the first-layer in-memory computing core structure of models A and B is shared. Compared with traditional technical solutions, the RRAM device resources and peripheral hardware resources such as digital / analog conversion circuits required for the entire convolutional layer are reduced, which effectively improves resource utilization and reduces design costs while improving system applications. And by introducing task scheduling control and data flow detection, the system can process multiple tasks in parallel, monitor task status in real time, and give priority to important tasks, thereby improving system flexibility and computing performance. In practical applications, the neural network architecture and task management can be adjusted and modified according to task requirements, such as Figure 5 shown.

[0062] The preferred embodiments of the present invention are described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0063] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0064] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A multi-neural network system based on a memristor array, characterized in that: The memristor array includes a controller, a plurality of computing modules and a post-processing module; Building a neural network model A and a neural network model B based on the controller, the multiple computing modules and the post-processing module; The convolution layer a of the neural network model A and the corresponding convolution layer b in the neural network model B are shared modules, and the shared modules use the same computing module; The controller loads the trained parameters related to the convolution layer a in the neural network model A into the convolution layer b, so that the convolution layer a and the convolution layer b maintain consistent parameters.

2. The system according to claim 1, characterized in that: The convolution layer a and the convolution layer b are the first convolution layers of the neural network model A and the neural network model B respectively.

3. The system according to claim 1, characterized in that: In the convolution layer a and the convolution layer b, functions are used to control the number of input channels, the number of output channels, the convolution kernel size and the convolution step size data to be consistent and unchanged.

4. The system according to claim 1, characterized in that: An intra-core detection signal is set in the computing module of the shared module.

5. The system according to claim 1, characterized in that: The relevant parameters of the neural network model A and the neural network model B are updated by the following formula: w t+1 = w t - a ▽ J ( w t )； in w t It is t The parameter value of the step, a is the learning rate, ▽ J ( w t ) is the gradient of the loss function with respect to the parameters. When weight freezing is applied, the gradients of some parameters can be set to zero. The parameters can be selected based on the structure of the model and the training results.

6. The system according to claim 1, characterized in that: The shared module can be expanded into multiple modules.

7. A method for constructing a system according to any one of claims 1 to 6, characterized in that: The method comprises the following steps: Step S1: Building different neural network models A and B for different image processing tasks; Step S2: Based on the first-stage training model and taking the parameters of the neural network model A as a benchmark, the attributes of the convolutional layer b parameters of the neural network model B to be frozen are set so that these parameters will not calculate the gradient during back propagation; Step S3: Loading the trained parameters related to the convolution layer a in the neural network model A into the convolution layer b, so that the convolution layer a and the convolution layer b maintain the same parameters; Step S4: After the neural network model A and the neural network model B are trained, the frozen parameters of the two models are compared to see whether they have not been updated during the training process, so as to verify the freezing effect.

8. A control method using the system of any one of claims 1 to 6, characterized in that: The method comprises the following steps: S1: setting an intra-core detection signal in a computing module in the shared module; S2: setting a first detection signal and a second detection signal in the last fully connected layer module of the neural network model A and the neural network model B to monitor the completion of different tasks; S3: The neural network model A can receive a new task when and only when the in-core detection signal is idle and the first detection signal indicates that the neural network model A has completed the previous task; the neural network model B can receive a new task when and only when the in-core detection signal is idle and the second detection signal indicates that the neural network model B has completed the previous task.

Images