A monitoring device and method for trench depth of split-gate MOSFET

Abstract

The present invention discloses a monitoring device and method for the groove depth of a separated gate MOSFET. By designing a plurality of components of different sizes, electrical tests are adopted to judge and quickly obtain the deviation of the groove depth of the separated gate MOSFET, without the need for destructive dissection tests on the chip. Moreover, according to the components of different sizes, the groove depth of the designated position area of ​​each wafer can be monitored. Compared with the traditional method, the monitoring frequency and range are more complete, the efficiency is higher and the cost is lower.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor detection technology, and in particular to a monitoring device and method for a trench depth of a separated gate MOSFET. Background Art

[0002] MOSFET chip is a semiconductor discrete device and a three-terminal device. According to its physical structure, MOSFET chips can be classified into two major categories: planar MOSFET and trench MOSFET. Split-gate MOSFET is a type of trench MOSFET chip. It uses the charge balance principle and has made great structural innovations compared to traditional trench MOSFET chips, so it can achieve lower on-resistance per unit area. In the split-gate MOSFET chip, two layers of heavily doped polysilicon are used to form the shield gate and control gate of the MOSFET chip respectively, where the shield gate and the epitaxial layer form a lateral charge balance to achieve the longitudinal withstand voltage of the MOSFET chip, and the control gate is used to control the opening and closing of the channel of the MOSFET chip.

[0003] The processing of split-gate MOSFET includes the main steps of trench formation, shield gate formation, control gate formation, body region and source region formation, contact hole and metal electrode formation, and centering. The trench formation process mainly includes the trench photolithography and etching process. The trench etching process is to form a trench of a specified depth in a set area by a plasma dry etching method.

[0004] The trench is a key structure in the split-gate MOSFET. Any deviation in the trench depth caused by process or equipment factors may cause changes in parameters and performance of the MOSFET, such as on-resistance and avalanche characteristics (EAS). Therefore, monitoring the trench depth is particularly important. At present, the method for monitoring the trench depth is to sample and dissect the chip and then use a scanning electron microscope (SEM) to observe and measure the trench depth at a high magnification. This method has obvious disadvantages, that is, it requires destructive dissection testing of the chip, so it is impossible to monitor every wafer in place, which has great limitations. Summary of the invention

[0005] The purpose of the present invention is to solve the technical problems existing in the background technology and to provide a monitoring device and method for the trench depth of a separated gate MOSFET.

[0006] In order to achieve the above technical objectives, the technical solution adopted in the first aspect of the present invention is as follows:

[0007] A monitoring device for the groove depth of a separated gate MOSFET comprises N components of different sizes, wherein N is a positive odd number, the components comprise a first layer, a second layer, a first electrode and a second electrode, the second layer is stacked on a first side of the first layer, the first electrode is mounted on the second layer, the second electrode is mounted on the second side of the first layer, the first layer comprises a groove and a silicon region, the groove surrounds the silicon region, the groove is sequentially filled with a first substance and a second substance, the second layer is provided with a first contact hole and a second contact hole, the first contact hole connects the groove with the first electrode, and the second contact hole connects the silicon region with the first electrode.

[0008] Preferably, the first layer includes an epitaxial layer close to the second electrode and a doped layer close to the second layer, wherein the epitaxial layer and the doped layer have opposite doping types.

[0009] Preferably, the first substance includes silicon oxide covering the inner wall of the trench.

[0010] Preferably, the second substance includes polysilicon filling the remaining space of the trench.

[0011] Preferably, the length of the silicon region is M times the width of the silicon region, where M>10.

[0012] Preferably, the width dimensions of the grooves in the N components decrease step by step, wherein the decreasing amplitude of the width dimension is in the range of 5%-10%.

[0013] Preferably, the epitaxial layer is of N type and the doped layer is of P type, or the epitaxial layer is of P type and the doped layer is of N type, wherein the epitaxial layer and the doped layer form a PN junction.

[0014] The technical solution adopted in the second aspect of the present invention is as follows:

[0015] A method for monitoring the trench depth of a split-gate MOSFET is applied to a monitoring device for the trench depth of a split-gate MOSFET as in any of the above solutions. The method for monitoring the trench depth of a split-gate MOSFET comprises:

[0016] Connecting the first electrodes of the N components to 0 volt respectively, and applying a preset voltage to the second electrodes of the N components;

[0017] Monitoring the leakage current from the first electrode to the second electrode to obtain N leakage current data;

[0018] Detecting whether there is an abnormal number of N leakage current data that exceeds a preset standard value;

[0019] The number of anomalies is compared with the median number of N components to determine the deviation of the trench depth of the split-gate MOSFET, wherein the median number is indivual.

[0020] Compared with the prior art, the present invention has the following beneficial technical effects: a plurality of components of different sizes are designed, and electrical tests are used to judge and quickly obtain the deviation of the trench depth of the separated-gate MOSFET for monitoring, without the need for destructive anatomical testing of the chip, and according to the components of different sizes, the trench depth of the specified position area of ​​each wafer can be monitored, and the monitoring frequency and range are more complete than those of traditional methods, and the efficiency is higher and the cost is lower. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic diagram of the planar structure of three components in the first aspect of the present invention;

[0022] Figure 2 A cross-sectional view of three components in an embodiment of the first aspect of the present invention;

[0023] Figure 3 This is a monitoring flow chart of an embodiment of the second aspect of the present invention.

[0024] Reference numerals: 100 first layer, 101 trench, 1011 first substance, 1012 second substance, 102 silicon region, 103 epitaxial layer, 104 doped layer, 200 second layer, 201 first contact hole, 202 second contact hole, 300 first electrode, 400 second electrode. DETAILED DESCRIPTION

[0025] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0026] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and the like are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", and the like may explicitly or implicitly include one or more features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0027] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or a specific connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood by specific circumstances.

[0028] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] like Figure 1 as well as Figure 2 As shown, the present invention provides a monitoring device for trench depth of a split-gate MOSFET in a first aspect, which includes N components of different sizes, wherein N is a positive odd number;

[0030] Specifically, in this embodiment, the monitoring device is actually located in the wafer dicing lane. Specifically, during the wafer etching and other chip preparation processes, the preparation of the monitoring device is also included in the process. The monitoring device includes N components of different sizes, wherein these components are ordered, and these size designs are pre-set test parameters. The maximum difference of these sizes is the maximum test range. It should be noted that in this embodiment, the median (i.e., the first The width of the groove 101 of the component with different sizes is the width of the groove of the chip cell area of ​​the monitored split-gate MOSFET. The size of the components is different because the components of different sizes represent different depths of the groove of the split-gate MOSFET. The number is selected as an odd number, so the median can be directly calculated using a simple formula If there are an even number, there are two medians, which is not convenient for subsequent judgment criteria.

[0031] The component includes a first layer 100, a second layer 200, a first electrode 300 and a second electrode 400. The second layer 200 is stacked on the first side of the first layer 100, the first electrode 300 is installed on the second layer 200, and the second electrode 400 is installed on the second side of the first layer 100. The first layer 100 includes a groove 101 and a silicon area 102. The groove 101 surrounds the silicon area 102. The groove 101 is filled with a first substance 1011 and a second substance 1012 in sequence. The second layer 200 is provided with a first contact hole 201 and a second contact hole 202. The first contact hole 201 connects the groove 101 and the first electrode 300, and the second contact hole 202 connects the silicon area 102 and the first electrode 300.

[0032] Specifically, the first electrode 300, the second layer 200, the first layer 100 and the second electrode 400 are stacked in sequence, and the groove 101 includes an annular groove and surrounds the silicon region 102. It should be noted that, as shown in the attached Figure 2 As shown, the groove 101 is surrounded by the silicon region 102, but does not surround the silicon region at the top and bottom (the top here refers to the side of the groove 101 close to the first electrode 300, and the bottom is the side of the groove 101 close to the second electrode 400). Since the width of the groove 101 is relatively narrow, there is not enough space to arrange the contact holes, so a wider groove is arranged on the periphery by adding a second layer 200 to arrange the first contact hole 201 and the second contact hole 202, wherein the second layer 200 is a dielectric layer.

[0033] As attached Figure 1 As shown, the groove 101 also includes a small groove with a shape similar to a matchstick. The small groove structure is connected in series to the annular groove, and the first contact hole 201 is connected to the small groove to achieve a smaller groove 101 width.

[0034] Furthermore, the first layer 100 includes an epitaxial layer 103 close to the second electrode 400 and a doped layer 104 close to the second layer 200 , wherein the epitaxial layer 103 and the doped layer 104 have opposite doping types.

[0035] The first substance 1011 includes silicon oxide covering the inner wall of the trench 101 , and the second substance 1012 includes polysilicon filling the remaining space of the trench 101 .

[0036] Specifically, polysilicon, silicon oxide and the epitaxial layer 103 constitute a lateral MOS capacitor, and the epitaxial layer 103 and the doped layer 104 constitute a PN junction. When the first electrode is connected to 0 volts and a set voltage is applied to the second electrode, the PN junction is in a reverse biased state, and the MOS capacitor is subjected to a high potential to form a lateral electric field. When the spacing and depth of the left and right grooves 101 and the doping concentration of the epitaxial layer 103 reach a set value (wherein this set value is a pre-set value), the space charge region formed by the left and right two sets of lateral electric fields just fills the epitaxial layer 103 between the left and right grooves 101, achieving charge balance. At this time, the voltage borne by the longitudinal PN junction is relatively small, so the leakage current between the two ports of the component is very small, usually less than 10 nanoamperes.

[0037] It should be noted that when the depth of the groove 101 is gradually reduced, the space charge region between the inner walls of the annular groove is not sufficient to withstand the set voltage, and the leakage current between the two ports of the component (ie, the first electrode 300 and the second electrode 400) is relatively large, usually greater than 100 nanoamperes.

[0038] Furthermore, the length of the silicon region 102 is M times the width of the silicon region 102 , where M>10.

[0039] Specifically, the length and width of the silicon region 102 in each component are consistent, wherein Figure 1 and Figure 2 As shown, the labels W1, W2 and W3 represent the widths of the silicon regions 102 in the three components respectively, and the labels Z1, Z2 and Z3 represent the lengths of the silicon regions 102 in the three components respectively. It should be noted that the width of the silicon region 102 is the distance between the inner walls of the annular grooves in the groove 101.

[0040] The widths of the grooves 101 in the N components decrease step by step, wherein the decreasing amplitude of the widths is in the range of 5%-10%.

[0041] like Figure 1 and Figure 2 As shown, reference numerals X1, X2 and X3 represent width dimensions of the grooves 101 in the three components, respectively, and reference numerals Y1, Y2 and Y3 represent depth dimensions of the grooves 101 in the three components, respectively.

[0042] The epitaxial layer 103 is of N type and the doped layer 104 is of P type, or the epitaxial layer 103 is of P type and the doped layer 104 is of N type, wherein the epitaxial layer 103 and the doped layer 104 form a PN junction.

[0043] like Figure 3 As shown, in a second aspect, the present invention provides a method for monitoring the trench depth of a split-gate MOSFET, which is applied to a monitoring device for the trench depth of a split-gate MOSFET as in any of the above schemes. The method for monitoring the trench depth of a split-gate MOSFET comprises:

[0044] S1, respectively connecting the first electrodes 300 in N components to 0 volt, and applying a preset voltage to the second electrodes 400 in several components;

[0045] S2, monitoring the leakage current from the first electrode 300 to the second electrode 400 to obtain N leakage current data;

[0046] S3, detecting whether there is an abnormal number of N leakage current data that exceeds a preset standard value;

[0047] S4. Compare the abnormal number with the median number of N components to determine the deviation of the trench depth of the split-gate MOSFET, wherein the median number is indivual.

[0048] Specifically, the width of the groove 101 in the N components involved decreases step by step, that is, X1>X2>X3......>Xn. Due to the inherent characteristics of the groove etching process, namely the plasma dry etching process, that is, the dry etching has a load effect, the wider the groove 101, the greater the etching depth, that is, Y1>Y2>Y3......>Yn.

[0049] In the actual use of this embodiment, The depth and width of the trench 101 of the (median) component are equal to the depth and width of the trench in the chip cell region of the monitored split-gate MOSFET;

[0050] The components with ranking numbers less than the median have trench 101 depths greater than the trench depths of the chip cell region of the monitored split-gate MOSFET;

[0051] The components with ranking numbers greater than the median have trench 101 depths less than the trench depth of the chip cell region of the monitored split-gate MOSFET, and the corresponding leakage current is relatively large.

[0052] When the etching depth of the groove 101 deviates, the depth of the groove 101 of the N components changes as a whole, specifically, becomes larger or smaller, so the number of components whose leakage current exceeds the set standard value changes, wherein the standard value is usually on the order of 100 nanoamperes, and can be specifically set according to the basic leakage current of the process platform of the monitored split-gate MOSFET;

[0053] As mentioned above, the number of abnormalities exceeding the set specification value is taken as the median number of N components by default, under which the depth of the trench 101 of the component does not deviate significantly from the trench depth of the split-gate MOSFET;

[0054] From the situation that the trench depth of the split-gate MOSFET is too small, the depth of the corresponding N components will become smaller, and the corresponding number of abnormalities exceeding the set specification value will increase and be greater than the median number of N components. In this way, the monitoring method can be used to reversely infer that when the number of abnormalities is less than the median number, the depth of all components is too large, which can directly indicate that the trench depth of the split-gate MOSFET is too large.

[0055] The specific value for determining whether the trench depth of the split-gate MOSFET is too large or too small is to directly look at the difference between the number of abnormalities and the median number, where the median number is indivual.

[0056] The above is a monitoring device and method for the trench depth of a separated gate MOSFET or multiple implementation methods provided in combination with specific content, and it is not intended that the specific implementation of the present invention is limited to these descriptions. Any method, structure, etc. similar to or identical to the present invention, or a number of technical deductions or replacements based on the concept of the present invention, should be considered as the scope of protection of the present invention.

Claims

1. A monitoring device for the trench depth of a split-gate MOSFET, arranged in a scribe line of a wafer, characterized in that: include: N components of different sizes, where N is a positive odd number; The components include: First layer (100); A second layer (200) laminated on a first side of the first layer (100); A first electrode (300) is mounted on the second layer (200); A second electrode (400) mounted on a second side of the first layer (100); The first layer (100) comprises a groove (101) and a silicon region (102), the groove (101) surrounds the silicon region (102), the groove (101) is filled with a first substance (1011) and a second substance (1012) in sequence, the first substance (1011) comprises silicon oxide covering the inner wall of the groove (101), and the second substance (1012) comprises polysilicon filling the remaining space of the groove (101); A first contact hole (201) and a second contact hole (202) are provided on the second layer (200), the first contact hole (201) connecting the groove (101) and the first electrode (300), and the second contact hole (202) connecting the silicon region (102) and the first electrode (300); The first layer (100) comprises an epitaxial layer (103) close to the second electrode (400) and a doped layer (104) close to the second layer (200), wherein the epitaxial layer (103) and the doped layer (104) have opposite doping types; The difference in size between the N components is the difference in width of the groove (101).

2. The device for monitoring the trench depth of a split-gate MOSFET according to claim 1, characterized in that: The length of the silicon region (102) is M times the width of the silicon region (102), where M>10.

3. The device for monitoring the trench depth of a split-gate MOSFET according to claim 1, characterized in that: The width dimensions of the grooves (101) in the N components decrease step by step, wherein the decreasing amplitude of the width dimensions is in the range of 5%-10%.

4. The device for monitoring the trench depth of a split-gate MOSFET according to claim 1, characterized in that: The epitaxial layer (103) is of N type and the doped layer (104) is of P type, or the epitaxial layer (103) is of P type and the doped layer (104) is of N type, wherein the epitaxial layer (103) and the doped layer (104) form a PN junction.

5. A method for monitoring the trench depth of a split-gate MOSFET, characterized in that: The apparatus for monitoring the trench depth of a split-gate MOSFET according to any one of claims 1 to 4, wherein the method for monitoring the trench depth of the split-gate MOSFET comprises: Connecting 0 volts to the first electrodes (300) in the N components respectively, and applying a preset voltage to the second electrodes (400) in the N components; monitoring the leakage current from the first electrode (300) to the second electrode (400) to obtain N leakage current data; Detecting whether there is an abnormal number of N leakage current data exceeding a preset standard value; The abnormal number is compared with the median number of the N components to determine the deviation of the depth of the trench (101) of the separated gate MOSFET, wherein the median number is indivual.

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