A surface acoustic wave wafer-level structure and manufacturing method thereof, and electronic equipment

Abstract

The present application discloses a surface acoustic wave wafer-level structure and a manufacturing method thereof, and an electronic device, and relates to the field of semiconductor technology. A packaging cover is introduced into the surface acoustic wave wafer-level structure as the bonding part of the WLP, and a plurality of raised columns are formed by processing the packaging cover to achieve the purpose of bonding with the substrate. Based on the characteristics of the packaging cover and the dry film, it can be known that the raised columns of the packaging cover are stronger than the support dam formed by the dry film. In the process of layout, the raised columns only need to exist around the chip and where there is a need for pad connection. Compared with the support dam in the double-layer dry film packaging technology, there is no need to consider the support problem. In other words, this technical solution has a huge improvement in reliability and support compared to the double-layer dry film packaging technology.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a surface acoustic wave wafer-level structure and a manufacturing method thereof, and an electronic device. Background Art

[0002] SAW (Surface Acoustic Wave) resonator is the abbreviation of surface acoustic wave resonator. It is a special filtering device made by using its piezoelectric effect and the physical characteristics of surface acoustic wave propagation. It is widely used in various fields, such as the radio frequency field. Among them, the surface acoustic wave is an elastic wave with energy concentrated near the surface. The design of the filter often uses the resonator as the basic unit, which can form the corresponding topology and amplify the specified frequency component signal.

[0003] Usually, the surface acoustic wave resonator produced will be packaged at the surface acoustic wave filter wafer level to obtain the surface acoustic wave filter. In the related art, the method for manufacturing the surface acoustic wave filter wafer level packaging is to first attach a first layer of dry film to the upper surface of the surface acoustic wave resonator, and form a support dam by etching the first layer of dry film. Then, a second layer of dry film is attached to the support dam to form the cavity of the surface acoustic wave filter.

[0004] However, based on the characteristics of the dry film, the strength of the support dam made of the first layer of dry film is relatively low and cannot effectively support the second layer of dry film, which will cause the second layer of dry film to collapse, thereby affecting the packaging effect of the surface acoustic wave wafer-level structure. Summary of the invention

[0005] In view of the above problems, the present application provides a surface acoustic wave wafer-level structure and a manufacturing method thereof, and an electronic device to achieve the purpose of improving the reliability of the surface acoustic wave wafer-level structure. The specific scheme is as follows:

[0006] A first aspect of the present application provides a surface acoustic wave wafer-level structure, the surface acoustic wave wafer-level structure comprising:

[0007] A substrate and a packaging cover plate are arranged opposite to each other, the packaging cover plate has a plurality of protruding columns, and the substrate and the packaging cover plate are packaged and connected via the plurality of protruding columns;

[0008] A piezoelectric film layer is located between the substrate and the packaging cover and on the substrate, and an interdigital electrode is located on a side of the piezoelectric film layer away from the substrate.

[0009] In a possible implementation, the packaging cover plate is a Si cover plate.

[0010] In a possible implementation, the surface acoustic wave wafer-level structure further includes:

[0011] At least one dielectric layer is located between the piezoelectric film layer and the substrate.

[0012] In a possible implementation, the surface acoustic wave wafer-level structure further includes:

[0013] a bonding layer at least between the raised pillar and the substrate;

[0014] The bonding layer includes: a first bonding layer disposed adjacent to the substrate, and a second bonding layer disposed adjacent to the protruding pillars.

[0015] In a possible implementation, the material of the first bonding layer and the second bonding layer is a metal material.

[0016] In a possible implementation, the material of the first bonding layer and the second bonding layer is gold material.

[0017] In a possible implementation, the first bonding layer is in contact with and connected to the interdigital electrodes.

[0018] In a possible implementation, the substrate has a through hole, and the through hole passes through the substrate;

[0019] The surface acoustic wave wafer-level structure further includes: an external lead structure, and the external lead structure is connected to the first bonding layer through the through hole.

[0020] A second aspect of the present application provides a method for manufacturing a surface acoustic wave wafer-level structure, the method for manufacturing a surface acoustic wave wafer-level structure comprising:

[0021] Providing a substrate, on which a piezoelectric film layer and at least one dielectric layer located between the piezoelectric film layer and the substrate are disposed;

[0022] forming interdigital electrodes on a side of the piezoelectric film layer facing away from the substrate;

[0023] Providing a packaging cover plate;

[0024] Processing the packaging cover plate to form a plurality of raised columns;

[0025] The substrate and the package cover are packaged and connected via the plurality of protruding columns.

[0026] A third aspect of the present application provides an electronic device, wherein the electronic device comprises the surface acoustic wave wafer-level structure described in any one of the above items.

[0027] Through the above technical solution, the present application provides a surface acoustic wave wafer-level structure and a manufacturing method thereof, and introduces a packaging cover plate in an electronic device as a bonding part of WLP (Wafer Level Package), and forms a plurality of raised columns by processing the packaging cover plate, so as to achieve the purpose of bonding with the substrate. Based on the characteristics of the packaging cover plate and the dry film, it can be known that the raised columns of the packaging cover plate are stronger than the support dam formed by the dry film. In the process of layout, the raised columns only need to exist around the chip and where there is a need for pad connection. Compared with the support dam in the double-layer dry film packaging technology, there is no need to consider the support problem. In other words, this technical solution has a huge improvement in reliability and support compared to the double-layer dry film packaging technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0029] Figure 1 A schematic diagram of the principle structure of a surface acoustic wave wafer-level structure provided by an embodiment of the present invention;

[0030] Figure 2 A schematic diagram of the principle structure of an interdigital electrode provided in an embodiment of the present invention;

[0031] Figure 3 A schematic flow chart of a method for manufacturing a surface acoustic wave wafer-level structure provided by an embodiment of the present invention;

[0032] Figure 4-Figure 16 for Figure 3 A partial structural schematic diagram corresponding to the method for manufacturing a surface acoustic wave wafer-level structure is shown. DETAILED DESCRIPTION

[0033] The following describes the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation method section of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0034] The embodiments of the present application are described below in conjunction with the accompanying drawings. Those skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0035] Combined with the content recorded in the background technology, the surface acoustic wave resonator and filter are an acoustic device widely used in the radio frequency field. They combine low insertion loss and good suppression performance, and are relatively small in size. They are used to filter out the interference of heterodyne signals, attenuate some frequency components, and only allow specified frequency components. They are the technical basis for the application of wireless spectrum as a non-renewable scarce resource. The specific principle can be simply understood as based on the piezoelectric properties of piezoelectric materials, using input and output transducer devices such as interdigital transducers to convert electrical signals into mechanical energy, and then convert them into electrical signals after processing, so as to amplify the required signals, filter out noise signals and improve signal quality. They are widely used in various wireless communication equipment.

[0036] At present, filters are mainly divided into SAW filters and BAW (Bulk Acoustic Wave) filters. Surface acoustic waves are an elastic wave that is generated and propagated on the surface of a piezoelectric substrate with piezoelectric properties, and whose amplitude decreases rapidly as the depth of the piezoelectric substrate increases. For SAW filters, their manufacturing cost is much lower than that of BAW filters. They are used in low-frequency bands, have low insertion loss and good suppression, and are temperature sensitive.

[0037] At the same time, it should be noted that SAW filters also have corresponding limitations. One of them is that they are easily affected by temperature changes. When the temperature rises, the stiffness of the base material tends to decrease and the sound speed will also decrease. It can also be said that SAW filters have the defect of temperature drift, that is, the frequency will drift with the operating temperature. Therefore, based on the traditional SAW filter, the TC-SAW filter, that is, the temperature-compensated SAW filter, is produced accordingly. It mainly utilizes the temperature compensation layer (such as SiO2 layer) and the piezoelectric film layer. The opposite temperature elastic characteristics realize compensation for the temperature drift characteristics.

[0038] It should be further explained that SAW filters also have product designs such as TF-SAW filters (thin film surface acoustic wave filters), in which the design of the filters often uses resonators as basic units, which can form the corresponding topology and amplify the specified frequency component signal.

[0039] Based on TC-SAW resonators, ordinary SAW resonators or TF-SAW resonators, the manufactured surface acoustic wave resonators will be packaged at the surface acoustic wave filter wafer level to obtain a surface acoustic wave filter. In the related art, the manufacturing method of the surface acoustic wave filter wafer level packaging first attaches a first layer of dry film to the upper surface of the surface acoustic wave resonator, and forms a support dam by etching the first layer of dry film. Then, a second layer of dry film is attached to the support dam to form the cavity of the surface acoustic wave filter.

[0040] However, based on the characteristics of the dry film, the strength of the support dam made of the first layer of dry film is relatively low and cannot effectively support the second layer of dry film, which will cause the second layer of dry film to collapse, thereby affecting the packaging effect of the surface acoustic wave wafer-level structure.

[0041] Based on this, the embodiment of the present invention provides a surface acoustic wave wafer-level structure and a manufacturing method thereof, and an electronic device, which is mainly divided into two parts from a structural point of view, namely, Device Wafer and Cap Wafer. The Device Wafer is the part where the surface acoustic wave device is located, which is the main working area of ​​the filter, mainly including a substrate, a piezoelectric film layer, and interdigital electrodes, etc.; the Cap Wafer is a structural component that is inverted on the Device Wafer and used for wafer-level packaging.

[0042] That is to say, in the present invention, a package cover is introduced as the bonding part of WLP (Wafer Level Package), and a plurality of raised columns are formed by processing the package cover to achieve the purpose of bonding with the substrate. At the same time, gold-gold bonding can also be introduced as the bonding process for the upper and lower wafers. Based on the characteristics of the package cover and the dry film, it can be seen that the raised columns of the package cover are stronger than the support dams formed by the dry film. In the process of layout, the raised columns only need to exist around the chip and where there are pad connection requirements. Compared with the support dams in the double-layer dry film packaging technology, there is no need to consider support issues. In other words, this technical solution has a huge improvement in reliability and support compared to the double-layer dry film packaging technology.

[0043] It should be noted that the surface acoustic wave wafer-level structure provided in the embodiment of the present invention includes but is not limited to the wafer-level structure of an ordinary SAW resonator, the wafer-level structure of a TC-SAW resonator or the wafer-level structure of a TF-SAW resonator. That is to say, the technical solution provided in the embodiment of the present invention can be applied to an ordinary SAW resonator, a TC-SAW resonator or a TF-SAW resonator. In the embodiment of the present invention, only the application to the TF-SAW resonator is used as an example for explanation.

[0044] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0045] refer to Figure 1 , Figure 1 A schematic diagram of the principle structure of a surface acoustic wave wafer-level structure provided by an embodiment of the present invention. A surface acoustic wave wafer-level structure provided by an embodiment of the present invention includes:

[0046] The substrate 11 and the packaging cover plate 12 are arranged opposite to each other. The packaging cover plate 11 has a plurality of protruding columns 13 . The substrate 11 and the packaging cover plate 12 are packaged and connected via the plurality of protruding columns 13 .

[0047] A piezoelectric film layer 14 is located between the substrate 11 and the package cover plate 12 and on the substrate 11 , and an interdigital electrode 15 is located on a side of the piezoelectric film layer 14 away from the substrate 11 .

[0048] Specifically, in the embodiment of the present invention, the package cover plate 12 may be a Si cover plate, that is, the package cover plate 12 may be obtained by processing a Si wafer, as shown in FIG. Figure 2 , Figure 2 A schematic diagram of the principle structure of an interdigitated electrode provided in an embodiment of the present invention, the interdigitated electrode 15 includes a bus bar and electrode fingers, the bus bar includes a first bus bar 151 and a second bus bar 152 arranged opposite to each other in a first direction X, the electrode fingers include a first electrode finger 153 located on the first bus bar 151 and a second electrode finger 154 located on the second bus bar 152; the first bus bar 151 and the second bus bar 152 have the same length extension direction, both extending along the second direction Y, the first direction X and the second direction Y are parallel to the plane where the substrate 11 is located, and the first direction X and the second direction Y intersect, and in the embodiment of the present invention, the first direction X and the second direction Y are perpendicular to each other for illustration.

[0049] The length extension direction of the first electrode fingers 153 and the second electrode fingers 154 is parallel to the first direction X, the multiple first electrode fingers 153 on the first bus bar 151 are arranged at intervals in the second direction Y, the multiple second electrode fingers 154 on the second bus bar 152 are arranged at intervals in the second direction Y, and the multiple first electrode fingers 153 on the first bus bar 151 and the multiple second electrode fingers 154 on the second bus bar 152 are arranged crosswise in sequence in the second direction Y, and there is a gap between the multiple first electrode fingers 153 on the first bus bar 151 and the second bus bar 152, and there is a gap between the multiple second electrode fingers 154 on the second bus bar 152 and the first bus bar 151. At this time, the bus bars and the electrode fingers are distributed in a manner similar to crossing fingers, forming a so-called interdigitated electrode 15. When the first bus bar 151 and the first electrode fingers 153 thereon are used as the transmitting end, the second bus bar 152 and the second electrode fingers 154 thereon are used as the receiving end. Conversely, when the first bus bar 151 and the first electrode fingers 153 thereon are used as the receiving end, the second bus bar 152 and the second electrode fingers 154 thereon are used as the transmitting end. The transmitting end is used to convert the electrical signal into an acoustic wave, and the acoustic wave mainly propagates on the surface of the piezoelectric film layer. The receiving end is used to convert the received acoustic wave into an electrical signal output, thereby realizing filtering.

[0050] The SAW wafer-level structure is mainly divided into two parts, namely, Device Wafer and Cap Wafer. Device Wafer is the part where the SAW device is located, which is the main working area of ​​the filter and mainly includes the substrate, piezoelectric film layer and interdigital electrodes; Cap Wafer is a structural component that is inverted on the Device Wafer and used for wafer-level packaging.

[0051] That is to say, in the embodiment of the present invention, the package cover plate 12 is introduced as the bonding part of the WLP (Wafer Level Package), and a plurality of raised columns 13 are formed by processing the package cover plate 12 (when the package cover plate is a Si cover plate, the raised columns 13 are raised silicon columns), so as to form the purpose of bonding with the substrate 11. Based on the characteristics of the package cover plate 12 and the dry film, it can be known that the raised columns 13 of the package cover plate 12 are stronger than the support dam formed by the dry film. In the process of layout, the raised columns 13 only need to exist around the chip and where there is a need for pad connection. Compared with the support dam in the double-layer dry film packaging technology, there is no need to consider the support problem. In other words, this technical solution has a huge improvement in reliability and support compared to the double-layer dry film packaging technology.

[0052] Furthermore, based on the double-layer dry film packaging technology, in order to improve the strength of the support dam, the width of the support dam is usually increased. Obviously, this operation is not conducive to the miniaturization design of the chip. However, since the protruding column 13 in the embodiment of the present application does not have the problem of support strength, it can also indirectly illustrate that the present technical solution has a huge improvement in the aspect of chip miniaturization design compared with the double-layer dry film packaging technology.

[0053] In an optional embodiment of the present invention, Figure 1 As shown, the surface acoustic wave wafer-level structure provided by the embodiment of the present invention also includes:

[0054] At least one dielectric layer is located between the piezoelectric film layer 14 and the substrate 11 .

[0055] Specifically, in the embodiment of the present invention, the dielectric layer between the piezoelectric film layer 14 and the substrate 11 can be any number of dielectric layers such as an insertion layer, a protective layer, an adjustment layer, a temperature compensation layer, a speed change layer, etc., to form a stacked layer structure, thereby achieving a variety of different technical effects. In the embodiment of the present invention, the number and function of the dielectric layer are not limited, and only two dielectric layers (i.e., a first dielectric layer 16 and a second dielectric layer 17) between the piezoelectric film layer 14 and the substrate 11 are used as an example for explanation.

[0056] In an optional embodiment of the present invention, Figure 1 As shown, the surface acoustic wave wafer-level structure provided by the embodiment of the present invention also includes:

[0057] A bonding layer is at least located between the protruding pillar 13 and the substrate 11 .

[0058] The bonding layer includes: a first bonding layer 18 disposed adjacent to the substrate 11 , and a second bonding layer 19 disposed adjacent to the protruding pillars 13 .

[0059] Specifically, in the embodiment of the present invention, the materials of the first bonding layer 18 and the second bonding layer 19 are metal materials. Exemplary materials of the first bonding layer 18 and the second bonding layer 19 are gold materials, that is, in the embodiment of the present invention, the package cover plate 12 is introduced as the bonding part of the WLP (Wafer Level Package), and the package cover plate 12 is processed to form a plurality of raised columns 13 (when the package cover plate is a Si cover plate, the raised columns 13 are raised silicon columns), so as to form the purpose of bonding with the substrate 11. Based on the characteristics of the package cover plate 12 and the dry film, it can be known that the raised columns 13 of the package cover plate 12 are stronger than the support dam formed by the dry film. Further, in the embodiment of the present invention, a gold-gold bonding process is introduced as the bonding process of the upper and lower wafers to further improve the bonding strength. In the process of layout, the raised columns 13 only need to exist around the chip and where there is a need for pad connection. Compared with the support dam in the double-layer dry film packaging technology, there is no need to consider the support problem.

[0060] In general, this technical solution has a huge improvement in reliability and support compared to the double-layer dry film packaging technology.

[0061] Further, such as Figure 1 As shown, the bonding surface of each of the protruding columns 13 also has a plurality of independent small protrusions, which can form a bite-like manner after bonding to increase the contact surface between the first bonding layer 18 and the second bonding layer 19 as much as possible, thereby further improving the bonding effect.

[0062] In an optional embodiment of the present invention, Figure 1 As shown, the first bonding layer 18 is in contact with the interdigital electrodes 15 , and the substrate 11 has a through hole 20 , and the through hole 20 penetrates the substrate 11 .

[0063] The surface acoustic wave wafer-level structure further includes an external lead structure 21 , and the external lead structure 21 is connected to the first bonding layer 18 through the through hole 20 .

[0064] Specifically, in the embodiment of the present invention, when the first bonding layer 18 is made of metal material, it can also be contacted and connected with the interdigital electrodes 15, and connected to the external lead structure 21 through the through hole 20 on the substrate 11, so as to realize the connection between the external components or external circuits and the surface acoustic wave wafer-level structure to achieve the desired functions.

[0065] For example, a copper column or a solder ball or other structure may be provided on the external lead structure 21 to realize the connection of external components, which is not limited in the embodiment of the present invention.

[0066] Based on the above embodiment of the present invention, another embodiment of the present invention further provides a method for manufacturing a surface acoustic wave wafer-level structure, referring to Figure 3 , Figure 3 A schematic flow chart of a method for manufacturing a surface acoustic wave wafer-level structure provided by an embodiment of the present invention. The method for manufacturing a surface acoustic wave wafer-level structure provided by an embodiment of the present invention includes:

[0067] S101: Figure 4 As shown, a substrate 11 is provided, on which a piezoelectric film layer 14 and at least one dielectric layer located between the piezoelectric film layer 14 and the substrate 11 are disposed.

[0068] Specifically, in this step, two dielectric layers (ie, a first dielectric layer 16 and a second dielectric layer 17) are provided between the piezoelectric film layer 14 and the substrate 11 as an example for description. Figure 4 The structure shown can also be understood as the structure of an incoming wafer.

[0069] S102: Figure 5-Figure 9 As shown, interdigital electrodes 15 are formed on a side of the piezoelectric film layer 14 facing away from the substrate 11 .

[0070] Specifically, in this step, Figure 5 As shown, the piezoelectric film layer 14 is thinned to reach the required thickness; Figure 6 As shown, the piezoelectric film layer 14 and the dielectric layer between the piezoelectric film layer 14 and the substrate 11 are patterned; Figure 7 As shown, interdigital electrodes 15 are formed on the side of the piezoelectric film layer 14 facing away from the substrate 11 .

[0071] For example, Figure 8 As shown, after the interdigital electrodes 15 are formed, a passivation layer 22 may be formed on the side of the interdigital electrodes 15 facing away from the substrate 11 to achieve passivation protection for the interdigital electrodes 15 .

[0072] For example, Fig. 9As shown, after the passivation layer 22 is formed, the first bonding layer 18 is formed. The material of the first bonding layer 18 is described by taking gold material as an example. The first bonding layer 18 is in contact with and connected to the interdigital electrodes 15 .

[0073] S103: Fig.10 As shown, a packaging cover 12 is provided.

[0074] S104: Figure 11-13 As shown, the package cover plate 12 is processed to form a plurality of protruding pillars 13 .

[0075] Specifically, in this step, Fig.11 As shown, one side surface of the package cover plate 12 is patterned to form a bonding portion pattern; Fig.12 As shown in FIG. 1 , a second bonding layer 19 is formed on the side with the patterned bonding portion, and the material of the second bonding layer 19 is described by taking gold material as an example; Fig.13 As shown, the second bonding layer 19 is patterned to form a plurality of protruding pillars 13 at the same time.

[0076] S105: Fig.14 and Figure 1 As shown, the substrate 11 and the packaging cover plate 12 are packaged and connected through the plurality of protruding pillars 13 .

[0077] Specifically, in this embodiment, Fig.14 As shown, the bonding surface of each of the protruding columns 13 also has a plurality of independent small protrusions, which can form a bite-like manner after bonding to increase the contact surface between the first bonding layer 18 and the second bonding layer 19 as much as possible, thereby further improving the bonding effect.

[0078] For example, Fig.15 As shown, after the bonding is completed, the substrate 11 may be ground to be thinned to a target thickness, which is not limited in the embodiment of the present invention and may be determined according to actual conditions.

[0079] For example, Fig.16 As shown, after the substrate 11 is thinned, the substrate 11 may be further etched, namely, TSV (Through Silicon Via) etching, to form a through hole 20 penetrating the substrate 11 .

[0080] For example, Figure 1 As shown, an external lead structure 21 is formed, and the external lead structure 21 is connected to the first bonding layer 18 through the through hole 20 .

[0081] It should be noted that Figure 1 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.14 , Fig.15 and Fig.16 The side walls of the whole formed by the piezoelectric film layer 14, the first dielectric layer 16 and the second dielectric layer 17 can also be inclined side walls, for example, the size of the whole formed by the piezoelectric film layer 14, the first dielectric layer 16 and the second dielectric layer 17 gradually decreases in the direction from the substrate 11 to the packaging cover plate 12.

[0082] Based on the above embodiments of the present invention, another embodiment of the present invention further provides an electronic device, which includes the surface acoustic wave wafer-level structure described in the above embodiments.

[0083] The above is a detailed introduction to a surface acoustic wave wafer-level structure and a manufacturing method and an electronic device provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

[0084] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0085] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device that includes a series of elements is inherent to the elements, or also includes elements inherent to these processes, methods, articles or devices. In the absence of further restrictions, the elements defined by the sentence "including a..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0086] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A surface acoustic wave wafer-level structure, characterized in that: The surface acoustic wave wafer-level structure comprises: A substrate and a packaging cover plate are arranged opposite to each other, the packaging cover plate has a plurality of protruding columns, and the substrate and the packaging cover plate are packaged and connected via the plurality of protruding columns; a piezoelectric film layer located between the substrate and the package cover and on the substrate, and an interdigitated electrode located on a side of the piezoelectric film layer facing away from the substrate; The surface acoustic wave wafer-level structure further includes: at least one dielectric layer located between the piezoelectric film layer and the substrate; The surface acoustic wave wafer-level structure further includes: a bonding layer at least between the raised pillar and the substrate; The bonding layer includes: a first bonding layer disposed adjacent to the substrate, and a second bonding layer disposed adjacent to the protruding pillar; The first bonding layer is in contact with the interdigital electrodes.

2. The surface acoustic wave wafer-level structure according to claim 1, characterized in that: The packaging cover plate is a Si cover plate.

3. The surface acoustic wave wafer-level structure according to claim 1, characterized in that: The first bonding layer and the second bonding layer are made of metal materials.

4. The surface acoustic wave wafer-level structure according to claim 3, characterized in that: The first bonding layer and the second bonding layer are made of gold.

5. The surface acoustic wave wafer-level structure according to claim 3, characterized in that: The substrate has a through hole, and the through hole penetrates the substrate; The surface acoustic wave wafer-level structure further includes: an external lead structure, and the external lead structure is connected to the first bonding layer through the through hole.

6. A method for manufacturing a surface acoustic wave wafer-level structure, characterized in that: The method for manufacturing a surface acoustic wave wafer-level structure is used to prepare the surface acoustic wave wafer-level structure according to any one of claims 1 to 5, and the method for manufacturing a surface acoustic wave wafer-level structure comprises: Providing a substrate, on which a piezoelectric film layer and at least one dielectric layer located between the piezoelectric film layer and the substrate are disposed; forming interdigital electrodes on a side of the piezoelectric film layer facing away from the substrate; Providing a packaging cover plate; Processing the packaging cover plate to form a plurality of raised columns; The substrate and the package cover are packaged and connected via the plurality of protruding columns.

7. An electronic device, characterized in that: The electronic device comprises the surface acoustic wave wafer-level structure according to any one of claims 1-5.

Images