AI accelerator architecture and AI chip based on the architecture

Abstract

The present invention relates to the field of integrated circuits, and discloses an AI accelerator architecture and an AI chip based on the architecture, wherein the AI ​​accelerator architecture comprises: a RISC-V processor, an in-memory computing accelerator and an instruction extension interface; the RISC-V processor is used to obtain and decode extended instructions for controlling the in-memory computing accelerator to perform operations; the instruction extension interface is used for the RISC-V processor to send decoded extended instructions to the in-memory computing acceleration core; the in-memory computing accelerator is used to perform corresponding operations according to the received extended instructions. The present invention has a high efficiency in sending extended instructions. The present invention is suitable for low-power AI chips.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to an AI accelerator architecture and an AI chip based on the architecture. Background Art

[0002] With the rapid development of artificial intelligence (AI) technology, the scale demand of AI algorithms has exploded, which has put forward higher requirements on the performance and cost of AI chips. The domain-specific architecture (DSA) based on the traditional von Neumann architecture faces extremely high memory access overhead when executing data and computing-intensive tasks such as artificial intelligence, high-performance computing, and video processing. Due to the bandwidth bottleneck between the memory and the processor, the delay caused by the data transfer between the processor and the memory seriously limits the improvement of the processor's computing efficiency. At present, the computing-in-memory (CIM) architecture, which combines the storage unit and the computing unit into one, can effectively avoid frequent data transfer and reduce the storage requirements of intermediate data. This feature makes computing-in-memory an effective hardware deployment solution for artificial intelligence applications. However, the storage-computing-in-one acceleration engine architecture usually lacks certain versatility and flexibility, which limits its use in a wider range of application scenarios.

[0003] In order to improve its versatility, flexibility and practical application capabilities, a common solution is to expand new instructions suitable for AI computing based on the existing CPU instruction set. RISC-V, due to its relatively streamlined instruction set architecture (ISA) and open source and relaxed BSD protocol, makes it possible to perform arbitrary architecture expansion and customization based on the RISC-V architecture. However, RISC-V and in-memory computing accelerators use different heterogeneous architectures, and their instruction and data transmission efficiency is different, resulting in different CPU control efficiency.

[0004] Figure 1 FIG. 1 is a schematic diagram of a heterogeneous mode of in-memory computing and RISC-V in the prior art. In this heterogeneous architecture, the in-memory computing accelerator and RISC-V are coupled via a system bus. The instruction sending process of this coupling mode is as follows: Figure 2 As shown in the figure, since the in-memory computing acceleration engine instruction is a piece of data for RISC-V, and this data requires RISC-V to execute several instructions to generate a complete in-memory computing extension instruction. RISC-V then sends the generated in-memory computing extension instruction to the bus. Since other components on the bus matrix will occupy the bus matrix, the instruction needs to wait for the bus to be idle before it can be written into the bus through the bus handshake protocol. Therefore, the efficiency of the CPU sending extension instructions is very low. Summary of the invention

[0005] The present invention provides an AI accelerator architecture and an AI chip based on the architecture, which have high extended instruction sending efficiency.

[0006] The present invention provides an AI accelerator architecture, comprising: a RISC-V processor, an in-memory computing accelerator and an instruction extension interface; the RISC-V processor is used to obtain and decode extended instructions for controlling the in-memory computing accelerator to perform operations; the instruction extension interface is used for the RISC-V processor to send the decoded extended instructions to the in-memory computing acceleration core; the in-memory computing accelerator is used to perform corresponding operations according to the received extended instructions.

[0007] The present invention also provides an AI chip that adopts the above-mentioned AI accelerator architecture.

[0008] In the embodiment of the present invention, the storage-computation-integrated acceleration engine based on RISC-V extended instructions flexibly controls the storage-computation-integrated array by extending the instruction set, and at the same time, it is easy to develop the upstream system software stack for storage-computation-integrated, integrate storage-computation-integrated into the RISC-V ecosystem, has higher versatility and flexibility, and can better adapt to a wider range of application scenarios; by setting the instruction extension interface to send extended instructions to control the in-memory computing accelerator, the instruction sending efficiency is greatly improved; a general acceleration engine is set in the in-memory computing accelerator to execute operators of other formats, which ensures the computational completeness of the in-memory computing accelerator, so that the in-memory computing array can give full play to the maximum hardware advantage when performing matrix multiplication related operations; in addition, a vector or matrix accelerator is also set in the RISC-V processor so that it can also be applied when the neural network algorithm is updated and iterated, and has versatility in a larger application range. Due to the above advantages, the storage-computation-integrated chip architecture in the present invention can realize high-energy-efficiency matrix multiplication, which meets the current needs of data and computing-intensive task loads such as artificial intelligence, high-performance computing, and video processing, and also meets the current social needs for energy saving and consumption reduction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0010] Figure 1 A schematic diagram of the heterogeneous mode of in-memory computing and RISC-V in the prior art;

[0011] Figure 2 for Figure 1 Schematic diagram of the instruction sending process in the system bus coupling mode;

[0012] Figure 3 A schematic diagram of the structure of an AI accelerator architecture provided by an embodiment of the present invention;

[0013] Figure 4A-4C Schematic diagrams of three specific AI accelerator architectures provided for embodiments of the present invention;

[0014] Figure 5A-Figure 5B A schematic diagram of the data path between the storage-computing integrated acceleration engine and the general acceleration engine;

[0015] Fig. 6A for Figure 5A-Figure 5B The schematic diagram of data calculation in the storage-computing integrated acceleration engine shown;

[0016] Figure 6B for Figure 5A-Figure 5B A schematic diagram of a vector accelerator and a matrix accelerator in a general acceleration engine is shown;

[0017] Figure 7 This is a schematic diagram of the structure of a storage-computing integrated acceleration engine in an embodiment of the present invention;

[0018] Figure 8A-8B Schematic diagram of an instruction sending interface in a RISC-V processor in an embodiment of the present invention;

[0019] Fig. 9 A schematic diagram of a parallel design scheme for a RISC-V processor and an in-memory computing accelerator in an embodiment of the present invention;

[0020] Fig.10 A schematic diagram of the effect of parallelization of a RISC-V processor and an in-memory computing accelerator in an embodiment of the present invention;

[0021] Fig.11 A schematic diagram comparing the efficiency of bus-coupled instructions and data transmission in an instruction expansion interface in an embodiment of the present invention and in the prior art;

[0022] Fig.12 A schematic diagram of the specific structure of an AI chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] As mentioned above, in the prior art, the in-memory computing accelerator and RISC-V are coupled through the system bus. This coupling method has a very low instruction sending efficiency because the in-memory computing extension instructions need to wait for the bus to be idle and can only be written to the bus through the bus protocol handshake. To this end, an embodiment of the present invention provides an AI accelerator architecture, which controls the in-memory computing accelerator by configuring an instruction extension interface instead of bus coupling, and uses an instruction extension dedicated interface to send instructions without waiting for the bus matrix to be idle. At the same time, since the in-memory computing instructions are an extended instruction of RISC-V, they have been pre-arranged during compilation, and there is no need to generate them in real time through multiple RISC-V instructions, so the instruction sending efficiency can be effectively improved.

[0025] To make the technical solution of the present invention clearer, embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] Figure 3 A schematic diagram of the structure of an AI accelerator architecture provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown, the AI ​​accelerator architecture of this embodiment includes: a RISC-V processor, an in-memory computing accelerator and an instruction extension interface; the RISC-V processor is used to obtain and decode extended instructions that control the in-memory computing accelerator to perform operations; the instruction extension interface is used for the RISC-V processor to send decoded extended instructions to the in-memory computing acceleration core; the in-memory computing accelerator is used to perform corresponding operations according to the received extended instructions.

[0027] In this embodiment, the RISC-V processor first obtains and decodes the extended instructions for controlling the in-memory computing accelerator to perform operations. The extended instructions can be pre-compiled instructions stored in the instruction memory. When performing in-memory computing, the RISC-V processor reads the instructions from the instruction memory, and after decoding, directly sends them to the in-memory computing accelerator through the configured instruction extension interface. After receiving the instructions, the in-memory computing accelerator performs corresponding operations according to the received decoded extended instructions. Since the instructions are sent through the configured instruction extension dedicated interface instead of the system bus matrix, there is no need to wait for the bus matrix to be idle, and there is no need to interact with the matrix bus by handshake, which greatly saves the waiting time before sending instructions; and since the extended instructions for executing a certain neural network operation are usually pre-arranged, the instructions can also be sent in batches at the same time, thereby effectively improving the efficiency of instruction sending.

[0028] In practical applications, the AI ​​accelerator architecture in the above embodiment can be implemented using three architectures: Figure 4A-4C Schematic diagram of three AI accelerator architectures provided in embodiments of the present invention, wherein Figure 4AIn the design architecture shown, the integrated memory and computing acceleration engine in the in-memory computing accelerator is used to perform matrix multiplication operations, while other neural network operators are executed by the vector or matrix accelerator in the RISC-V processor. Instructions to control the in-memory computing accelerator are sent by the RISC-V processor through the instruction extension interface; in order to increase the RISC-V data access bandwidth, this design usually requires a data cache. The in-memory computing accelerator and RISC-V exchange data through the shared memory on the bus. That is to say, after the integrated memory and computing acceleration engine completes matrix-related operations, it saves the data in the shared memory, and RISC-V accesses the data through the bus interface to execute neural network operators other than matrix multiplication. In order to reduce the data interaction between the RISC-V processor and the in-memory computing accelerator, and to reduce the complexity of the memory system of the heterogeneous architecture and avoid introducing a data cache, Figure 4B In the design architecture shown, a general acceleration engine is configured in the in-memory computing accelerator, that is, a vector or matrix acceleration unit is introduced to complete other neural network operators except matrix multiplication. Therefore, this architecture reduces the computing power demand of RISC-V, and there is no need to introduce Cache to improve the bandwidth of RISC-V. Data frequently interacts inside the in-memory computing accelerator, forming a tightly coupled structure between the in-memory computing core and the vector computing core. With the continuous update and iteration of the neural network algorithm, new operators are constantly generated accordingly, which may cause the vector or matrix acceleration unit in the general acceleration engine of the in-memory computing accelerator to be unable to implement this type of operator. To this end, the present invention Figure 4C In the design architecture shown, the vector or matrix accelerator in the RISC-V processor is still maintained to update the neural network operator to ensure that the AI ​​accelerator is still applicable when the algorithm is updated. In this architecture, the shared memory configured on the bus matrix has a function similar to Figure 4A It is used for data exchange between RISC-V processors and in-memory computing accelerators.

[0029] In the above three design architectures, the control instructions sent by the RISC-V processor to the in-memory computing accelerator are all sent through the configured instruction expansion interface without passing through the bus matrix. Therefore, there is no need to wait for the bus matrix to be idle, nor is there any need to handshake with the matrix bus, which greatly saves the waiting time before sending instructions.

[0030] In the above Figure 4B and Figure 4CIn the architecture shown, the data in the in-memory computing accelerator includes tensors and vectors, and the computing engine of the data includes an integrated storage and computing acceleration engine and a general acceleration unit. The general acceleration engine is used to make up for the computational completeness of the integrated storage and computing acceleration engine. The general computing acceleration engine can be composed of a vector accelerator or a matrix accelerator, both of which contain multiple ALU operation units for calculating other neural network operators except matrix multiplication, so as to make up for the computational completeness of the integrated storage and computing acceleration engine. Figure 6B The storage-computation acceleration engine is used to perform vector-tensor multiplication and accumulation operations or tensor-tensor multiplication operations, such as Fig. 6A shown.

[0031] The data interaction between the storage-computing integrated acceleration engine and the general acceleration engine can be as follows: Figure 5A or Figure 5B The structure shown in the figure is implemented, the data outside the in-memory computing accelerator is loaded and stored in advance by the off-chip on-chip data loading unit configured on the in-memory computing accelerator, and the data is only exchanged inside the accelerator during the calculation process. Figure 5A In the structure shown, after the data is loaded into the off-chip on-chip data loading unit of the accelerator, it is sent to the unified local storage unit and the storage-computing integrated acceleration engine set in the accelerator. During the operation process, the general acceleration engine and the storage-computing integrated acceleration engine interact with the unified local storage unit through the data exchange network to perform data access. In actual applications, the data interaction between the general acceleration engine and the storage-computing integrated acceleration engine can also be completed through a direct data path to reduce on-chip data transmission. Figure 5B In the structure shown, after the data is loaded into the off-chip on-chip data loading unit of the accelerator, it is sent to the storage-computation integrated acceleration engine storage unit, the general acceleration engine storage unit and the storage-computation integrated acceleration engine set in the accelerator respectively. The data generated during the calculation process of the storage-computation integrated acceleration engine and the general acceleration engine are temporarily stored in the corresponding storage-computation integrated acceleration engine storage unit and the general acceleration engine storage unit, and the two interact through the data transfer unit. In the above two structures, the data storage used by the storage-computation integrated acceleration engine and the general acceleration engine can be divided into a unified local memory or each computing engine has a separate data storage. When a unified local memory is used, the storage-computation integrated acceleration engine and the general acceleration engine interact with the unified local storage unit using a data exchange network. Using a unified local storage unit, that is, vector, matrix, and tensor data structures are all stored in a unified local storage in a unified storage form, avoiding the use of different storage resources to store different data structures, reducing storage area overhead and on-chip data handling. When the two computing engines use different memories, data interaction is performed through the data transfer unit. Regardless of which structure is used, an off-chip on-chip data loading unit is used to realize off-chip and on-chip data transmission.

[0032] The storage-computing integrated acceleration engine in the above embodiment can be a single-macro-unit storage-computing integrated acceleration engine or a multi-macro-unit storage-computing integrated acceleration engine. When the storage-computing integrated acceleration engine is a multi-macro-unit storage-computing integrated acceleration engine, multiple storage-computing integrated macro-units are configured in the storage-computing integrated acceleration engine, and the connection relationship of each storage-computing integrated macro-unit is adjusted through a configurable switch network.

[0033] Figure 7 FIG. 1 is a schematic diagram of the structure of the storage-computing integrated acceleration engine in an embodiment of the present invention. Figure 7 As shown, in the multi-macrocell storage-computation integrated acceleration engine, multiple storage-computation integrated macrocells configure the switch network through configurable information, thereby changing the connection relationship of the storage-computation integrated macrocells and realizing flexible network mapping of different sizes. Inside the storage-computation integrated macrocell, its input processing circuit and output processing circuit preprocess the input and output data respectively, and the multiplication results of the internal storage unit and the calculation unit are accumulated through the adder. The storage unit can be designed as a single storage unit and a sub-array formed by multiple single storage units.

[0034] In an embodiment of the present invention, the extended instruction for controlling the in-memory computing accelerator is sent through an instruction extension interface, which may be a single instruction sending interface or a multi-instruction sending interface, such as Figure 8A-8B As shown in FIG. 1 , when the instruction extension interface is a multi-instruction sending interface, a data dependency detection module is configured in the RISC-V processor, which detects the extended instructions that can be sent simultaneously according to the data dependency, so that the detected extended instructions that can be sent simultaneously are sent through the multi-instruction sending interface. Correspondingly, the instruction interface will configure the corresponding data sending interface and data return interface, which will interact with the register stack in the RISC-V processor, such as Fig. 8A As shown. The multi-instruction transmission interface can ensure that multiple instructions are sent at the same time, which is beneficial to the efficiency of instruction transmission. In the design of a single extended instruction transmission interface, the RISC-V processor can only send one extended instruction at a time, and there are two corresponding data transmission interfaces and data return interfaces. These interface configurations comply with the RISC-V R-type instruction standard.

[0035] In order to enable the RISC-V processor and the in-memory computing accelerator to work in parallel and reduce waiting time, in an embodiment of the present invention, an instruction FIFO and an instruction scheduling unit are provided in the in-memory computing accelerator, such as Fig. 9As shown, the instruction FIFO is used to cache the extended instructions sent by the RISC-V processor through the instruction extension interface; the instruction scheduling unit is used to allocate the extended instructions cached in the instruction FIFO to the corresponding functional modules in the in-memory computing accelerator according to their functions, so that the functional modules perform corresponding operations according to the received extended instructions. That is, after the in-memory computing accelerator receives the instruction, it saves the instruction in the FIFO. At this time, RISC-V does not have to wait for the execution of the instruction to be completed, but continues to execute subsequent operations. The instructions saved in the instruction FIFO are automatically scheduled and allocated by the instruction scheduling unit in the in-memory computing accelerator. Fig.10 FIG. 1 is a schematic diagram of the effect of parallelization of a RISC-V processor and an in-memory computing accelerator in an embodiment of the present invention. Fig.10 As shown in the figure, for an extended instruction, the number of cycles to be executed is usually large. When RISC-V completes sending an instruction, the in-memory computing accelerator starts to execute the instruction, and synchronously RISC-V prepares to send the next instruction. If the RISC-V processor extended instruction 2 arrives, the in-memory computing accelerator has not yet completed the execution of the first instruction. The in-memory computing accelerator caches instruction 2 in the instruction FIFO to solve the instruction sending waiting problem. Through this design method, RISC-V and the in-memory computing accelerator can work in parallel.

[0036] In addition, in the instruction set design, when an extended instruction does not require the in-memory computing accelerator to return data through the data return interface, the in-memory computing accelerator will receive the instruction and immediately return the end mark of the instruction to the RISC-V processor.

[0037] Fig.11 FIG. 1 is a schematic diagram comparing the efficiency of the instruction expansion interface in the embodiment of the present invention and the bus coupling instruction and data transmission in the prior art, Fig.11 It can be seen that the present invention adopts the instruction expansion interface to avoid the problem of waiting for the bus to be idle before sending instructions, the instruction sending efficiency is greatly improved, and the waste of in-memory computing power is reduced.

[0038] An embodiment of the present invention also provides an AI chip that adopts the above-mentioned AI accelerator architecture. Fig.12 A schematic diagram of the specific structure of an AI chip provided by an embodiment of the present invention is shown in FIG. Fig.12As shown, in this embodiment, after the extended instructions are designed according to the algorithm that needs to be accelerated by the neural network, they are temporarily stored in the instruction memory. When the chip performs accelerated calculations, the RISC-V processor first reads the pre-stored instructions from the instruction memory, passes through the instruction cache module and the instruction cache interface in sequence, and then decodes them, and sends the decoded instructions to the in-memory computing accelerator through the instruction expansion interface. The instruction FIFO in the in-memory computing accelerator caches the instructions to achieve parallel operations with the RISC-V processor. The instruction scheduling unit in the in-memory computing accelerator allocates the instructions in the instruction FIFO to the corresponding functional modules in sequence according to the instruction functions, such as the data reordering unit (data format conversion and reordering), the vector processing unit, etc. For operation data, the high-speed bus can access the Master from the global data memory (similar to Figure 4A and Figure 4C The data is loaded from the shared memory in the local storage unit into the load storage unit, and then transferred from the load storage unit to the unified local storage unit.

[0039] In order to overcome the instruction sending efficiency problem of the bus coupling mode and to efficiently realize the flexible control of RISC-V over the in-memory computing accelerator, the embodiment of the present invention specially sets up an instruction expansion interface for sending instructions; in order to overcome the computational completeness problem of the in-memory computing accelerator, the in-memory computing array can give full play to the maximum hardware advantage when performing matrix multiplication related operations. The present invention sets up a general acceleration engine in the in-memory computing accelerator for executing operators in other formats; in order to increase the versatility of the application of the AI ​​accelerator, a vector or matrix accelerator is also set in the RISC-V processor so that it can also be applied when the neural network algorithm is updated and iterated.

[0040] The storage-computing integrated acceleration engine of the present invention is based on RISC-V extended instructions. It can flexibly control the storage-computing integrated array by expanding the instruction set. At the same time, it is easy to develop the upstream system software stack for storage-computing integrated, and integrate storage-computing integrated into the RISC-V ecosystem. It has higher versatility and flexibility, and can better adapt to a wider range of application scenarios. Due to the reduction of a large amount of power consumption and delay overhead caused by data handling, the storage-computing integrated chip architecture adopted by the present invention can achieve high-efficiency matrix multiplication, which meets the current data and computing-intensive task load requirements such as artificial intelligence, high-performance computing, and video processing, and also meets the current social demand for energy saving and consumption reduction.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An AI accelerator architecture, characterized in that: include: RISC-V processor, in-memory computing accelerator and instruction expansion interface using multiple instruction issue interface; The RISC-V processor is used to obtain and decode extended instructions for controlling the in-memory computing accelerator to perform operations; the extended instructions are pre-compiled instructions stored in the instruction memory; the RISC-V processor is configured with a data dependency detection module, which is used to detect extended instructions that can be sent simultaneously according to the data dependency, so that the detected extended instructions that can be sent simultaneously are sent through the multi-instruction sending interface; The instruction extension interface is used for the RISC-V processor to send decoded extension instructions to the in-memory computing acceleration core; the instruction extension interface is directly connected to the general register in the RISC-V processor through the register interface; The in-memory computing accelerator is used to perform corresponding operations according to the received extended instructions; the in-memory computing accelerator is configured with a general acceleration engine and a storage-computing integrated acceleration engine; The storage-computation integrated acceleration engine is used to perform matrix multiplication operations; the general acceleration engine is used to perform other neural network operators except matrix multiplication; The in-memory computing accelerator is provided with an instruction FIFO and an instruction scheduling unit for enabling the in-memory computing accelerator and the RISC-V processor to work in parallel. The instruction FIFO is used to cache extended instructions sent by the RISC-V processor through the instruction extension interface. The instruction scheduling unit is used to allocate the extended instructions cached in the instruction FIFO to corresponding functional modules in the in-memory computing accelerator according to their functions, so that the functional modules perform corresponding operations according to the received extended instructions.

2. The architecture according to claim 1, characterized in that Also includes: The shared memory configured on the bus matrix is ​​used for data exchange between the RISC-V processor and the in-memory computing accelerator; the in-memory computing accelerator is specifically used to perform matrix multiplication operations, and the vector or matrix accelerator configured in the RISC-V processor executes other neural network operators except matrix multiplication operations.

3. The architecture according to claim 1, characterized in that The RISC-V processor is configured with a vector or matrix accelerator, which is used to execute other neural network operators in the updated neural network algorithm except for matrix multiplication operations when the neural network algorithm is updated. The architecture also includes a shared memory configured on the bus matrix for data exchange between the RISC-V processor and the in-memory computing accelerator.

4. The architecture according to claim 1, characterized in that: The in-memory computing accelerator is also configured with a unified local storage unit connected to an off-chip on-chip data loading unit. The general acceleration engine and the integrated storage and computing acceleration engine interact with the unified local storage unit through a data exchange network to perform data access.

5. The architecture according to claim 1, characterized in that: The in-memory computing accelerator is also configured with a storage-computing integrated acceleration engine storage unit, a general acceleration engine storage unit and a data transfer unit; the storage-computing integrated acceleration engine storage unit and the general acceleration engine storage unit perform data exchange through the data transfer unit; the storage-computing integrated acceleration engine storage unit and the general acceleration engine storage unit are respectively connected to an off-chip on-chip data loading unit.

6. The architecture according to claim 1, characterized in that: The storage-computing integrated acceleration engine is a single-macro-unit storage-computing integrated acceleration engine or a multi-macro-unit storage-computing integrated acceleration engine. When the storage-computing integrated acceleration engine is a multi-macro-unit storage-computing integrated acceleration engine, the storage-computing integrated acceleration engine is configured with multiple storage-computing integrated macro-units, and the connection relationship of each storage-computing integrated macro-unit is adjusted through a configurable switch network.

7. An AI chip, characterized in that: Adopt the AI ​​accelerator architecture as described in any one of claims 1-6.

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