LED chip based on micro-reflector and preparation method thereof

Abstract

The present invention discloses an LED chip based on a micro-reflector and a preparation method thereof, and relates to the field of semiconductor optoelectronic devices. The preparation method of the LED chip comprises the following steps: providing an epitaxial wafer; etching the surface of the epitaxial wafer to form a plurality of protrusions; forming a dielectric layer; polishing to expose the protrusions; forming a transparent conductive layer on the protrusions and on the dielectric layer in the grooves; forming a metal reflective layer on the transparent conductive layer; forming a bonding layer on the metal reflective layer; bonding with a second substrate; removing the first substrate to expose the N-type semiconductor layer; forming an N electrode on the N-type semiconductor layer; forming a P electrode on the second substrate to obtain an LED wafer; cutting the LED wafer to obtain an LED chip based on a micro-reflector. The implementation of the present invention can improve the luminous efficiency of the LED chip.

Description

Technical Field

[0001] The invention relates to the field of semiconductor optoelectronic devices, and in particular to a LED chip based on a micro-reflector and a preparation method thereof. Background Art

[0002] At present, the internal quantum efficiency of LED chips has reached a relatively high level, but the external quantum efficiency needs to be further improved. One of the main factors affecting the external quantum extraction efficiency is the light extraction efficiency. In order to improve the light extraction efficiency, there are generally several solutions in the prior art. One is to pattern the substrate, and the other is to form a reflective layer on the substrate, such as a DBR layer, but the overall reflectivity of the DBR layer is not high. Therefore, the new technology often combines the DBR layer with the metal reflective layer to form an ODR reflective structure.

[0003] There are three common types of ODR layers in existing vertical LED chips. One is a flat dielectric layer (such as SiO2 layer, etc.) + metal reflective layer structure, but the area of ​​this flat ODR reflector is basically the same as the area of ​​the chip light-emitting area, and it is difficult to further increase the reflective area. The other is to use a buried ODR, that is, to etch away part of the active area to form a reflector with a certain angle. Although this solution effectively increases the area of ​​the ODR reflector and changes the angle of the reflector, this solution requires etching away part of the active area. On the one hand, it reduces the area of ​​the effective light-emitting area, and on the other hand, the damage caused by etching the active area may cause reliability problems such as leakage. Another solution is to form a micro-vacuum structure with hemispherical grooves to improve the light reflectivity, but this structure has a cavity of a quasi-vacuum layer inside the chip, and when the solid crystal, wire bonding, etc. are subjected to external pressure, the risk of epitaxial layer fragmentation will be greatly increased. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide an LED chip based on a micro-reflector and a preparation method thereof, which can not only effectively improve the light extraction efficiency but also do not damage the active layer and have higher reliability.

[0005] In order to solve the above technical problems, the present invention provides a method for preparing an LED chip based on a micro-reflector, which comprises the following steps:

[0006] S1. Providing an epitaxial wafer, wherein the epitaxial wafer comprises a first substrate and an N-type semiconductor layer, an MQW layer, a P-type semiconductor layer and a P-type contact layer sequentially arranged on the first substrate;

[0007] S2, etching the P-type contact layer to form a plurality of protrusions, and providing grooves between adjacent protrusions; the height of the protrusions is less than or equal to 50% of the thickness of the P-type contact layer;

[0008] S3, forming a dielectric layer on the epitaxial wafer obtained in step S2, wherein the thickness of the dielectric layer is greater than the depth of the groove, so that the dielectric layer completely covers the protrusion, and the refractive index of the dielectric layer is less than the refractive index of the P-type contact layer;

[0009] S4, polishing the epitaxial wafer obtained in step S3 to expose the protrusion and retaining a dielectric layer of a preset thickness in the groove; the preset thickness is less than or equal to the height of the protrusion;

[0010] S5, forming a transparent conductive layer on the protrusions and on the dielectric layer in the grooves;

[0011] S6, forming a metal reflective layer on the transparent conductive layer;

[0012] S7, forming a bonding layer on the metal reflective layer;

[0013] S8, bonding the epitaxial wafer obtained in step S7 to the second substrate;

[0014] S9, removing the first substrate to expose the N-type semiconductor layer;

[0015] S10, forming an N electrode on the N-type semiconductor layer;

[0016] S11, forming a P electrode on the second substrate to obtain an LED wafer;

[0017] S12, cutting the LED wafer to obtain LED chips based on micro-reflectors.

[0018] As an improvement of the above technical solution, in step S4, the epitaxial wafer obtained in step S3 is polished by a chemical mechanical polishing process, and the abrasive of the polishing liquid used in the chemical mechanical polishing is silica sol, aluminum sol and / or cerium oxide, so that the polishing speed of the P-type contact layer is lower than the polishing speed of the dielectric layer.

[0019] As an improvement of the above technical solution, in step S4, the epitaxial wafer obtained in step S3 is polished by a chemical mechanical polishing process;

[0020] Among them, the polishing pressure is 0.1kgf / cm 2 ~2.0kgf / cm 2 , the flow rate of the polishing liquid is 1mL / min~20mL / min, and the speed of the polishing disc is 20rpm~200rpm;

[0021] Wherein, the polishing liquid comprises the following components in weight percentage:

[0022] Silica sol 40%~70%, aluminum sol 20%~50%, ethylenediamine 3%~10%, fatty alcohol polyoxyethylene ether 0.2%~1%, passivator 0.1%~1%;

[0023] The concentration of silica sol is 15wt%~30wt%, and the concentration of aluminum sol is 10wt%~30wt%.

[0024] As an improvement of the above technical solution, in step S6, the metal reflective layer is an Al layer, an Au layer or an Ag layer;

[0025] In step S7, the bonding layer is an Au layer or an Ag layer;

[0026] In step S8, a Ag layer or an Au layer is provided on the surface of the second substrate; the epitaxial wafer obtained in step S7 is bonded to the second substrate by thermal compression bonding, and during bonding, the metal reflective layer and the bonding layer are pressed against each other to fill the gap on the surface of the epitaxial wafer;

[0027] Among them, the bonding temperature is 200℃~360℃, and the bonding pressure is 8000kgf~15000kgf.

[0028] As an improvement of the above technical solution, the thickness of the P-type contact layer is 1 μm to 10 μm, and its doping concentration is ≥ 1×10 19 cm -3 ; and / or

[0029] The protrusions are truncated cone, ellipsoid crown or prism shape, the height of the protrusions is 0.5 μm to 5 μm, the distance between adjacent protrusions is 0.5 μm to 10 μm, and the diameter of the circumscribed circle of the protrusions is 1 μm to 50 μm; and / or

[0030] The height of the protrusion is 20% to 35% of the thickness of the P-type contact layer; and / or

[0031] The dielectric layer is one or more of a SiO2 layer, a MgF2 layer, a TiO2 layer, and a Ti2O5 layer; the thickness of the dielectric layer is 1 μm to 5 μm; and / or

[0032] The transparent conductive layer is one or more of an ITO layer, an IZO layer, an IGZO layer, and an IGO layer; the thickness of the transparent conductive layer is 1 nm to 100 nm; and / or

[0033] The metal reflective layer is one or more of an Au layer, an Ag layer, and an Al layer, and the thickness of the metal reflective layer is 100nm-500nm.

[0034] As an improvement of the above technical solution, the thickness of the P-type contact layer is 1.5 μm to 4 μm, and its doping concentration is 3×1019 cm -3 ~5×10 20 cm -3 ; and / or

[0035] The protrusions are in the shape of ellipsoid crowns, the height of the protrusions is 0.5 μm to 1.8 μm, the distance between adjacent protrusions is 0.5 μm to 3 μm, and the diameter of the circumscribed circle of the protrusions is 1 μm to 3 μm; and / or

[0036] The dielectric layer is a SiO2 layer, and in step S2, the thickness thereof is 1.5 μm to 4 μm; and / or

[0037] The transparent conductive layer is an ITO layer, and its thickness is 3nm-20nm; and / or

[0038] The metal reflective layer is an Au layer, and its thickness is 100nm-400nm.

[0039] As an improvement of the above technical solution, a distribution area of ​​the protrusions is staggered from a distribution area of ​​the N-electrode.

[0040] As an improvement of the above technical solution, the epitaxial wafer includes a first substrate, an N-type GaAs buffer layer, an N-type GaInP etching stop layer, an N-type semiconductor layer, an MQW layer, a P-type semiconductor layer and a P-type contact layer sequentially arranged on the first substrate;

[0041] The first substrate is a GaAs substrate;

[0042] The second substrate is a P-type silicon wafer;

[0043] The N-type semiconductor layer includes an N-type GaAs ohmic contact layer, an N-type AlGaInP roughening layer, an N-type AlGaInP current spreading layer and an N-type AlGaInP limiting layer, which are arranged on the N-type GaInP etching stop layer in sequence;

[0044] The P-type semiconductor layer is a P-type AlGaInP confinement layer;

[0045] The P-type contact layer is a P-type GaP window layer.

[0046] As an improvement of the above technical solution, in step S9, the first substrate and the N-type GaInP etching stop layer are removed to expose the N-type GaAs ohmic contact layer, and the N-type GaAs ohmic contact layer is etched to form a contact pattern;

[0047] In step S10, an N electrode is formed on the contact pattern, the N-type AlGaInP roughening layer is roughened, a passivation protection layer is deposited, and the N electrode is exposed by etching;

[0048] In step S11, the second substrate is ground and thinned, and a P electrode is formed on the second substrate.

[0049] Correspondingly, the present invention further discloses a micro-reflector-based LED chip, which is prepared by the above-mentioned method for preparing a micro-reflector-based LED chip.

[0050] The implementation of the present invention has the following beneficial effects:

[0051] 1. In the preparation method of the LED chip based on micro-reflectors of the present invention, a process of etching a P-type contact layer to form a protrusion - forming a dielectric layer - polishing the dielectric layer and / or protrusion - forming a transparent conductive layer - forming a metal reflective layer is used to form a micro-reflector. Based on this process: First, by controlling the height of the protrusion to be less than or equal to 50% of the thickness of the P-type contact layer, it is avoided that the MQW active area is damaged by etching too deep, and the effective light-emitting area is not lost. Second, etching thins the P-type contact layer and reduces the light absorption of the P-type contact layer. Third, by controlling the thickness of the dielectric layer in the groove after polishing to be less than or equal to the height of the protrusion, the P-type contact layer is exposed to a certain area, and then supplemented with a transparent conductive layer, the P-type contact layer maintains a good ohmic contact with the P electrode, and does not affect the current expansion function of the P-type contact layer. Fourth, by controlling the refractive index of the dielectric layer to be less than the refractive index of the P-type contact layer, and the composite metal reflective layer, a micro-reflector structure is formed, which greatly increases the reflection area of ​​the micro-reflector, changes the reflection angle, improves the light reflectivity, and thus improves the light extraction efficiency. Fifth, the layers are tightly combined without gaps, which prevents the LED chip from being damaged during the subsequent crystal bonding and wire bonding, thereby improving reliability.

[0052] 2. In the preparation method of the LED chip based on the micro-reflector of the present invention, the epitaxial wafer obtained in step S3 is polished by chemical mechanical polishing process, and the polishing speed of the P-type contact layer is lower than the polishing speed of the dielectric layer by coordinated control of the polishing liquid formula and polishing parameters. Thus, the protrusion is polished while removing part of the dielectric layer in the groove, maintaining the light-emitting surface area of ​​the protrusion, further improving the light extraction efficiency, and the polishing process is simple and low-cost.

[0053] 3. In the method for preparing LED chips based on micro-reflectors of the present invention, the shape of the protrusions is controlled to be an ellipsoid crown, a truncated cone, or a prism, so that the top is small, the bottom is large, and the protrusions have an inclined surface, which can effectively increase the reflection area and change the reflection angle.

[0054] 4. In the preparation method of the micro-reflector-based LED chip of the present invention, by controlling the materials of the metal reflective layer and the bonding layer and selecting a hot-pressing bonding process, during the bonding process, the ductile metal is squeezed to fill the pits without leaving any gaps, that is, there is no cavity inside the chip. During the processes of crystal solidification and wire bonding, the risk of the epitaxial layer being broken due to pressure can be greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 is a schematic structural diagram of an epitaxial wafer in one embodiment of the present invention;

[0056] Figure 2 is a schematic diagram of the structure of the epitaxial wafer after step S2 in one embodiment of the present invention;

[0057] Figure 3 is a schematic diagram of the structure of the epitaxial wafer after step S3 in one embodiment of the present invention;

[0058] Figure 4 is a schematic diagram of the structure of the epitaxial wafer after step S4 in one embodiment of the present invention;

[0059] Figure 5 is a schematic diagram of the structure of the epitaxial wafer after step S5 in one embodiment of the present invention;

[0060] Figure 6 is a schematic diagram of the structure of the epitaxial wafer after step S6 in one embodiment of the present invention;

[0061] Figure 7 is a schematic diagram of the structure of the epitaxial wafer after step S8 in one embodiment of the present invention;

[0062] Figure 8 is a schematic diagram of the structure of the LED chip after step S12 in one embodiment of the present invention;

[0063] Fig. 9 is a schematic diagram of a top view of a LED chip based on a micro-reflector in one embodiment of the present invention;

[0064] In the figure, 1 is an epitaxial wafer, 11 is a first substrate, 12 is an N-type semiconductor layer, 121 is an N-type GaAs ohmic contact layer, 122 is an N-type AlGaInP roughening layer, 123 is an N-type AlGaInP current spreading layer, 124 is an N-type AlGaInP limiting layer, 13 is an MQW layer, 14 is a P-type semiconductor layer, 15 is a P-type contact layer, 151 is a protrusion, 152 is a groove, 16 is an N-type GaAs buffer layer, 17 is an N-type GaInP corrosion stop layer, 2 is a dielectric layer, 3 is a transparent conductive layer, 4 is a metal reflective layer, 5 is a bonding layer, 6 is a second substrate, 7 is an N-electrode, 8 is a P-electrode, and 9 is a passivation protection layer. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is described in further detail below.

[0066] The present invention provides a method for preparing an LED chip based on a micro-reflector, which comprises the following steps:

[0067] S1. Provide epitaxial wafers;

[0068] Ginseng Figure 1 , the epitaxial wafer 1 includes a first substrate 11, and an N-type semiconductor layer 12, an MQW layer 13, a P-type semiconductor layer 14 and a P-type contact layer 15 sequentially arranged on the first substrate 11. Specifically, the LED chip of the present invention may be a red, green, yellow or purple LED chip, and different types of semiconductor layers, MQW layers and contact layers may be selected based on the control of the emission wavelength. Exemplarily, in one embodiment, when the LED chip is a blue LED chip or a green LED chip, the N-type semiconductor layer 12 may be an N-type GaN layer, the MQW layer 13 may be an InGaN-GaN type multi-quantum well layer, the P-type semiconductor layer 14 may be a P-type GaN layer, and the P-type contact layer 15 may be a P-type InGaN layer or a highly doped P-type GaN layer, but is not limited thereto. In another embodiment, when the LED chip is a purple LED chip, the N-type semiconductor layer 12 may be an N-type AlGaN layer, the MQW layer 13 may be an AlGaN-AlGaN type multi-quantum well layer, the P-type semiconductor layer 14 may be a P-type AlGaN layer, and the P-type contact layer 15 may be a P-type GaN layer, but is not limited thereto.

[0069] Preferably, in one embodiment, the LED chip is a red LED chip, and the epitaxial wafer 1 includes an N-type GaAs buffer layer 16, an N-type GaInP etching stop layer 17, an N-type semiconductor layer 12, an MQW layer 13, a P-type semiconductor layer 14 and a P-type contact layer 15 sequentially arranged on a first substrate 11. The first substrate 11 is a GaAs substrate. The N-type semiconductor layer 12 includes an N-type GaAs ohmic contact layer 121, an N-type AlGaInP roughening layer 122, an N-type AlGaInP current spreading layer 123 and an N-type AlGaInP limiting layer 124 sequentially arranged on the N-type GaInP etching stop layer 17; the P-type semiconductor layer 14 is a P-type AlGaInP limiting layer; and the P-type contact layer 15 is a P-type GaP window layer. The following steps are described with reference to a red LED chip, but the technical solution of the present invention is not limited to the red LED chip described herein.

[0070] Specifically, the thickness of the P-type contact layer 15 is 1 μm to 10 μm. If the thickness is too small, the MQW layer 13 is easily damaged when etching to form the protrusion 151, thereby reducing the luminous efficiency. At the same time, it will also affect the current expansion function of the P-type contact layer 15. In addition, the protrusion 151 formed is small in thickness and curvature, and the effect of improving the light extraction efficiency is weak. If the thickness is greater than 10 μm, too much light is absorbed, reducing the light extraction efficiency. Preferably, the thickness of the P-type contact layer 15 is 1 μm to 5 μm, and more preferably 1.5 μm to 4 μm.

[0071] Specifically, the P-type doping concentration of the P-type contact layer 15 is ≥ 1×10 19 cm -3 , so as to form a good ohmic contact with the transparent conductive layer 3 deposited later. Preferably, the P-type doping concentration of the P-type contact layer 15 is 3×10 19 cm -3 ~5×10 20 cm -3 More preferably, the doping concentration of the P-type contact layer 15 away from the P-type semiconductor layer 14 is greater than the doping concentration close to the P-type semiconductor layer 14, which can retain a portion of the high-doping layer on the surface of the P-type contact layer 15 after subsequent etching to form a good ohmic contact with the transparent conductive layer 3, and the lower doping concentration at the bottom can reduce defects and reduce light absorption, and can also reduce the adverse effects of leakage channels formed by etching.

[0072] S2: etching the P-type contact layer to form a plurality of protrusions;

[0073] Among them, reference Figure 2 The protrusion 151 is small at the top and large at the bottom, and its side has an inclined surface, a curved surface or a spherical surface, which can effectively increase the reflection area, change the reflection angle, and improve the light extraction efficiency. Preferably, the protrusion 151 is in the shape of a truncated cone, an ellipsoid crown or a prism, but is not limited thereto. More preferably, it is in the shape of an ellipsoid crown.

[0074] Specifically, the height of the protrusion 151 is less than or equal to 50% of the thickness of the P-type contact layer 15 to prevent the MQW layer 13 from being damaged by excessive etching, without losing the effective light-emitting area, and without affecting the current expansion function of the P-type contact layer 15. Preferably, the height of the protrusion 151 is 20% to 40% of the thickness of the P-type contact layer 15, and more preferably 20% to 35%.

[0075] Specifically, the height of the protrusion 151 is 0.5 μm to 5 μm, and the diameter of the circumscribed circle of the protrusion 151 is 1 μm to 50 μm. The protrusion 151 of this shape can better reflect light. Preferably, the height of the protrusion 151 is 0.5 μm to 1.5 μm, and the diameter of the circumscribed circle of the protrusion 151 is 1 μm to 3 μm.

[0076] Among them, the protrusions 151 are arranged in an array, preferably, see Fig. 9 In one embodiment, its distribution area is staggered with the distribution area of ​​the N-electrode 7, which can further reduce the blocking of light by the N-electrode 7 and improve the luminous efficiency.

[0077] Specifically, the distance between adjacent protrusions 151 is 0.5 μm to 10 μm. If the distance is too small, the ohmic contact function of the P-type contact layer 15 is affected. If the distance is too large, less light is reflected, and the effect of improving light extraction efficiency is limited. Preferably, the distance between adjacent protrusions 151 is 0.5 μm to 4 μm, and more preferably 0.5 μm to 3 μm. A groove 152 is provided between adjacent protrusions 151.

[0078] Specifically, the P-type contact layer 15 can be etched by dry etching or wet etching, but is not limited thereto. Preferably, the P-type contact layer 15 is etched by dry etching, which has high etching accuracy and can better control the distribution and shape of the protrusions 151.

[0079] S3: forming a dielectric layer on the epitaxial wafer obtained in step S2;

[0080] The refractive index of the dielectric layer 2 is less than that of the P-type contact layer 15, so as to be combined with the protrusion 151 to improve the reflectivity of light. Specifically, the dielectric layer 2 is one or more of a SiO2 layer, a MgF2 layer, a TiO2 layer, and a Ti2O5 layer, but is not limited thereto. The above-mentioned dielectric layer 2 can not only improve the reflectivity of light, but also effectively passivate the damage formed by etching to avoid leakage. More preferably, the dielectric layer 2 is a SiO2 layer.

[0081] Among them, see Figure 3 The thickness of the dielectric layer 2 is greater than the depth of the groove 152, so that the dielectric layer 2 completely covers the protrusion 151. Preferably, the thickness of the dielectric layer 2 is 1 μm to 5 μm, preferably 1 μm to 4 μm, and more preferably 1.5 μm to 4 μm.

[0082] S4: polishing the epitaxial wafer obtained in step S3 to expose the protrusions and retaining a dielectric layer of a preset thickness in the grooves;

[0083] The epitaxial wafer may be polished by an ion beam polishing process, a magnetorheological polishing process or a chemical mechanical polishing process, but is not limited thereto. By polishing, not only the dielectric layer 2 on the surface of the protrusion 151 is removed to expose the protrusion 151, but also the roughness of the surface of the protrusion 151 is reduced, further improving the light extraction efficiency.

[0084] Specifically, after polishing, the thickness of the dielectric layer 2 is less than or equal to the height of the protrusion 151. Preferably, in one embodiment of the present invention, see Figure 4After polishing, the thickness of the dielectric layer 2 is less than the height of the protrusion 151. Based on this shape, the optical path can be better controlled and the light extraction efficiency can be improved. Specifically, 3% to 10% of the dielectric layer 2 in the depth of the groove 152 is removed by polishing. If too much is removed, the top morphology of the protrusion 151 will be destroyed. If too little is removed, the ohmic contact performance with the P electrode 8 is poor and the working voltage is large.

[0085] Preferably, in one embodiment of the present invention, the epitaxial wafer is polished by a chemical mechanical polishing process, and the abrasive of the polishing liquid used during polishing is silica sol, aluminum sol and / or nano-cerium oxide. When the above abrasive is used, the polishing speed of the P-type contact layer 15 is lower than the polishing speed of the dielectric layer 2, thereby achieving the purpose of removing part of the dielectric layer 2 and polishing the protrusion 151. More preferably, the purpose of removing the dielectric layer 2 of a preset thickness in the groove 152 and effectively polishing the protrusion 151 is achieved.

[0086] More preferably, when the chemical mechanical polishing process is used, the polishing pressure is 0.1 kgf / cm 2 ~2.0kgf / cm 2 , the flow rate of the polishing liquid is 1mL / min~20mL / min, and the speed of the polishing disc is 20rpm~200rpm; the polishing liquid used for polishing includes the following components in weight percentage:

[0087] Silica sol 40%~70%, aluminum sol 20%~50%, ethylenediamine 3%~10%, fatty alcohol polyoxyethylene ether 0.2%~1%, passivator 0.1%~1%; wherein, the concentration of silica sol is 15wt%~30wt%, and the concentration of aluminum sol is 10wt%~30wt%.

[0088] Based on the polishing liquid with specific components and polishing parameters, the dielectric layer 2 can be quickly removed, the protrusion 151 can be exposed, and the protrusion 151 can be polished. Furthermore, through this process, in the process of removing the dielectric layer 2 with a preset thickness in the groove 152, the structure of the protrusion 151 will not be damaged, and its larger side light emitting surface is maintained, thereby improving the light extraction efficiency.

[0089] S5: forming a transparent conductive layer on the protrusions and on the dielectric layer in the grooves;

[0090] It should be noted that etching the P-type ohmic contact layer 15 to form a protrusion 151 to form a microlens structure will improve the light extraction efficiency. However, it also leads to a weakening of the ohmic contact between the P-type ohmic contact layer 15 and the P electrode 8 to a certain extent. Therefore, the present invention removes part of the dielectric layer 2 in the groove 152 by polishing to increase the ohmic contact area of ​​the protrusion 151. The two form a transparent conductive layer 3 to further improve the ohmic contact.

[0091] For details, see Figure 5 The transparent conductive layer 3 is one or more of an ITO layer, an IZO layer, an IGZO layer, and an IGO layer, but is not limited thereto. Preferably, it is an ITO layer. The thickness of the transparent conductive layer 3 is 1 nm to 200 nm, preferably 1 nm to 100 nm, and more preferably 3 nm to 20 nm.

[0092] S6: forming a metal reflective layer on the transparent conductive layer;

[0093] Among them, see Figure 6 The metal reflective layer 4 is one or more of an Au layer, an Ag layer, and an Al layer, but is not limited thereto. The Au layer is preferred, which has better adhesion and a reflectivity close to that of Ag, and can form a good ohmic contact with the transparent conductive layer 3 and the protrusion 151. At the same time, the reflectivity of the Au layer decreases the least after being subjected to high temperature.

[0094] Specifically, the thickness of the metal reflective layer 4 is 100nm-500nm. When the thickness is too small, the reflectivity of light is small. When the thickness exceeds a certain limit, the reflectivity of light is no longer improved. Preferably, the thickness of the metal reflective layer 4 is 100nm-400nm.

[0095] S7: forming a bonding layer on the metal reflective layer;

[0096] Among them, according to different later bonding processes, a bonding layer 5 of different materials can be formed on the metal reflective layer 4. For example, when a eutectic bonding process is adopted, an Au layer, a Cu layer, an In layer, a Pb layer or a Sn layer can be used, but it is not limited to this. For another example, when a hot pressing bonding process is adopted, an Au layer, a Cu layer, an Ag layer, or an Al layer can be used as the bonding layer 5, but it is not limited to this. It should be noted that in this embodiment, in order to ensure that the P electrode 8 forms a good ohmic contact with the P-type contact layer 15, the bonding layer 5 is made of a conductive material.

[0097] Preferably, in one embodiment, a hot compression bonding process is adopted for bonding, that is, the bonding layer 5 is selected from an Au layer or an Ag layer. The bonding layer 5 can assist the metal reflective layer 4 to improve the reflectivity of light; secondly, low-temperature hot compression bonding can be adopted. During hot compression bonding, the metal reflective layer 4 and the bonding layer 5 have ductility under the combined action of temperature and pressure, so that the metal is squeezed to fill the gaps on the surface of the epitaxial wafer, that is, the resulting chip has no cavity and can withstand higher pressure without breaking in the later process of crystal solidification and wire bonding, thereby greatly improving the yield rate.

[0098] The thickness of the bonding layer 5 is 300 nm to 800 nm, preferably 300 nm to 500 nm.

[0099] S8: bonding the epitaxial wafer obtained in step S7 to the second substrate;

[0100] Specifically, the epitaxial wafer and the second substrate 6 may be bonded by eutectic bonding, thermal compression bonding, etc., but are not limited thereto. Preferably, thermal compression bonding is used. The bonding temperature is 200°C to 360°C, and the bonding pressure is 8000kgf to 15000kgf. The epitaxial wafer structure obtained after bonding is as follows: Figure 7 shown.

[0101] Specifically, when the thermal compression bonding process is adopted, an Ag layer or an Au layer is disposed on the surface of the second substrate 6 to complete the bonding.

[0102] The second substrate 6 is a common conductive substrate in the art, exemplarily a P-type single crystal silicon substrate.

[0103] S9: removing the first substrate to expose the N-type semiconductor layer;

[0104] Specifically, the first substrate may be removed by an alkali polishing process or a laser lift-off process, but is not limited thereto. Preferably, the first substrate is removed by a laser lift-off process.

[0105] In the process of removing the first substrate, the buffer layer, intrinsic GaN layer, etc. disposed on the surface are also removed. In one embodiment of the present invention, when the LED is a red LED chip, the first substrate (GaAs substrate), N-type GaAs buffer layer 16 and N-type GaInP etching stop layer 17 are removed.

[0106] S10: forming an N electrode on the N-type semiconductor layer;

[0107] The N electrode 7 may be formed by evaporation, sputtering or other processes, and the N electrode 7 may be one or more of a Cr layer, an Al layer, a Pt layer, an Au layer or the like commonly used in the art, but is not limited thereto.

[0108] Preferably, when the LED is a red LED chip, the N-type GaAs ohmic contact layer is first patterned by a photolithography and etching process, and then the N electrode 7 is formed, and then a passivation protection layer 9 is formed on the surface of the obtained epitaxial wafer.

[0109] S11: forming a P electrode on the second substrate to obtain an LED wafer;

[0110] The P electrode 8 may be formed by evaporation, sputtering or other processes, and the P electrode 8 may be one or more of the Cr layer, Al layer, Pt layer, Au layer, etc. commonly used in the art, but is not limited thereto.

[0111] Preferably, in one embodiment, the second substrate 6 is first ground and thinned, and then the P electrode 8 is formed.

[0112] S12: Cut the LED wafer to obtain LED chips based on micro-reflectors

[0113] Specifically, after the processes of cutting, back cutting and splitting, the LED wafer is cut into separate LED chips, the structure of which is as follows: Figure 8 shown.

[0114] The above is a preferred embodiment of the invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the invention. These improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A method for preparing a LED chip based on a micro-reflector, characterized in that: The following steps are involved: S1. Providing an epitaxial wafer, wherein the epitaxial wafer comprises a first substrate and an N-type semiconductor layer, an MQW layer, a P-type semiconductor layer and a P-type contact layer sequentially arranged on the first substrate; S2, etching the P-type contact layer to form a plurality of protrusions, and providing grooves between adjacent protrusions; the height of the protrusions is less than or equal to 50% of the thickness of the P-type contact layer; S3, forming a dielectric layer on the epitaxial wafer obtained in step S2, wherein the thickness of the dielectric layer is greater than the depth of the groove, so that the dielectric layer completely covers the protrusion, and the refractive index of the dielectric layer is less than the refractive index of the P-type contact layer; S4, polishing the epitaxial wafer obtained in step S3 to expose the protrusion and retaining a dielectric layer of a preset thickness in the groove; the preset thickness is less than or equal to the height of the protrusion; S5, forming a transparent conductive layer on the protrusions and on the dielectric layer in the grooves; S6, forming a metal reflective layer on the transparent conductive layer; S7, forming a bonding layer on the metal reflective layer; S8, bonding the epitaxial wafer obtained in step S7 to the second substrate; S9, removing the first substrate to expose the N-type semiconductor layer; S10, forming an N electrode on the N-type semiconductor layer; S11, forming a P electrode on the second substrate to obtain an LED wafer; S12, cutting the LED wafer to obtain LED chips based on micro-reflectors; Wherein, in step S4, the epitaxial wafer obtained in step S3 is polished by a chemical mechanical polishing process; the polishing speed of the P-type contact layer is lower than the polishing speed of the dielectric layer; Among them, the polishing pressure is 0.1kgf / cm 2 ~2.0kgf / cm 2 , the flow rate of the polishing liquid is 1mL / min~20mL / min, and the speed of the polishing disc is 20rpm~200rpm; Wherein, the polishing liquid comprises the following components in weight percentage: Silica sol 40%~70%, aluminum sol 20%~50%, ethylenediamine 3%~10%, fatty alcohol polyoxyethylene ether 0.2%~1%, passivator 0.1%~1%; The concentration of silica sol is 15wt%~30wt%, and the concentration of aluminum sol is 10wt%~30wt%.

2. The method for preparing a LED chip based on a micro-reflector according to claim 1, characterized in that: In step S4, 3% to 10% of the dielectric layer in the groove depth is removed by polishing.

3. The method for preparing a LED chip based on a micro-reflector according to claim 1, characterized in that: In step S6, the metal reflective layer is an Al layer, an Au layer or an Ag layer; In step S7, the bonding layer is an Au layer or an Ag layer; In step S8, a Ag layer or an Au layer is provided on the surface of the second substrate; the epitaxial wafer obtained in step S7 is bonded to the second substrate by thermal compression bonding, and during bonding, the metal reflective layer and the bonding layer are pressed against each other to fill the gap on the surface of the epitaxial wafer; Among them, the bonding temperature is 200℃~360℃, and the bonding pressure is 8000kgf~15000kgf.

4. The method for preparing a LED chip based on a micro-reflector according to claim 1, characterized in that: The thickness of the P-type contact layer is 1 μm to 10 μm, and its doping concentration is ≥ 1×10 19 cm -3 ; and / or The protrusions are truncated cone, ellipsoid crown or prism shape, the height of the protrusions is 0.5 μm to 5 μm, the distance between adjacent protrusions is 0.5 μm to 10 μm, and the diameter of the circumscribed circle of the protrusions is 1 μm to 50 μm; and / or The height of the protrusion is 20% to 35% of the thickness of the P-type contact layer; and / or The dielectric layer is one or more of a SiO2 layer, a MgF2 layer, a TiO2 layer, and a Ti2O5 layer; the thickness of the dielectric layer is 1 μm to 5 μm; and / or The transparent conductive layer is one or more of an ITO layer, an IZO layer, an IGZO layer, and an IGO layer; the thickness of the transparent conductive layer is 1 nm to 100 nm; and / or The metal reflective layer is one or more of an Au layer, an Ag layer, and an Al layer, and the thickness of the metal reflective layer is 100nm-500nm.

5. The method for preparing a LED chip based on a micro-reflector according to claim 1 or 4, characterized in that: The thickness of the P-type contact layer is 1.5 μm to 4 μm, and the doping concentration is 3×10 19 cm -3 ~5×10 20 cm -3 ; and / or The protrusions are in the shape of ellipsoid crowns, the height of the protrusions is 0.5 μm to 1.8 μm, the distance between adjacent protrusions is 0.5 μm to 3 μm, and the diameter of the circumscribed circle of the protrusions is 1 μm to 3 μm; and / or The dielectric layer is a SiO2 layer, and in step S2, the thickness thereof is 1.5 μm to 4 μm; and / or The transparent conductive layer is an ITO layer, and its thickness is 3nm-20nm; and / or The metal reflective layer is an Au layer, and its thickness is 100nm-400nm.

6. The method for preparing a LED chip based on a micro-reflector according to claim 1, characterized in that: The distribution area of ​​the protrusions is staggered from the distribution area of ​​the N-electrode.

7. The method for preparing a LED chip based on a micro-reflector according to claim 1, characterized in that: The epitaxial wafer comprises a first substrate, an N-type GaAs buffer layer, an N-type GaInP etching stop layer, an N-type semiconductor layer, an MQW layer, a P-type semiconductor layer and a P-type contact layer which are sequentially arranged on the first substrate; The first substrate is a GaAs substrate; The second substrate is a P-type silicon wafer; The N-type semiconductor layer includes an N-type GaAs ohmic contact layer, an N-type AlGaInP roughening layer, an N-type AlGaInP current spreading layer and an N-type AlGaInP limiting layer, which are arranged on the N-type GaInP etching stop layer in sequence; The P-type semiconductor layer is a P-type AlGaInP confinement layer; The P-type contact layer is a P-type GaP window layer.

8. The method for preparing a LED chip based on a micro-reflector according to claim 7, characterized in that: In step S9, the first substrate and the N-type GaInP etching stop layer are removed to expose the N-type GaAs ohmic contact layer, and the N-type GaAs ohmic contact layer is etched to form a contact pattern; In step S10, an N electrode is formed on the contact pattern, the N-type AlGaInP roughening layer is roughened, a passivation protection layer is deposited, and the N electrode is exposed by etching; In step S11, the second substrate is ground and thinned, and a P electrode is formed on the second substrate.

9. A LED chip based on a micro-reflector, characterized in that: The LED chip is prepared by the method for preparing a micro-reflector-based LED chip as described in any one of claims 1 to 8.

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