A chip preparation method

Abstract

The present invention discloses a chip preparation method, which relates to the semiconductor field. The chip preparation method comprises: obtaining a flatness map of a wafer; forming a composite material layer on the back of the wafer; and imprinting a side of the composite material layer away from the wafer according to the flatness map to eliminate the stress of the wafer. The chip preparation method provided by the present invention can completely eliminate the stress of the wafer and improve the chip quality and yield rate.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a chip preparation method. Background Art

[0002] After the wafer is formed through multiple processes, it often has poor flatness due to stress accumulation, including flatness changes and warping. In order to reduce the adverse effects of wafer flatness on the chip preparation process, the market generally uses a method of pasting a stress layer on the back of the wafer during chip preparation to correct the wafer warping, thereby eliminating the warping stress.

[0003] Due to the structural integrity of the stress layer, the flatness of the wafer cannot be corrected after it is pasted on the back of the wafer, that is, the flatness stress cannot be eliminated. The front of the wafer is still uneven, which will still have an adverse effect on the process effects such as lithography accuracy in the chip preparation process, and there is also a high risk of cracking. Summary of the invention

[0004] The object of the present invention is to provide a chip preparation method, which can completely eliminate wafer stress and improve chip quality and yield.

[0005] The embodiment of the present invention provides a technical solution:

[0006] A chip preparation method, comprising:

[0007] Obtaining a wafer flatness map;

[0008] forming a composite material layer on the back side of the wafer;

[0009] A side of the composite material layer facing away from the wafer is imprinted according to the planarity map.

[0010] In an optional embodiment, before the step of imprinting the side of the composite material layer facing away from the wafer according to the flatness mapping, the chip preparation method further includes:

[0011] Dividing the wafer surface into a plurality of correction units;

[0012] Obtaining the correction stress required by each correction unit according to the flatness mapping;

[0013] The thickness of the composite material layer is adjusted according to the modified stress and the thickness-stress relationship curve of the composite material layer.

[0014] In an optional embodiment, before the step of imprinting the side of the composite material layer facing away from the wafer according to the flatness mapping, the chip preparation method further includes:

[0015] An imprinting mold is prepared according to the planarity map.

[0016] In an optional embodiment, the step of preparing an imprint mold according to the flatness mapping comprises:

[0017] Dividing the wafer surface into a plurality of correction units;

[0018] Obtaining the correction stress required by each correction unit according to the flatness mapping;

[0019] Obtaining a target thickness of the composite material layer at each correction unit according to a plurality of correction stresses and a thickness-stress relationship curve of the composite material layer;

[0020] The imprinting mold is 3D printed according to the plurality of target thicknesses.

[0021] In an optional embodiment, the thickness-stress relationship curve of the composite material layer is obtained by experimental simulation or big data analysis.

[0022] In an optional embodiment, the step of imprinting a side of the composite material layer facing away from the wafer according to the planarity mapping comprises:

[0023] The imprinting mold is used to imprint the side of the composite material layer facing away from the wafer in accordance with the flatness map until the composite material layer at each correction unit reaches the respective target thickness.

[0024] In an optional embodiment, the step of obtaining a wafer flatness map includes:

[0025] The surface of the wafer is scanned in multiple lines by using a scanning device to obtain the flatness map.

[0026] In an optional embodiment, the step of forming a polymer material film layer on the back side of the wafer includes:

[0027] The polyimide and the carbon fiber are mixed in a predetermined ratio to obtain a composite material;

[0028] The composite material is coated on the back side of the wafer to form the composite material layer.

[0029] In an optional embodiment, before the step of imprinting the side of the composite material layer facing away from the wafer according to the flatness mapping, the chip preparation method further includes:

[0030] An imprint protection film is formed on the front side of the wafer.

[0031] In an optional embodiment, after the step of imprinting the side of the composite material layer facing away from the wafer according to the flatness mapping, the chip preparation method further includes:

[0032] growing a functional layer on the front side of the wafer;

[0033] If a photolithography and development process is required during the growth of the functional layer, a protective layer is deposited on the surface of the composite material layer in advance.

[0034] In an optional embodiment, the wafer includes an epitaxial layer, and after the step of growing a functional layer on the front side of the wafer, the chip preparation method further includes:

[0035] Removing the epitaxial layer on the wafer at the scribe line to open the scribe line;

[0036] performing annealing treatment on the wafer;

[0037] Cutting the wafer along the cutting paths to obtain chip modules;

[0038] The corresponding composite material layer on the chip module is removed to obtain a chip.

[0039] Compared with the prior art, the chip preparation method provided by the present invention, after forming a composite material layer on the back of the wafer, performs embossing on the side of the composite material layer away from the wafer according to the flatness mapping of the wafer, thereby accurately correcting the flatness of the wafer, including the overall warpage and local flatness, and improving the process effect in the subsequent growth of functional layers to prepare chips, thereby improving the chip quality. And it can completely eliminate warpage stress and flatness stress to avoid cracking during the process. Therefore, the beneficial effects of the chip preparation method provided by the present invention include: it is adaptable to the substrate warpage of the wafer, can accurately define the microstructure, and accurately adjust the warpage of the wafer; it can completely eliminate wafer stress and improve chip quality and yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative work.

[0041] Figure 1 A flowchart of a chip preparation method provided by an embodiment of the present invention;

[0042] Figure 2 for Figure 1 A sub-step flow chart of step S101;

[0043] Figure 3 for Figure 1 A sub-step flow chart of step S102;

[0044] Figure 4 for Figure 1 A sub-step flow chart of step S103;

[0045] Figure 5 for Figure 1 A sub-step flow chart of step S104 in FIG. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0047] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0049] In the description of the present invention, it should be understood that the terms "upper", "lower", "inside", "outside", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use, or are directions or positional relationships commonly understood by those skilled in the art. These directions or positional relationships are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0050] Furthermore, the terms “first”, “second”, etc. are merely used for distinguishing descriptions and should not be understood as indicating or implying relative importance.

[0051] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms such as "setting" and "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0052] The specific implementation modes of the present invention are described in detail below in conjunction with the accompanying drawings.

[0053] Example

[0054] See also Figure 1 , Figure 1 The figure shows a flow chart of a chip preparation method provided by this embodiment, and the chip preparation method can prepare chips with better quality and higher yield. Specifically, the chip preparation method may include:

[0055] Step S101, obtaining a wafer flatness map.

[0056] Please refer to Figure 2 , Figure 2 The figure shows a sub-step flow chart of step S101. Step S101 may include the following sub-steps:

[0057] Sub-step S1011, using a scanning device to perform multi-line scanning on the surface of the wafer to obtain a flatness map.

[0058] In this embodiment, the scanning device is a 3D tester, which performs four-line scanning on the surface of the wafer to obtain a flatness map.

[0059] It should be noted that the surface of the wafer in this embodiment refers to the front side of the wafer, that is, the side surface for growing the functional layer. The flatness mapping of the wafer characterizes the flatness of the wafer surface, including warpage and flatness. The flatness mapping of the wafer obtained by multi-line scanning can intuitively reflect the stress distribution on the wafer surface and accurately adjust the warpage of the wafer.

[0060] In other embodiments, various devices such as a stress measuring instrument, a white light interferometer, a laser confocal microscope, and an optical profilometer may be used to obtain the stress distribution on the wafer surface.

[0061] Please continue reading Figure 1 , the chip preparation method may further include:

[0062] Step S102 , forming a composite material layer on the back side of the wafer.

[0063] Please refer to Figure 3 , Figure 3 The figure shows a sub-step flow chart of step S102. Step S102 may include the following sub-steps:

[0064] Sub-step S1021, mixing polyimide and carbon fiber in a preset ratio to obtain a composite material.

[0065] Sub-step S1022 , coating the composite material onto the back side of the wafer to form a composite material layer.

[0066] A composite material of a certain thickness is coated on the back side of the wafer, and the coating thickness is within a thickness range corresponding to an average stress range of the wafer. Preferably, a spin coating method is used in this embodiment.

[0067] The polyimide in the composite material can withstand temperatures up to 600°C and has extremely high thermal stability. The elastic modulus of polyimide is usually 3 GPa to 4 GPa, and the mechanical strength is usually 100 MPa to 400 MPa.

[0068] Carbon fiber can reinforce polyimide while increasing the thermal expansion coefficient of the composite material. The elastic modulus of carbon fiber can reach between 200 GPa and 800 GPa, and the mechanical strength is usually between 2 GPa and 4.5 GPa.

[0069] The elastic modulus of composite materials composed of polyimide and carbon fiber is between 50 GPa and 300 GPa, and the mechanical strength can usually reach between 500 MPa and 1.5 GPa, depending on the carbon fiber content.

[0070] Please continue reading Figure 1 , the chip preparation method may further include:

[0071] Step S103, preparing an imprinting mold according to the flatness mapping.

[0072] Please refer to Figure 4 , Figure 4 The figure shows a sub-step flow chart of step S103. Step S103 may include the following sub-steps:

[0073] Sub-step S1031, dividing the wafer surface into a plurality of correction units.

[0074] Sub-step S1032, obtaining the correction stress required for each correction unit according to the flatness mapping.

[0075] The infinite element analysis method is used to divide the front side of the wafer into multiple correction units. The correction stress required for each correction unit to correct the flatness is analyzed by comparing the flatness mapping, and multiple correction stresses are obtained.

[0076] Sub-step S1033, obtaining a target thickness of the composite material layer at each correction unit according to the plurality of correction stresses and the thickness-stress relationship curve of the composite material layer.

[0077] In fact, before sub-step S1033, it also includes a sub-step of obtaining a thickness-stress relationship curve of the composite material layer by using experimental simulation or big data analysis methods. The thickness-stress relationship curve of the composite material layer is a relationship curve between the thickness of the composite material layer and the stress of the composite material layer.

[0078] It is understandable that changes in the content of carbon fiber in the composite material will significantly affect the thickness-stress relationship of the composite material layer. Therefore, when obtaining the thickness-stress relationship curve of the composite material layer, it is also necessary to perform experimental simulation or big data analysis based on the standard of mixing polyimide and carbon fiber in a preset ratio.

[0079] Sub-step S1034, 3D printing an imprinting mold according to multiple target thicknesses.

[0080] The flatness of the wafer can be determined based on the flatness mapping. As a parameter of the 3D printing imprint mold, the concave-convex conditions, shapes, sizes, etc. of multiple positions on the printing mold corresponding to multiple correction units can be determined.

[0081] Furthermore, the height differences of multiple positions corresponding to multiple correction units on the printing mold can be determined according to multiple target thicknesses, which are also used as parameters of the 3D printing imprint mold, ensuring that under the imprinting of the same imprint mold, the composite material layers at each correction unit can simultaneously reach their respective target thicknesses to meet the correction stress requirements of each correction unit.

[0082] Please continue reading Figure 1 , the chip preparation method may further include:

[0083] Step S104 , imprinting the composite material layer on a side facing away from the wafer according to the planarity mapping to eliminate the stress of the wafer.

[0084] In another embodiment, in order to protect the front side of the wafer during the imprinting process, an imprinting protection film may be formed on the front side of the wafer before step S104. The imprinting protection film may be formed by deposition or pasting and is a flexible film layer.

[0085] Please refer to Figure 5 , Figure 5 The figure shows a sub-step flow chart of step S104. Step S104 may include the following sub-steps:

[0086] Sub-step S1041 , using an imprinting mold, imprinting the side of the composite material layer facing away from the wafer according to the flatness mapping, until the composite material layer at each correction unit reaches its respective target thickness.

[0087] In this embodiment, nanoimprinting is performed on the side of the composite material layer away from the wafer, that is, the pattern scale of the imprinting mold prepared in step S103 is nanometer-scale. It can be understood that the imprinting process is performed in a heated environment, and the composite material layer is cured when the imprinting is completed.

[0088] After the imprint mold is prepared according to the stress distribution of the wafer through step S103, the positions of the corresponding multiple correction units on the composite material layer are accurately imprinted by comparing the flatness map of the wafer, so that the composite material layers at the multiple correction units on the wafer can accurately and synchronously reach their respective target thicknesses to meet the correction stress requirements of each correction unit, so that the flatness of the wafer can be accurately corrected and the stress can be completely eliminated.

[0089] In order to ensure that the composite material layer at each correction unit can be smoothly imprinted to its respective target thickness in step S104, the thickness of the composite material layer before imprinting needs to meet the requirements. Therefore, before step S104, the chip preparation method may further include the following steps:

[0090] Dividing the wafer surface into a plurality of correction units;

[0091] According to the flatness mapping, the correction stress required for each correction unit is obtained;

[0092] The thickness of the composite material layer is adjusted according to the modified stress and the thickness-stress relationship curve of the composite material layer.

[0093] After obtaining the correction stress required for each correction unit through flatness mapping, the average stress range of the wafer can be obtained. By comparing the thickness-stress relationship curve of the composite material layer, the thickness range of the composite material layer corresponding to the average stress range can be obtained, so that the composite material layer can be adjusted to within this thickness range for subsequent imprinting.

[0094] Please continue reading Figure 1 , the chip preparation method may further include:

[0095] Step S105 , growing a functional layer on the front side of the wafer.

[0096] Step S106: if a photolithography and development process is required in the process of growing the functional layer, a protective layer is deposited on the surface of the composite material layer in advance.

[0097] It is understandable that in order to prevent the composite material layer from being corroded during the photolithography and development process, a protective layer is deposited on the surface of the composite material layer in advance, and the protective layer may be a metal layer.

[0098] In fact, the wafer includes a substrate and an epitaxial layer. After step S105, the chip preparation method may further include the following steps:

[0099] removing the epitaxial layer on the wafer at the scribe line to open the scribe line;

[0100] Annealing the wafer;

[0101] Cutting the wafer along the cutting path to obtain chip modules;

[0102] The corresponding composite material layer on the chip module is removed to obtain the chip.

[0103] After the growth of the functional layer is completed, the cutting path is opened by photolithography, and the epitaxial layer on the surface of the cutting path between different chips is removed by dry ICP and wet etching.

[0104] It is understandable that annealing the wafer can further release the stress of the wafer and prevent the wafer from cracking during the subsequent removal of the composite material layer, cutting, splitting, and sorting.

[0105] If the ICP etching cut line causes the wafer stress to be overcorrected, the stress can be eliminated again by partially thinning or partially removing the composite material layer.

[0106] In summary, the chip preparation method provided in this embodiment can completely eliminate wafer stress and improve chip quality and yield.

[0107] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A chip preparation method, characterized in that: include: Obtaining a wafer flatness map; forming a composite material layer on the back side of the wafer; imprinting a side of the composite material layer facing away from the wafer according to the planarity map; Before the step of imprinting the side of the composite material layer away from the wafer according to the flatness mapping, the chip preparation method further includes: preparing an imprinting mold according to the flatness map; The step of preparing an imprint mold according to the flatness mapping comprises: Dividing the wafer surface into a plurality of correction units; Obtaining the correction stress required by each correction unit according to the flatness mapping; Obtaining a target thickness of the composite material layer at each correction unit according to a plurality of correction stresses and a thickness-stress relationship curve of the composite material layer; The imprinting mold is 3D printed according to the plurality of target thicknesses.

2. The chip preparation method according to claim 1, characterized in that: Before imprinting the side of the composite material layer away from the wafer according to the flatness mapping, the chip preparation method further includes: Dividing the wafer surface into a plurality of correction units; Obtaining the correction stress required by each correction unit according to the flatness mapping; The thickness of the composite material layer is adjusted according to the modified stress and the thickness-stress relationship curve of the composite material layer.

3. The chip preparation method according to claim 1 or 2, characterized in that: The thickness-stress relationship curve of the composite material layer is obtained by experimental simulation or big data analysis.

4. The chip preparation method according to claim 1, characterized in that: The step of imprinting the side of the composite material layer facing away from the wafer according to the planarity mapping comprises: The imprinting mold is used to imprint the side of the composite material layer facing away from the wafer in accordance with the flatness map until the composite material layer at each correction unit reaches the respective target thickness.

5. The chip preparation method according to claim 1, characterized in that: The step of obtaining a wafer flatness map comprises: The surface of the wafer is scanned in multiple lines by using a scanning device to obtain the flatness map.

6. The chip preparation method according to claim 1, characterized in that: The step of forming a polymer material film layer on the back side of the wafer comprises: The polyimide and the carbon fiber are mixed in a predetermined ratio to obtain a composite material; The composite material is coated on the back side of the wafer to form the composite material layer.

7. The chip preparation method according to claim 1, characterized in that: Before the step of imprinting the side of the composite material layer away from the wafer according to the flatness mapping, the chip preparation method further includes: An imprint protection film is formed on the front side of the wafer.

8. The chip preparation method according to claim 1, characterized in that: After the step of imprinting the side of the composite material layer away from the wafer according to the flatness mapping, the chip preparation method further includes: growing a functional layer on the front side of the wafer; If a photolithography and development process is required during the growth of the functional layer, a protective layer is deposited on the surface of the composite material layer in advance.

9. The chip preparation method according to claim 8, characterized in that: The wafer includes an epitaxial layer, and after the step of growing a functional layer on the front side of the wafer, the chip preparation method further includes: Removing the epitaxial layer on the wafer at the scribe line to open the scribe line; performing annealing treatment on the wafer; Cutting the wafer along the cutting paths to obtain chip modules; The corresponding composite material layer on the chip module is removed to obtain a chip.

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