High-precision comparator based on folding latch

Abstract

The present invention discloses a high-precision comparator based on a folding latch, comprising a pre-amplifier and a post-folding latch connected to each other, wherein the pre-amplifier comprises an amplifier circuit and an offset calibration circuit, the amplifier circuit is used to amplify the input signal in the working phase of the comparator, the offset calibration circuit is used to store the offset voltage of the comparator in the offset calibration phase, and reduce the offset voltage of the comparator by offsetting in the working phase of the comparator, the working phase of the comparator is alternately performed with the offset calibration phase; the post-folding latch is used to identify the amplified signal and reconstruct it into a logic high level and a logic low level. The comparator of the present invention has a stronger ability to resist noise interference, lower power consumption, and a faster working speed of the latch; and has the performance characteristics of high precision, low power consumption and fast response speed.

Description

Technical Field

[0001] The invention belongs to the technical field of mixed signal integrated circuits, and in particular relates to a high-precision comparator based on a folding latch. Background Art

[0002] High-precision analog-to-digital converters are an indispensable core component in modern electronic systems. They are widely used in electronic measurement, communication equipment, medical equipment, automotive electronics, industrial automation, seismic surveys, aerospace and other fields. They can accurately convert analog signals into digital signals, so that the equipment in these fields can process and control data more accurately, meeting various application needs from scientific research to daily life. The accuracy of the analog-to-digital converter is determined by the comparator. In recent years, the technological development of comparators has focused on improving speed, reducing power consumption, increasing accuracy and integration. Comparators have made significant progress in high-speed performance, low power consumption and high precision, and have also become more compact and have stronger anti-interference capabilities.

[0003] However, there are still some problems with high-precision comparators in terms of accuracy, power consumption, response speed, etc. Traditional static comparators can achieve higher accuracy requirements, but there is static power consumption, and the overall power consumption of the comparator is relatively large; traditional dynamic comparators have a comparator dormant state, and the overall power consumption is relatively small, but because dynamic comparators are greatly affected by noise, the accuracy of the comparator will be affected. Meeting the requirements of power consumption and accuracy at the same time is a problem that high-precision comparators need to overcome. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a high-precision comparator based on a folding latch. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The present invention provides a high-precision comparator based on a folding latch, comprising a front-stage amplifier and a rear-stage folding latch connected to each other, wherein:

[0006] The preamplifier comprises an amplifier circuit and an offset calibration circuit, wherein the amplifier circuit is used to amplify the input signal in the comparator working stage, and the offset calibration circuit is used to store the offset voltage of the comparator in the offset calibration stage and reduce the offset voltage of the comparator by offsetting in the comparator working stage, wherein the comparator working stage and the offset calibration stage are performed alternately;

[0007] The post-stage folding latch is used to identify the amplified signal and reconstruct it into a logic high level and a logic low level.

[0008] In one embodiment of the present invention, the amplifier circuit includes a first-stage operational amplifier unit OP1, a second-stage operational amplifier unit OP2, a third-stage operational amplifier unit OP3 and a fourth-stage operational amplifier unit OP4, and the offset calibration circuit includes a calibration capacitor C1, a calibration capacitor C2, a calibration capacitor C3, a calibration capacitor C4, a calibration capacitor C5, a calibration capacitor C6, a calibration switch S1, a calibration switch S2, a calibration switch S3 and a calibration switch S4, wherein,

[0009] The calibration switch S1 is connected between the positive input terminal and the negative input terminal of the first-stage operational amplifier unit OP1, the calibration capacitor C1 is connected between the positive output terminal of the first-stage operational amplifier unit OP1 and the positive input terminal of the second-stage operational amplifier unit OP2, the calibration capacitor C4 is connected between the negative output terminal of the first-stage operational amplifier unit OP1 and the negative input terminal of the second-stage operational amplifier unit OP2, and the calibration switch S2 is connected between the positive input terminal and the negative input terminal of the second-stage operational amplifier unit OP2;

[0010] The calibration capacitor C2 is connected between the positive output terminal of the second-stage operational amplifier unit OP2 and the positive input terminal of the third-stage operational amplifier unit OP3, the calibration capacitor C5 is connected between the negative output terminal of the second-stage operational amplifier unit OP2 and the negative input terminal of the third-stage operational amplifier unit OP3, and the calibration switch S3 is connected between the positive input terminal and the negative input terminal of the third-stage operational amplifier unit OP3;

[0011] The calibration capacitor C3 is connected between the positive output terminal of the third-stage operational amplifier unit OP3 and the positive input terminal of the fourth-stage operational amplifier unit OP4, the calibration capacitor C6 is connected between the negative output terminal of the third-stage operational amplifier unit OP3 and the negative input terminal of the fourth-stage operational amplifier unit OP4, and the calibration switch S4 is connected between the positive input terminal and the negative input terminal of the fourth-stage operational amplifier unit OP4;

[0012] The positive output terminal of the fourth-stage operational amplifier unit OP4 is connected to the positive input terminal of the subsequent-stage folding latch, and the negative output terminal of the fourth-stage operational amplifier unit OP4 is connected to the negative input terminal of the subsequent-stage folding latch;

[0013] The calibration switch S1, the calibration switch S2, the calibration switch S3 and the calibration switch S4 are all connected to the offset calibration clock signal input end, and the offset calibration clock signal input end is used to input the offset calibration clock signal CLK_CTRL in the offset calibration stage, and the offset calibration clock signal CLK_CTRL is used to control the closing and opening of the calibration switch S1, the calibration switch S2, the calibration switch S3 and the calibration switch S4.

[0014] In one embodiment of the present invention, the circuit structures of the first-stage operational amplifier unit OP1, the second-stage operational amplifier unit OP2, the third-stage operational amplifier unit OP3 and the fourth-stage operational amplifier unit OP4 are all the same.

[0015] In one embodiment of the present invention, the first-stage operational amplifier unit OP1 includes a MOS transistor M1, a MOS transistor M2, a MOS transistor M3, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6 and a current source I1, wherein:

[0016] The source of the MOS tube M3, the source of the MOS tube M4, the source of the MOS tube M5 and the source of the MOS tube M6 are all connected to the ground terminal GND.

[0017] The gate of the MOS tube M3 is connected to the gate of the MOS tube M4, the drain of the MOS tube M3, the drain of the MOS tube M5 and the drain of the MOS tube M1;

[0018] The gate of the MOS tube M5 is connected to the gate of the MOS tube M6, the drain of the MOS tube M6, the drain of the MOS tube M4 and the drain of the MOS tube M2;

[0019] The positive electrode of the current source I1 is connected to the power supply terminal VDD, the negative electrode of the current source I1 is connected to the source of the MOS transistor M1 and the source of the MOS transistor M2, the gate of the MOS transistor M1 serves as the positive input terminal VIP of the first-stage operational amplifier unit OP1, and the gate of the MOS transistor M2 serves as the negative input terminal VIN of the first-stage operational amplifier unit OP1;

[0020] The gate of the MOS transistor M3 serves as the negative output terminal OUT_N of the first-stage operational amplifier unit OP1 , and the gate of the MOS transistor M6 serves as the positive output terminal OUT_P of the first-stage operational amplifier unit OP1 .

[0021] In one embodiment of the present invention, the latter folding latch includes MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16, MOS tube M17, MOS tube M18, MOS tube M19, MOS tube M20, MOS tube M21, MOS tube M22, MOS tube M23, MOS tube M24, MOS tube M25, MOS tube M26, MOS tube M27, MOS tube M28, current source I2 and current source I3, wherein,

[0022] The drain of the MOS tube M7 and the drain of the MOS tube M8 are both connected to the power supply terminal VDD, the gate of the MOS tube M7 is connected to the positive output terminal of the pre-stage amplifier as the positive input terminal VI+ of the post-stage folding latch, the gate of the MOS tube M8 is connected to the negative output terminal of the pre-stage amplifier as the negative input terminal VI- of the post-stage folding latch, the source of the MOS tube M7 is connected to the drain of the MOS tube M17 and the source of the MOS tube M15, and the source of the MOS tube M8 is connected to the drain of the MOS tube M18 and the source of the MOS tube M16;

[0023] The current source I2 is connected between the source of the MOS tube M17 and the ground terminal GND, the current source I3 is connected between the source of the MOS tube M18 and the ground terminal GND, the gate of the MOS tube M17, the gate of the MOS tube M18, the gate of the MOS tube M15, and the gate of the MOS tube M16 are all input with the clock signal CLK, the drain of the MOS tube M15 is connected with the gate of the MOS tube M21, the gate of the MOS tube M22, the gate of the MOS tube M10, the gate of the MOS tube M11, the drain of the MOS tube M19, the drain of the MOS tube M20, and the source of the MOS tube M12, the drain of the MOS tube M16 is connected with the drain of the MOS tube M21, the drain of the MOS tube M22, the gate of the MOS tube M12, the gate of the MOS tube M13, the gate of the MOS tube M19, the gate of the MOS tube M20, and the source of the MOS tube M10;

[0024] The source of the MOS tube M21 and the source of the MOS tube M19 are both connected to the drain of the MOS tube M25 and the drain of the MOS tube M26, and the source of the MOS tube M22 and the source of the MOS tube M20 are both connected to the drain of the MOS tube M27 and the drain of the MOS tube M28; the source of the MOS tube M25 and the source of the MOS tube M26 are both connected to the power supply terminal VDD, the gate of the MOS tube M25 inputs the clock signal CLK, the gate of the MOS tube M26 is connected to the ground terminal GND, the source of the MOS tube M27 and the source of the MOS tube M28 are both connected to the ground terminal GND, and the gate of the MOS tube M28 is connected to the power supply terminal VDD;

[0025] The drain of the MOS tube M10 is connected to the drain of the MOS tube M11 and the drain of the MOS tube M9 and serves as the negative output terminal OUT- of the subsequent folding latch, and the source of the MOS tube M9 and the source of the MOS tube M11 are both connected to the ground terminal; the gate of the MOS tube M9 inputs the clock signal CLK;

[0026] The drain of the MOS tube M12 is connected to the drain of the MOS tube M13 and the drain of the MOS tube M14 and serves as the positive output terminal OUT+ of the subsequent folding latch. The source of the MOS tube M13 and the source of the MOS tube M14 are both connected to the ground terminal. The gate of the MOS tube M14 inputs the clock signal CLK.

[0027] The drain of the MOS tube M23 and the drain of the MOS tube M24 input the clock signal CLK, the source of the MOS tube M23 is connected to the power supply terminal VDD, the source of the MOS tube M24 is connected to the ground terminal GND, the gate of the MOS tube M23 and the gate of the MOS tube M24 are used to output the clock signal CLKN, and the gate of the MOS tube M24 is connected to the gate of the MOS tube M27.

[0028] In one embodiment of the present invention, the clock signal CLK and the clock signal CLKN are inverse signals.

[0029] In one embodiment of the present invention, the gate length L of the MOS transistor M26 and the gate width W of the MOS transistor M28 are both greater than the gate width W.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] 1. The present invention proposes a high-precision comparator based on a folding latch. Compared with the traditional comparator, the comparator of the present invention has a stronger ability to resist noise interference, consumes less power, and the working speed of the subsequent folding latch is faster. The comparator of the present invention has the performance characteristics of high precision, low power consumption and fast response speed.

[0032] 2. In the reset phase of the comparator of the present invention, when the two input signals VI+ and VI- of the rear-stage folding latch are transmitted to points P and Q, the preamplifier of the comparator works, and the input signals VI+ and VI- are amplified at points P and Q. Therefore, the noise of the MOS tube has a smaller impact on the signals at points P and Q, and the rear-stage folding latch can identify with higher accuracy. Compared with the traditional dynamic comparator, the comparator of the present invention has a stronger ability to resist noise interference.

[0033] 3. In the comparator of the present invention, the P and Q points are near the common mode level. When the latching stage arrives, the P and Q points are differentiated from the common mode level to the ground and power supply voltage, which is the case with the lowest power consumption, effectively reducing the time required for differentiation and improving the working speed of the latch. The switch tubes M17 and M18 control the on and off of the current sources I2 and I3. In the latching stage, the tail current generated by the current sources I2 and I3 is close to 0, and the power consumption is relatively small.

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a structural schematic diagram of a high-precision comparator based on a folding latch provided by an embodiment of the present invention;

[0036] Figure 2 is a circuit diagram of an operational amplifier unit provided by an embodiment of the present invention;

[0037] Figure 3 1 is a schematic diagram of a circuit structure of a rear-stage folding latch provided by an embodiment of the present invention;

[0038] Figure 4 This is a working timing diagram of a high-precision comparator provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the high-precision comparator based on the folding latch proposed in accordance with the present invention is described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0040] The above and other technical contents, features and effects of the present invention are clearly presented in the following detailed description of the specific implementation modes in conjunction with the accompanying drawings. Through the description of the specific implementation modes, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the attached drawings are only for reference and explanation purposes and are not used to limit the technical solutions of the present invention.

[0041] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the statement "including one..." do not exclude the existence of other identical elements in the article or device including the elements.

[0042] Embodiment 1

[0043] See also Figure 1 , Figure 1It is a structural diagram of a high-precision comparator based on a folding latch provided by an embodiment of the present invention. The high-precision comparator includes a pre-amplifier and a post-folding latch connected to each other, wherein the pre-amplifier includes an amplifier circuit and an offset calibration circuit, the amplifier circuit is used to amplify the input signal in the comparator working stage, the offset calibration circuit is used to store the offset voltage of the comparator in the offset calibration stage, and reduce the offset voltage of the comparator by offsetting in the comparator working stage, and the comparator working stage and the offset calibration stage are performed alternately; the post-folding latch is used to identify the amplified signal and reconstruct it into a logic high level and a logic low level.

[0044] The amplifier circuit of this embodiment includes four operational amplifier units, which play a role in signal amplification. The operational amplifier units of each stage have the same structure, and the offset calibration circuit includes an offset storage capacitor (calibration capacitor) and an offset calibration switch between the operational amplifier units of each stage. The capacitor is used to measure and store the offset through an independent offset calibration cycle to offset the offset during normal operation.

[0045] Specifically, the amplifier circuit of this embodiment includes a first-stage operational amplifier unit OP1, a second-stage operational amplifier unit OP2, a third-stage operational amplifier unit OP3 and a fourth-stage operational amplifier unit OP4, and the offset calibration circuit includes a calibration capacitor C1, a calibration capacitor C2, a calibration capacitor C3, a calibration capacitor C4, a calibration capacitor C5, a calibration capacitor C6, a calibration switch S1, a calibration switch S2, a calibration switch S3 and a calibration switch S4.

[0046] The calibration switch S1 is connected between the positive input terminal and the negative input terminal of the first-stage operational amplifier unit OP1, the calibration capacitor C1 is connected between the positive output terminal of the first-stage operational amplifier unit OP1 and the positive input terminal of the second-stage operational amplifier unit OP2, the calibration capacitor C4 is connected between the negative output terminal of the first-stage operational amplifier unit OP1 and the negative input terminal of the second-stage operational amplifier unit OP2, and the calibration switch S2 is connected between the positive input terminal and the negative input terminal of the second-stage operational amplifier unit OP2; the calibration capacitor C2 is connected between the positive output terminal of the second-stage operational amplifier unit OP2 and the positive input terminal of the third-stage operational amplifier unit OP3, the calibration capacitor C5 is connected between the negative output terminal of the second-stage operational amplifier unit OP2 and the negative input terminal of the third-stage operational amplifier unit OP3, and the calibration switch S3 is connected between the positive input terminal and the negative input terminal of the third-stage operational amplifier unit OP3.

[0047] The calibration capacitor C3 is connected between the positive output terminal of the third-stage operational amplifier unit OP3 and the positive input terminal of the fourth-stage operational amplifier unit OP4, the calibration capacitor C6 is connected between the negative output terminal of the third-stage operational amplifier unit OP3 and the negative input terminal of the fourth-stage operational amplifier unit OP4, and the calibration switch S4 is connected between the positive input terminal and the negative input terminal of the fourth-stage operational amplifier unit OP4; the positive output terminal of the fourth-stage operational amplifier unit OP4 is connected to the positive input terminal of the subsequent-stage folding latch, and the negative output terminal of the fourth-stage operational amplifier unit OP4 is connected to the negative input terminal of the subsequent-stage folding latch. The calibration switch S1, the calibration switch S2, the calibration switch S3 and the calibration switch S4 are all connected to the offset calibration clock signal input terminal, and the offset calibration clock signal input terminal is used to input the offset calibration clock signal CLK_CTRL in the offset calibration stage, and the offset calibration clock signal CLK_CTRL is used to control the closing and opening of the calibration switch S1, the calibration switch S2, the calibration switch S3 and the calibration switch S4.

[0048] Specifically, Figure 2 As shown, the first-stage operational amplifier unit OP1 includes a MOS tube M1, a MOS tube M2, a MOS tube M3, a MOS tube M4, a MOS tube M5, a MOS tube M6 and a current source I1, wherein the source of the MOS tube M3, the source of the MOS tube M4, the source of the MOS tube M5 and the source of the MOS tube M6 are all connected to the ground terminal GND, the gate of the MOS tube M3 is connected to the gate of the MOS tube M4, the drain of the MOS tube M3, the drain of the MOS tube M5 and the drain of the MOS tube M1; the gate of the MOS tube M5 is connected to the gate of the MOS tube M6, the drain of the MOS tube M6, the drain of the MOS tube M4 and the drain of the MOS tube M2. The positive electrode of the current source I1 is connected to the power supply terminal VDD, the negative electrode of the current source I1 is connected to the source of the MOS tube M1 and the source of the MOS tube M2, the gate of the MOS tube M1 serves as the positive input terminal VIP of the first-stage operational amplifier unit OP1, the gate of the MOS tube M2 serves as the negative input terminal VIN of the first-stage operational amplifier unit OP1; the gate of the MOS tube M3 serves as the negative output terminal OUT_N of the first-stage operational amplifier unit OP1, and the gate of the MOS tube M6 serves as the positive output terminal OUT_P of the first-stage operational amplifier unit OP1.

[0049] In this embodiment, the MOS transistor M1 and the MOS transistor M2 are input transistors, the MOS transistor M3 and the MOS transistor M6 are loads, and the MOS transistor M4 and the MOS transistor M5 form cross-coupled MOS transistors.

[0050] See also Figure 3 , Figure 31 is a circuit structure diagram of a rear-stage folding latch provided by an embodiment of the present invention. The rear-stage folding latch includes MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16, MOS tube M17, MOS tube M18, MOS tube M19, MOS tube M20, MOS tube M21, MOS tube M22, MOS tube M23, MOS tube M24, MOS tube M25, MOS tube M26, MOS tube M27, MOS tube M28, current source I2 and current source I3.

[0051] The drain of the MOS tube M7 and the drain of the MOS tube M8 are both connected to the power supply terminal VDD, the gate of the MOS tube M7 is connected to the positive output terminal of the front-stage amplifier as the positive input terminal VI+ of the rear-stage folding latch, the gate of the MOS tube M8 is connected to the negative output terminal of the front-stage amplifier as the negative input terminal VI- of the rear-stage folding latch, the source of the MOS tube M7 is connected to the drain of the MOS tube M17 and the source of the MOS tube M15, and the source of the MOS tube M8 is connected to the drain of the MOS tube M18 and the source of the MOS tube M16.

[0052] The current source I2 is connected between the source of the MOS tube M17 and the ground terminal GND, the current source I3 is connected between the source of the MOS tube M18 and the ground terminal GND, the gates of the MOS tube M17, the gates of the MOS tube M18, the gates of the MOS tube M15, and the gates of the MOS tube M16 all input the clock signal CLK, the drain of the MOS tube M15 is connected to the gates of the MOS tube M21, the gates of the MOS tube M22, the gates of the MOS tube M10, the gates of the MOS tube M11, the drains of the MOS tube M19, the drains of the MOS tube M20, and the source of the MOS tube M12, and the drains of the MOS tube M16 are connected to the drains of the MOS tube M21, the drains of the MOS tube M22, the gates of the MOS tube M12, the gates of the MOS tube M13, the gates of the MOS tube M19, the gates of the MOS tube M20, and the source of the MOS tube M10.

[0053] The source of the MOS tube M21 and the source of the MOS tube M19 are both connected to the drain of the MOS tube M25 and the drain of the MOS tube M26, the source of the MOS tube M22 and the source of the MOS tube M20 are both connected to the drain of the MOS tube M27 and the drain of the MOS tube M28; the source of the MOS tube M25 and the source of the MOS tube M26 are both connected to the power supply terminal VDD, the gate of the MOS tube M25 inputs the clock signal CLK, the gate of the MOS tube M26 is connected to the ground terminal GND, the source of the MOS tube M27 and the source of the MOS tube M28 are both connected to the ground terminal GND, and the gate of the MOS tube M28 is connected to the power supply terminal VDD.

[0054] The drain of the MOS tube M10 is connected to the drain of the MOS tube M11 and the drain of the MOS tube M9 and serves as the negative output terminal OUT- of the subsequent folding latch, and the source of the MOS tube M9 and the source of the MOS tube M11 are both connected to the ground terminal; the gate of the MOS tube M9 inputs the clock signal CLK; the drain of the MOS tube M12 is connected to the drain of the MOS tube M13 and the drain of the MOS tube M14 and serves as the positive output terminal OUT+ of the subsequent folding latch, and the source of the MOS tube M13 and the source of the MOS tube M14 are both connected to the ground terminal; the gate of the MOS tube M14 inputs the clock signal CLK; the drain of the MOS tube M23 and the drain of the MOS tube M24 input the clock signal CLK, the source of the MOS tube M23 is connected to the power supply terminal VDD, the source of the MOS tube M24 is connected to the ground terminal GND, the gate of the MOS tube M23 and the gate of the MOS tube M24 output the clock signal CLKN, and the gate of the MOS tube M24 is connected to the gate of the MOS tube M27.

[0055] Specifically, the MOS transistors M7 and M8 in the rear-stage folding latch of this embodiment are input transistors, the MOS transistors M9, M14, M15, M16, M17, M18, M25, M26, M27 and M28 are switching transistors, the MOS transistors M10, M11, M12, M13, M19, M20, M21, M22, M23 and M24 are inverter transistors, and I2 and I3 are bias current sources. The clock signal CLK and the clock signal CLKN are inverse signals.

[0056] The comparator working phase includes a reset phase and a latch phase which are alternating with each other. In the reset phase, the clock signal CLK is at a high level and the clock signal CLKN is at a low level. In the latch phase, the clock signal CLK is at a low level and the clock signal CLKN is at a high level.

[0057] like Figure 3 As shown, in the reset phase, the P point connected to the gate of the MOS tube M10 and the Q point connected to the gate of the MOS tube M12 are both set to the vicinity of the common mode level, and are affected by the input signals VI+ and VI-. The MOS tube M25 is turned off, and the MOS tube M26 is turned on. At this time, the voltage transmission capability is limited, and the voltage of the V1 node is set to "weak VDD"; the MOS tube M27 is turned off, and the MOS tube M28 is turned on. At this time, the voltage transmission capability is limited, and the voltage of the V2 node is set to "weak GND", and the output terminals OUT+ and OUT- of the subsequent folding latch are both set to high level.

[0058] In the latching stage, MOS tubes M25 and M26 are turned on, and the voltage of the V1 node is set to "strong VDD"; MOS tubes M27 and M28 are turned on, and the voltage of the V2 node is set to "strong GND". Points P and Q are affected by positive feedback and are quickly pulled to the high and low level output terminals. The output terminals OUT+ and OUT- are quickly pulled to high and low levels to complete the function of digital code output. The use of this post-stage folding latch can effectively improve the noise and accuracy performance of the comparator, and has the advantages of low power consumption and high speed.

[0059] In this embodiment, the clock signal CLK is connected to the gates of the switching tubes M9, M14, M15, M16, M17, and M18, the offset calibration clock signal CLK_CTRL is connected to the calibration switches S1, S2, S3, and S4, and the input signals VIP and VIN are respectively connected to the gates of the input tubes M1 and M2 of the first-stage operational amplifier unit OP1. The reference voltage VDD is at a high level, and the reference voltage GND is at a low level.

[0060] The working principle of the high-precision comparator based on the folding latch of the present invention is as follows:

[0061] The pre-amplifier of the high-precision comparator provides a large gain, amplifies the small differential signal input at the input end of the pre-amplifier to a sufficiently large amplitude, and then sends it to the post-stage folding latch. The post-stage folding latch then identifies the amplified signal and reconstructs it into logical high and low levels to achieve signal regeneration. In order to achieve higher-precision recognition, the gain of the pre-amplifier needs to be high enough, and the high gain requirement can be achieved through a multi-stage cascade.

[0062] like Figure 2 As shown, the MOS tube M1 and MOS tube M2 of the preamplifier form a differential input pair, the cross-coupled MOS tubes M4 and M5 and the diode-connected MOS tubes M3 and M6 provide loads, and the power supply terminal I1 provides bias current. The DC gain provided by the preamplifier It is expressed as:

[0063] ,

[0064] in, , , Indicates the transconductance of MOS tube M1, MOS tube M3, and MOS tube M4, , , , Indicates the output resistance of MOS tube M1, MOS tube M3, and MOS tube M4. Indicates parallel connection.

[0065] It can be seen from the amplifier DC gain expression that the negative resistance structure can achieve a higher gain as a load, and the front-stage amplifier realizes signal amplification of the input signals VIP and VIN. The positive output terminal OUT_P of the fourth-stage operational amplifier unit OP4 is connected to the positive input terminal of the subsequent folding latch, and the negative output terminal OUT_N of the fourth-stage operational amplifier unit OP4 is connected to the negative input terminal of the subsequent folding latch.

[0066] The preamplifier achieves high gain amplification through four-stage cascade connection. However, after the cascade connection, the operational amplifier unit of each stage will introduce an offset problem. To solve this problem, the present invention adopts output offset voltage calibration technology. The calibration capacitor is placed at the output end of the operational amplifier unit to isolate the preamplifier offset from the next stage circuit. Figure 4 , Figure 4 This is a working timing diagram of a high-precision comparator provided by an embodiment of the present invention. When the offset calibration clock signal CLK_CTRL is at a high level, the comparator performs an offset calibration phase, and the calibration switches S1, S2, S3, and S4 are closed, and the offset voltage information is stored on the calibration capacitors C1-C6. When the comparator is in the working phase, the offset calibration clock signal CLK_CTRL is at a low level, and the calibration switches S1, S2, S3, and S4 are disconnected, so that the initial offset voltage information can be removed from the signal path by offsetting.

[0067] like Figure 3 As shown, the post-stage folding latch includes two working stages. The first stage is the reset stage, in which the output signal is reset, and the second stage is the latch stage, in which the latch outputs a digital code value.

[0068] MOS tubes M7 and M8 form an input stage, converting the input signal into two differential currents. MOS tubes M19-M22 form a complementary coupled inverter positive feedback structure to complete the level setting of points P and Q, thereby determining the output latch result. MOS tubes M9 and M14 act as output reset switches to control the output signal to reset to a high level. MOS tubes M10-M13 act as inverter structures to control points P and Q to output the result to the latch output end. MOS tubes M15 and M16 act as input signal switch tubes to control the input signals VI+ and VI- to be transmitted to points P and Q. MOS tubes M7 and M8 act as switch tubes of current sources I2 and I3 to control the opening and closing of the current sources. MOS tubes M23 and M24 form an inverter structure to generate a clock signal CLKN, which is the reverse of the clock signal CLK. MOS tubes M25-M28 act as switch tubes to control the transmission of power supply signals and ground signals.

[0069] When the comparator is working, the CLK signal is at a high level, the CLKN signal is at a low level, and the latch is in a reset state. At this time, the switch tubes M9 and M14 are turned on, and the output terminals OUT+ and OUT- are set to a low level GND. The switch tubes M25 and M27 are turned off. The switch tubes M15, M16, M17, and M18 are turned on, and the input signal VI+ of the subsequent folding latch is transmitted to the node P, and the input signal VI- is transmitted to the node Q.

[0070] The gate of MOS tube M26 is connected to the ground terminal GND, and the gate of MOS tube M28 is connected to the power supply terminal VDD. M26 and M28 are constantly turned on. When designing, M26 and M28 are designed as inverse ratio tubes, that is, the gate length L of MOS tube M26 and MOS tube M28 is greater than the gate width W. At this time, although M26 and M28 are constantly turned on, their conduction capabilities are limited. At this time, the voltages of V1 and V2 nodes can be defined as "weak VDD" and "weak GND". Due to the limited ability to provide and extract current, the value of "weak VDD" will be lower than the value of VDD, and the value of weak "GND" will be higher than the weak GND.

[0071] Since the V1 node is at "weak VDD" and the V2 node is at "weak GND", the complementary coupling inverter formed by MOS tubes M19, M20, M21, and M22 as a latch structure will not pull the P and Q points to VDD and GND, but maintain them at the common mode level under the joint action of current sources I2, I3 and input voltages VI+ and VI-. If VI+>VI-, the common mode level is broken, the gate-source voltage of MOS tube M7 is greater than the gate-source voltage of MOS tube M8, the current flowing through MOS tube M7 is larger, and the charging capacity is stronger, the source voltage of MOS tube M15 is greater than the source voltage of MOS tube M16, and through the transmission action of MOS tubes M15 and M16, the P node voltage rises, the Q node voltage drops, and the P node voltage is slightly higher than the Q node voltage. If VI+>VI-, the common mode level is broken, the gate-source voltage of the MOS tube M7 is lower than the gate-source voltage of the MOS tube M8, the current flowing through the MOS tube M8 is larger, and the charging capacity is stronger. The source voltage of the MOS tube M15 is lower than the source voltage of the MOS tube M16. Through the transmission effect of the MOS tubes M15 and M16, the P node voltage drops, the Q node voltage rises, and the P node voltage is slightly lower than the Q node voltage.

[0072] When the clock signal CLK is at a low level, the switches M15, M16, M17, and M18 are turned off, and the values ​​of VI+ and VI- no longer affect the values ​​of the node voltages P and Q. At the same time, the switches M9 and M14 are turned off, so that the output nodes OUT+ and OUT- output the values ​​stored in the latch structure.

[0073] When the clock signal CLK is at a low level, the CLKN signal is at a high level. The switching transistors M9 and M14 are turned off. OUT+ and OUT- are floating, maintaining the low-level state during the reset phase. M15 and M16 are turned off, and the input signals VI+ and VI- no longer affect the voltages at points P and Q. M17 and M18 are turned off. At this time, the tail currents generated by current sources I2 and I3 are close to 0, greatly reducing the circuit power consumption at this time.

[0074] The switching transistors M25 and M27 are turned on. V1 is set from "weak VDD" to VDD, and V2 is set from "weak GND" to GND. When the clock signal CLK transitions from a high level to a low level, at the falling edge, the value of V1 is VDD and the value of V2 is GND. The complementary coupled inverter formed by M19, M20, M21, and M22, as a latch structure, will quickly differentiate the values existing at points P and Q, forming a positive feedback state.

[0075] If VI+ > VI-, the voltages VP > VQ stored at nodes P and Q during the reset phase. Under the action of the complementary coupled inverter, the voltage at point Q is pulled to GND, and the voltage at point P is pulled to VDD. The inverter formed by M12 and M13 works, and the output terminal OUT+ outputs a high level. The inverter formed by M10 and M11 is turned off, and the output terminal OUT_ maintains the low level output during the reset phase.

[0076] If VI+ < VI-, the voltages VP < VQ stored at nodes P and Q during the reset phase. Under the action of the complementary coupled inverter, the voltage at point Q is pulled to VDD, and the voltage at point P is pulled to GND. The inverter formed by M12 and M13 is turned off, and the output terminal OUT+ maintains the low level output during the reset phase. The inverter formed by M10 and M11 works, and the output terminal OUT_ outputs a high level.

[0077] The present invention proposes a high-precision comparator based on a folded latch. Compared with traditional comparators, the comparator of the present invention has stronger anti-noise interference ability, lower power consumption, and faster working speed of the subsequent folded latch. The comparator of the present invention has performance characteristics of high precision, low power consumption, and fast response speed.

[0078] During the reset phase of the comparator of the present invention, when the two input signals VI+ and VI- of the subsequent folded latch are transmitted to points P and Q, the preamplifier of the comparator works, and the input signals VI+ and VI- are amplified at points P and Q. Therefore, the noise of the MOS transistors has less influence on the signals at points P and Q, and the subsequent folded latch can recognize higher precision. Compared with traditional dynamic comparators, the comparator of the present invention has stronger anti-noise interference ability.

[0079] In the comparator of the present invention, the P and Q points are near the common mode level. When the latching stage arrives, the P and Q points are differentiated from the common mode level to the ground and power supply voltage, which is the case with the lowest power consumption, effectively reducing the time required for differentiation and improving the working speed of the latch. The switch tubes M17 and M18 control the on and off of the current sources I2 and I3. In the latching stage, the tail current generated by the current sources I2 and I3 is close to 0, and the power consumption is relatively small.

[0080] In the several embodiments provided by the present invention, it should be understood that the apparatus and method disclosed by the present invention can be implemented in other ways. For example, the apparatus embodiments described above are only illustrative, for example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation, for example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0081] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0082] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A high-precision comparator based on a folding latch, characterized in that: The invention comprises a front-stage amplifier and a rear-stage folding latch connected to each other, wherein: The preamplifier comprises an amplifier circuit and an offset calibration circuit, wherein the amplifier circuit is used to amplify the input signal in the comparator working stage, and the offset calibration circuit is used to store the offset voltage of the comparator in the offset calibration stage and reduce the offset voltage of the comparator by offsetting in the comparator working stage, wherein the comparator working stage and the offset calibration stage are performed alternately; The post-stage folding latch is used to identify the amplified signal and reconstruct it into a logic high level and a logic low level; The amplifier circuit includes a first-stage operational amplifier unit OP1, a second-stage operational amplifier unit OP2, a third-stage operational amplifier unit OP3 and a fourth-stage operational amplifier unit OP4, and the offset calibration circuit includes a calibration capacitor C1, a calibration capacitor C2, a calibration capacitor C3, a calibration capacitor C4, a calibration capacitor C5, a calibration capacitor C6, a calibration switch S1, a calibration switch S2, a calibration switch S3 and a calibration switch S4, wherein, The calibration switch S1 is connected between the positive input terminal and the negative input terminal of the first-stage operational amplifier unit OP1, the calibration capacitor C1 is connected between the positive output terminal of the first-stage operational amplifier unit OP1 and the positive input terminal of the second-stage operational amplifier unit OP2, the calibration capacitor C4 is connected between the negative output terminal of the first-stage operational amplifier unit OP1 and the negative input terminal of the second-stage operational amplifier unit OP2, and the calibration switch S2 is connected between the positive input terminal and the negative input terminal of the second-stage operational amplifier unit OP2; The calibration capacitor C2 is connected between the positive output terminal of the second-stage operational amplifier unit OP2 and the positive input terminal of the third-stage operational amplifier unit OP3, the calibration capacitor C5 is connected between the negative output terminal of the second-stage operational amplifier unit OP2 and the negative input terminal of the third-stage operational amplifier unit OP3, and the calibration switch S3 is connected between the positive input terminal and the negative input terminal of the third-stage operational amplifier unit OP3; The calibration capacitor C3 is connected between the positive output terminal of the third-stage operational amplifier unit OP3 and the positive input terminal of the fourth-stage operational amplifier unit OP4, the calibration capacitor C6 is connected between the negative output terminal of the third-stage operational amplifier unit OP3 and the negative input terminal of the fourth-stage operational amplifier unit OP4, and the calibration switch S4 is connected between the positive input terminal and the negative input terminal of the fourth-stage operational amplifier unit OP4; The positive output terminal of the fourth-stage operational amplifier unit OP4 is connected to the positive input terminal of the subsequent-stage folding latch, and the negative output terminal of the fourth-stage operational amplifier unit OP4 is connected to the negative input terminal of the subsequent-stage folding latch; The calibration switch S1, the calibration switch S2, the calibration switch S3 and the calibration switch S4 are all connected to an offset calibration clock signal input terminal, the offset calibration clock signal input terminal is used to input an offset calibration clock signal CLK_CTRL in the offset calibration stage, and the offset calibration clock signal CLK_CTRL is used to control the closing and opening of the calibration switch S1, the calibration switch S2, the calibration switch S3 and the calibration switch S4; The latter folding latch includes MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16, MOS tube M17, MOS tube M18, MOS tube M19, MOS tube M20, MOS tube M21, MOS tube M22, MOS tube M23, MOS tube M24, MOS tube M25, MOS tube M26, MOS tube M27, MOS tube M28, current source I2 and current source I3, wherein, The drain of the MOS tube M7 and the drain of the MOS tube M8 are both connected to the power supply terminal VDD, the gate of the MOS tube M7 is connected to the positive output terminal of the pre-stage amplifier as the positive input terminal VI+ of the post-stage folding latch, the gate of the MOS tube M8 is connected to the negative output terminal of the pre-stage amplifier as the negative input terminal VI- of the post-stage folding latch, the source of the MOS tube M7 is connected to the drain of the MOS tube M17 and the source of the MOS tube M15, and the source of the MOS tube M8 is connected to the drain of the MOS tube M18 and the source of the MOS tube M16; The current source I2 is connected between the source of the MOS tube M17 and the ground terminal GND, the current source I3 is connected between the source of the MOS tube M18 and the ground terminal GND, the gate of the MOS tube M17, the gate of the MOS tube M18, the gate of the MOS tube M15, and the gate of the MOS tube M16 are all input with the clock signal CLK, the drain of the MOS tube M15 is connected with the gate of the MOS tube M21, the gate of the MOS tube M22, the gate of the MOS tube M10, the gate of the MOS tube M11, the drain of the MOS tube M19, the drain of the MOS tube M20, and the source of the MOS tube M12, the drain of the MOS tube M16 is connected with the drain of the MOS tube M21, the drain of the MOS tube M22, the gate of the MOS tube M12, the gate of the MOS tube M13, the gate of the MOS tube M19, the gate of the MOS tube M20, and the source of the MOS tube M10; The source of the MOS tube M21 and the source of the MOS tube M19 are both connected to the drain of the MOS tube M25 and the drain of the MOS tube M26, and the source of the MOS tube M22 and the source of the MOS tube M20 are both connected to the drain of the MOS tube M27 and the drain of the MOS tube M28; the source of the MOS tube M25 and the source of the MOS tube M26 are both connected to the power supply terminal VDD, the gate of the MOS tube M25 inputs the clock signal CLK, the gate of the MOS tube M26 is connected to the ground terminal GND, the source of the MOS tube M27 and the source of the MOS tube M28 are both connected to the ground terminal GND, and the gate of the MOS tube M28 is connected to the power supply terminal VDD; The drain of the MOS tube M10 is connected to the drain of the MOS tube M11 and the drain of the MOS tube M9 and serves as the negative output terminal OUT- of the subsequent folding latch, and the source of the MOS tube M9 and the source of the MOS tube M11 are both connected to the ground terminal; the gate of the MOS tube M9 inputs the clock signal CLK; The drain of the MOS tube M12 is connected to the drain of the MOS tube M13 and the drain of the MOS tube M14 and serves as the positive output terminal OUT+ of the subsequent folding latch. The source of the MOS tube M13 and the source of the MOS tube M14 are both connected to the ground terminal. The gate of the MOS tube M14 inputs the clock signal CLK. The drain of the MOS tube M23 and the drain of the MOS tube M24 input the clock signal CLK, the source of the MOS tube M23 is connected to the power supply terminal VDD, the source of the MOS tube M24 is connected to the ground terminal GND, the gate of the MOS tube M23 and the gate of the MOS tube M24 are used to output the clock signal CLKN, and the gate of the MOS tube M24 is connected to the gate of the MOS tube M27.

2. The high-precision comparator based on the folding latch according to claim 1, characterized in that: The circuit structures of the first-stage operational amplifier unit OP1, the second-stage operational amplifier unit OP2, the third-stage operational amplifier unit OP3 and the fourth-stage operational amplifier unit OP4 are all the same.

3. The high-precision comparator based on the folding latch according to claim 2, characterized in that: The first-stage operational amplifier unit OP1 includes MOS transistors M1, M2, M3, M4, M5, M6 and a current source I1, wherein: The source of the MOS tube M3, the source of the MOS tube M4, the source of the MOS tube M5 and the source of the MOS tube M6 are all connected to the ground terminal GND. The gate of the MOS tube M3 is connected to the gate of the MOS tube M4, the drain of the MOS tube M3, the drain of the MOS tube M5 and the drain of the MOS tube M1; The gate of the MOS tube M5 is connected to the gate of the MOS tube M6, the drain of the MOS tube M6, the drain of the MOS tube M4 and the drain of the MOS tube M2; The positive electrode of the current source I1 is connected to the power supply terminal VDD, the negative electrode of the current source I1 is connected to the source of the MOS transistor M1 and the source of the MOS transistor M2, the gate of the MOS transistor M1 serves as the positive input terminal VIP of the first-stage operational amplifier unit OP1, and the gate of the MOS transistor M2 serves as the negative input terminal VIN of the first-stage operational amplifier unit OP1; The gate of the MOS transistor M3 serves as the negative output terminal OUT_N of the first-stage operational amplifier unit OP1 , and the gate of the MOS transistor M6 serves as the positive output terminal OUT_P of the first-stage operational amplifier unit OP1 .

4. The high-precision comparator based on the folding latch according to claim 3, characterized in that: The clock signal CLK and the clock signal CLKN are inverse signals.

5. The high-precision comparator based on the folding latch according to claim 4, characterized in that: The gate length L of the MOS transistor M26 and the gate width W of the MOS transistor M28 are both greater than the gate width W.

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