Low power consumption, low latency and high precision analog-to-digital converter based on high-order code pre-assignment

Abstract

The present invention provides a low-power, low-latency, high-precision analog-to-digital converter based on high-bit code pre-assignment, which relates to the technical field of mixed signal integrated circuits, including a sampling network, a differential DAC capacitor array, a comparator, a pre-assignment discrimination module and a SAR logic module, wherein the pre-assignment discrimination module is used to output a logic level according to an N-M-bit preset code value; the SAR logic module is used to store the preset code value and, when the logic level is a high logic level, use the M-bit preset high-bit code value as the M-bit high-bit code value of the current cycle, use the first target code value as the code value other than the M-bit high-bit code value of the current cycle, and output the first N-bit code value. The logic level output by the N-M-bit preset code value of the previous cycle is used as the basis for pre-assignment, and when the logic level is a high logic level, the SAR logic module uses the M-bit preset high-bit code value of the previous cycle as the M-bit high-bit code value of the current cycle, thereby reducing the number of conversion clock cycles and achieving low latency and high energy efficiency of conversion.

Description

Technical Field

[0001] The present invention relates to the technical field of mixed signal integrated circuits, and in particular to a low-power, low-delay, high-precision analog-to-digital converter based on high-order code pre-assignment. Background Art

[0002] With the booming development of digital signal processing technology, more and more analog signals need to be converted into digital signals for processing. Signals in nature are continuous analog signals, which need to be converted into discrete digital signals for faster and more energy-efficient processing. This makes the existing technology have higher and higher requirements for analog-to-digital converters (ADCs). Therefore, in most modern electronic systems, the performance of ADC is the limiting factor of the overall performance of the system. Improving ADC performance is the prerequisite for further improving the performance of signal processing systems, and research on ADC is imperative.

[0003] The Successive Approximation Register Analog to Digital Converter (SAR ADC) has a simple structure, low power consumption, and has the characteristics of low latency and high precision. Therefore, SAR ADC has gradually become the mainstream architecture of low-power, low-latency, and high-precision ADC. However, in high-precision applications, the input signal of the ADC is often accompanied by low-frequency characteristics, which means that the high-order code value of the quantization result of the analog-to-digital converter will remain unchanged for a certain period of time. If this part of the code value is still repeatedly quantized, it will undoubtedly cause a waste of time and power consumption, limiting the further improvement of the performance of the SAR ADC, making the conversion delay of the analog-to-digital converter to convert the analog signal to the digital signal longer and the power consumption higher. Summary of the invention

[0004] The purpose of the embodiment of the present invention is to provide a low-power, low-delay, high-precision analog-to-digital converter with pre-assigned high-bit codes, so as to solve the problem of long conversion delay and high power consumption of the analog-to-digital converter when converting analog signals into digital signals.

[0005] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0006] The present invention provides a low-power, low-delay, high-precision analog-to-digital converter based on high-bit code pre-assignment, comprising a sampling network, a differential digital-to-analog converter (DAC) capacitor array, a comparator, a pre-assignment judgment module and a SAR logic module;

[0007] A sampling network for collecting input signals and maintaining the input signals on the differential DAC capacitor array;

[0008] A differential DAC capacitor array, used to determine a preset top plate voltage according to a preset capacitor bottom plate signal when an input signal is maintained on the differential DAC capacitor array, wherein the preset capacitor bottom plate signal is a signal converted by a SAR logic module according to a preset control signal;

[0009] A comparator, connected to the sampling network and the differential DAC capacitor array, respectively, for determining a preset code value corresponding to a comparator output terminal level of a preset period according to a preset top plate voltage;

[0010] The SAR logic module is connected to the comparator and the differential DAC capacitor array, respectively, and is used to store and output a preset code value, where the preset code value is an N-bit preset code value, and the N-bit preset code value includes an M-bit preset high-order code value and an NM-bit preset code value;

[0011] The pre-assigned value discrimination module is connected to the SAR logic module and is used to output a logic level according to the preset code value of the NM bit;

[0012] The SAR logic module is also used to store preset code values, and when the logic level is a high logic level, the M-bit preset high-order code value is used as the M-bit high-order code value of the current cycle, and the first target code value is used as the code value other than the M-bit high-order code value of the current cycle to output the first N-bit code value, the preset cycle is the previous cycle of the current cycle, the first target code value is the target code value corresponding to the comparator output terminal level of the current cycle determined by the comparator according to the current first top plate voltage corresponding to the capacitors other than the high M-bit capacitors in the differential DAC capacitor array, and the current first top plate voltage is the voltage determined by the differential DAC capacitor array according to the current first capacitor bottom plate signal when the input signal is maintained on the differential DAC capacitor array.

[0013] In some embodiments, the SAR logic module is also used to use the second target code value as the second N-bit code value of the current cycle to output the second N-bit code value when the logic level is a low logic level. The second target code value is the target code value corresponding to the comparator output terminal level of the current cycle determined by the comparator based on the current second top plate voltage corresponding to the most significant bit capacitor in the differential DAC capacitor array. The current second top plate voltage is the voltage determined by the differential DAC capacitor array based on the current second capacitor bottom plate signal when the input signal is maintained on the differential DAC capacitor array.

[0014] In some embodiments, the pre-assignment judgment module includes a multi-input AND gate, a multi-input NOR gate and a two-input OR gate, the output end of the multi-input AND gate and the output end of the multi-input NOR gate are both connected to the input end of the two-input OR gate, the input end of the multi-input AND gate and the input end of the multi-input NOR gate are both connected to the SAR logic module, and the output end of the two-input OR gate is connected to the SAR logic module.

[0015] In some embodiments, the differential DAC capacitor array includes a first group of capacitors, a second group of capacitors, and a capacitor ,capacitance , first set of switches, second set of switches, switches ,switch ,switch ,switch ,switch , the first group of capacitors includes first high M-bit capacitors, and the second group of capacitors includes second high M-bit capacitors;

[0016] The top plates of each capacitor in the first group of capacitors are connected to the positive input terminal of the comparator, the switch The bottom plates of the capacitors in the first group of capacitors are connected to one end of each switch in the first group of switches in a one-to-one correspondence, and the other end of each switch in the first group of switches is connected to the SAR logic module; the top plates of the capacitors in the second group of capacitors are connected to the negative input end of the comparator, the switch The bottom plates of the capacitors in the second group of capacitors are connected to one end of each switch in the second group of switches in a one-to-one correspondence, and the other end of each switch in the second group of switches is connected to the SAR logic module; the switches The other end and switch The other end of The signals are connected;

[0017] capacitance One end of is connected to the top plate of the first high M-bit capacitor, the capacitor The other end is connected to the top plate of the capacitor except the first high M capacitor. One end is connected to the top plate of the second highest M-bit capacitor, and the capacitor The other end is connected to the top plates of all capacitors except the second highest M-bit capacitor;

[0018] switch One end is connected to the positive input of the comparator, and the switch The other end of Signal connection, switch One end is connected to the positive input of the comparator, and the switch The other end is connected to the negative input of the comparator. One end is connected to the negative input of the comparator, and the switch The other end of Signals are connected.

[0019] In some embodiments, the first group of capacitors and the second group of capacitors each include 2N capacitors, and the first group of switches and the second group of switches each include 2N switches.

[0020] In some embodiments, the pre-assigned value determination module is specifically used to determine whether the preset code values ​​of the NM bits are all 0 or all 1, and if so, output a low logic level, and if not, output a high logic level.

[0021] In some embodiments, the preset top plate voltage includes a positive preset top plate voltage and a negative preset top plate voltage, the input voltage of the positive input terminal of the comparator is the positive preset top plate voltage, and the input voltage of the negative input terminal of the comparator is the negative preset top plate voltage.

[0022] In some embodiments, the preset code value includes a first preset code value and a second preset code value, and the comparator is specifically used to determine whether the input voltage of the positive input terminal is less than the input voltage of the negative input terminal. If not, the positive output terminal outputs the first preset code value corresponding to the high level, and the negative output terminal outputs a low level. If so, the positive output terminal outputs the second preset code value corresponding to the low level, and the negative output terminal outputs a high level.

[0023] In some embodiments, the control signal includes a first control signal and a second control signal, and the SAR logic module is further used to convert the first control signal and the second control signal into capacitor bottom plate signals before storing the preset code value, and feed them back to the differential DAC capacitor array, and the capacitor bottom plate signals include a first capacitor bottom plate signal, a second capacitor bottom plate signal, a third capacitor bottom plate signal and a fourth capacitor bottom plate signal.

[0024] In some embodiments, the differential DAC capacitor array includes a first group of capacitors and a second group of capacitors, the first group of capacitors includes a first positive terminal capacitor and a second positive terminal capacitor, the second group of capacitors includes a first negative terminal capacitor and a second negative terminal capacitor, and the differential DAC capacitor array is specifically used to switch the first positive terminal capacitor according to the bottom plate signal of the first capacitor when the input signal is maintained on the differential DAC capacitor array, and switch the second positive terminal capacitor according to the bottom plate signal of the second capacitor to obtain a preset top plate voltage at the positive end, switch the first negative terminal capacitor according to the bottom plate signal of the third capacitor, and switch the second negative terminal capacitor according to the bottom plate signal of the fourth capacitor to obtain a preset top plate voltage at the negative end.

[0025] Compared with the prior art, the present invention provides a low-power, low-latency, high-precision analog-to-digital converter based on high-bit code pre-assignment, which uses the remaining NM-bit preset code values ​​of the previous cycle to output the corresponding logic level, and uses the corresponding logic level as the basis for whether the SAR logic module is pre-assigned. At the same time, when the logic level of the SAR logic module is a high logic level, the M-bit preset high-bit code value of the previous cycle is used as the M-bit high-bit code value of the current cycle. That is to say, the high M-bit capacitor is pre-assigned using the M-bit preset high-bit code value of the previous cycle, which can reduce the number of clock cycles required for the analog-to-digital converter conversion, so that the conversion power consumption is lower and the conversion delay is shorter, so as to achieve low latency and high energy efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0027] Figure 1 The schematic diagram of the structure of a low-power, low-delay, high-precision analog-to-digital converter based on high-order code pre-assignment is shown schematically;

[0028] Figure 2 The schematic diagram of the structure of the pre-assignment discrimination module is shown schematically;

[0029] Figure 3 The output spectrum of normal quantization modeling using matlab is schematically shown;

[0030] Figure 4 The output spectrum diagram of the low-power, low-delay, high-precision analog-to-digital converter with high-bit code pre-assignment of the present invention is schematically shown. DETAILED DESCRIPTION

[0031] The following is a further detailed description of the embodiments of the present invention in conjunction with the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to exemplarily illustrate the principles of the present invention, but cannot be used to limit the scope of the present invention. The present invention can be implemented in many different forms and is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

[0032] The following is a detailed description of a low-power, low-latency, high-precision analog-to-digital converter based on high-order code pre-assignment in an embodiment of the present invention.

[0033] See also Figure 1 As shown, Figure 1The schematic diagram of the structure of a low-power, low-latency, high-precision analog-to-digital converter based on high-order code pre-assignment is schematically shown. The embodiment of the present invention proposes a low-power, low-latency, high-precision analog-to-digital converter based on high-order code pre-assignment, including a sampling network, a differential DAC capacitor array, a comparator, a pre-assignment judgment module and a SAR logic module;

[0034] The sampling network is used to acquire the input signal and maintain it on the differential DAC capacitor array.

[0035] The differential DAC capacitor array is used to determine a preset top plate voltage according to a preset capacitor bottom plate signal when an input signal is maintained on the differential DAC capacitor array. The preset capacitor bottom plate signal is a signal converted by a SAR logic module according to a preset control signal.

[0036] The comparator is connected to the sampling network and the differential DAC capacitor array respectively, and is used to determine the preset code value corresponding to the comparator output terminal level of the preset period according to the preset top plate voltage.

[0037] The SAR logic module is connected to the comparator and the differential DAC capacitor array respectively, and is used to store and output a preset code value. The preset code value is an N-bit preset code value, and the N-bit preset code value includes an M-bit preset high-order code value and an NM-bit preset code value.

[0038] The pre-assigned value discrimination module is connected to the SAR logic module and is used to output a logic level according to the preset code value of the NM bit.

[0039] The SAR logic module is also used to store preset code values, and when the logic level is a high logic level, the M-bit preset high-order code value is used as the M-bit high-order code value of the current cycle, and the first target code value is used as the code value other than the M-bit high-order code value of the current cycle to output the first N-bit code value, the preset cycle is the previous cycle of the current cycle, the first target code value is the target code value corresponding to the comparator output terminal level of the current cycle determined by the comparator according to the current first top plate voltage corresponding to the capacitors other than the high M-bit capacitors in the differential DAC capacitor array, and the current first top plate voltage is the voltage determined by the differential DAC capacitor array according to the current first capacitor bottom plate signal when the input signal is maintained on the differential DAC capacitor array.

[0040] Specifically, the preset code value is the preset code value of the preset period, and correspondingly, the M-bit preset high-order code value is the M-bit preset high-order code value of the preset period, that is, the M-bit preset high-order code value of the previous period.

[0041] In this embodiment, the SAR logic module is also used to use the second target code value as the second N-bit code value of the current cycle to output the second N-bit code value when the logic level is a low logic level. The second target code value is the target code value corresponding to the comparator output terminal level of the current cycle determined by the comparator according to the current second top plate voltage corresponding to the most significant bit capacitor in the differential DAC capacitor array. The current second top plate voltage is the voltage determined by the differential DAC capacitor array according to the current second capacitor bottom plate signal when the input signal is maintained on the differential DAC capacitor array.

[0042] Specifically, the first N-bit code value and the second N-bit code value both include an N-bit target code value and an M-bit target high-order code value. When the period executed by the low-power, low-latency, high-precision analog-to-digital converter with a pre-assigned high-order code is greater than two periods, the preset code value is stored in the SAR logic module, and when the logic level is a high logic level, the M-bit preset high-order code value is used as the M-bit high-order code value of the current period, and the first target code value is used as the code value other than the M-bit high-order code value of the current period to output the first N-bit code value, and also includes: a pre-assigned judgment module, which is also used to output the target logic level according to the N-bit target code value and the M-bit target high-order code value; the SAR logic module is also used to use the first target code value or the second target code value as The preset code value is set, the target logic level is used as the logic level, and the M-bit target high-order code value is used as the M-bit preset high-order code value. The above-mentioned storage of the preset code value is repeated, and when the logic level is a high logic level, the M-bit preset high-order code value is used as the M-bit high-order code value of the current cycle, and the first target code value is used as the code value other than the M-bit high-order code value of the current cycle to output the first N-bit code value. When the logic level is a low logic level, the second target code value is used as the second N-bit code value of the current cycle to output the second N-bit code value, until the current cycle is the target cycle, and the final N-bit code value is output.

[0043] Specifically, the sampling network is a conventional sampling and holding circuit. The differential DAC capacitor array is a split capacitor array. The differential DAC capacitor array determines the preset top plate voltage according to the preset capacitor bottom plate signal through bottom plate sampling, and uses the preset top plate voltage as the input of the comparator. The comparator is a conventional comparator, which is used to compare the preset top plate voltage of the differential DAC capacitor array. The SAR logic module can also be called a SAR logic module with high-order code pre-assignment, and the high M bits are pre-assigned bits.

[0044] In this embodiment, Figure 2 The schematic diagram of the structure of the pre-assignment discrimination module is shown schematically, see Figure 2As shown, the pre-assigned value discrimination module includes a multi-input AND gate, a multi-input NOR gate and a two-input OR gate. The output of the multi-input AND gate and the output of the multi-input NOR gate are both connected to the input of the two-input OR gate. The input of the multi-input AND gate and the input of the multi-input NOR gate are both connected to the SAR logic module, and the output of the two-input OR gate is connected to the SAR logic module. Specifically, the input signals of the multi-input AND gate and the multi-input NOR gate are the NM-bit preset code values ​​of the preset cycle, i.e., the previous cycle, and the input signal of the multi-input AND gate is the NM-bit preset code value. The NM-bit preset code value is recorded as , the input signal of the multi-input NOR gate is the NM-bit preset code value, and the NM-bit preset code value is recorded as , the output of the two-input OR gate is the P_SIG signal, and the P_SIG signal corresponds to the logic level.

[0045] In this embodiment, the differential DAC capacitor array includes a first group of capacitors, a second group of capacitors, and a capacitor ,capacitance , first set of switches, second set of switches, switches ,switch ,switch ,switch ,switch , the first group of capacitors includes first high M-bit capacitors, and the second group of capacitors includes second high M-bit capacitors;

[0046] The top plates of each capacitor in the first group of capacitors are connected to the positive input terminal of the comparator, the switch The bottom plates of the capacitors in the first group of capacitors are connected to one end of each switch in the first group of switches in a one-to-one correspondence, and the other end of each switch in the first group of switches is connected to the SAR logic module; the top plates of the capacitors in the second group of capacitors are connected to the negative input end of the comparator, the switch The bottom plates of the capacitors in the second group of capacitors are connected to one end of each switch in the second group of switches in a one-to-one correspondence, and the other end of each switch in the second group of switches is connected to the SAR logic module; the switches The other end and switch The other end of The signals are connected;

[0047] capacitance One end of is connected to the top plate of the first high M-bit capacitor, the capacitor The other end is connected to the top plate of the capacitor except the first high M capacitor. One end is connected to the top plate of the second highest M-bit capacitor, and the capacitor The other end is connected to the top plates of all capacitors except the second highest M-bit capacitor;

[0048] switch One end is connected to the positive input of the comparator, and the switch The other end of Signal connection, switch One end is connected to the positive input of the comparator, and the switch The other end is connected to the negative input of the comparator. One end is connected to the negative input of the comparator, and the switch The other end of Signals are connected.

[0049] Specifically, the differential DAC capacitor array includes a first group of capacitors, a second group of capacitors, and a capacitor and capacitor The first group of capacitors includes a first positive terminal capacitor, that is, a positive terminal capacitor And the second positive terminal capacitor, that is, the positive terminal capacitor The number of the first positive terminal capacitor and the second positive terminal capacitor are both N, and the first positive terminal capacitor includes a capacitor , the second positive terminal capacitor includes capacitor The second group of capacitors includes a first negative terminal capacitor, namely a negative terminal capacitor And the second negative terminal capacitor, that is, the negative terminal capacitor The number of the first negative terminal capacitor and the second negative terminal capacitor are both N, and the first negative terminal capacitor includes a capacitor , the second negative terminal capacitor includes a capacitor The first switch group includes a first switch and a second switch, wherein the first switch includes a switch , the second switch includes a switch The second switch group includes a third switch and a fourth switch, and the third switch includes a switch , the fourth switch includes a switch .

[0050] The bottom plates of each capacitor in the first group of capacitors are connected to one end of each switch in the first group of switches in a one-to-one correspondence. That is, the first positive terminal capacitor in the first group of capacitors The bottom plate and the first switch of the first set of switches The first group of capacitors is connected to the second positive terminal capacitor The bottom plate and the second switch in the first set of switches The first positive terminal capacitor is connected in a one-to-one correspondence. With the first switch Corresponding connection, the second positive terminal capacitor With the second switch Corresponding connections are made, and so on, the bottom plates of each capacitor in the first group of capacitors are correspondingly connected with one end of each switch in the first group of switches.

[0051] The bottom plates of each capacitor in the second group of capacitors are connected to one end of each switch in the second group of switches in a one-to-one correspondence. That is, the first negative terminal capacitor in the second group of capacitors The bottom plate of the second switch and the third switch in the second switch group The second negative terminal capacitor in the second group of capacitors is connected one by one. The bottom plate of the second switch and the fourth switch of the second switch group The first negative terminal capacitor is connected in a one-to-one correspondence. With the third switch Corresponding connection, the second negative terminal capacitor With the fourth switch Corresponding connections are made, and so on, the bottom plates of each capacitor in the second group of capacitors are correspondingly connected with one end of each switch in the second group of switches.

[0052] The sampling network reuses the high five capacitors of the differential DAC capacitor array. The high five capacitors are capacitors ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance .capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance are connected to the positive input of the comparator, the capacitor ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance ,capacitance Both are connected to the negative input of the comparator.

[0053] The other end of each switch corresponding to the upper five capacitors is also connected to , GND or The switches corresponding to the upper five capacitors are switches. ,switch ,switch ,switch ,switch ,switch ,switch ,switch ,switch ,switch ,switch ,switch ,switch ,switch ,switch ,switch ,switch ,switch ,switch ,switch The other ends of the switches other than the switches corresponding to the upper five capacitors are also connected to Or connect to GND.

[0054] In this embodiment, the first group of capacitors and the second group of capacitors each include 2N capacitors, and the first group of switches and the second group of switches each include 2N switches.

[0055] Specifically, the preset code value corresponding to the 2N capacitors is an N-bit preset code value.

[0056] In this embodiment, the control signal includes a first control signal and a second control signal. The SAR logic module is also used to convert the first control signal and the second control signal into capacitor bottom plate signals before storing the preset code value, and feed them back to the differential DAC capacitor array. The capacitor bottom plate signals include a first capacitor bottom plate signal, a second capacitor bottom plate signal, a third capacitor bottom plate signal and a fourth capacitor bottom plate signal.

[0057] Specifically, the first control signal may be 0 or 1, the second control signal may also be 0 or 1, the first capacitor bottom plate signal, i.e., the P_CA signal, may be 0 or 1, the second capacitor bottom plate signal, i.e., the P_CB signal, may be 0 or 1, the third capacitor bottom plate signal, i.e., the N_CA signal, may be 0 or 1, and the fourth capacitor bottom plate signal, i.e., the N_CB signal, may be 0 or 1. The capacitor bottom plate signal may be 1, 0, 0, 1, or 0, 1, 1, 0, etc.

[0058] In this embodiment, the differential DAC capacitor array includes a first group of capacitors and a second group of capacitors, the first group of capacitors includes a first positive terminal capacitor and a second positive terminal capacitor, the second group of capacitors includes a first negative terminal capacitor and a second negative terminal capacitor, and the differential DAC capacitor array is specifically used to switch the first positive terminal capacitor according to the bottom plate signal of the first capacitor and switch the second positive terminal capacitor according to the bottom plate signal of the second capacitor when the input signal is maintained on the differential DAC capacitor array to obtain a preset top plate voltage at the positive end, switch the first negative terminal capacitor according to the bottom plate signal of the third capacitor, and switch the second negative terminal capacitor according to the bottom plate signal of the fourth capacitor to obtain a preset top plate voltage at the negative end.

[0059] Specifically, in the differential DAC capacitor array, the first positive capacitor is switched according to the bottom plate signal of the first capacitor, so that the voltage of the preset bottom plate corresponding to the first positive capacitor is switched, and the second positive capacitor is switched according to the bottom plate signal of the second capacitor, so that the voltage of the preset bottom plate corresponding to the second positive capacitor is switched, and according to the law of conservation of charge, the corresponding preset top plate voltage will change accordingly, and the positive preset top plate voltage will be obtained. The first negative capacitor is switched according to the bottom plate signal of the third capacitor, so that the voltage of the preset bottom plate corresponding to the first negative capacitor is switched, and the second negative capacitor is switched according to the bottom plate signal of the fourth capacitor, so that the voltage of the preset bottom plate corresponding to the second negative capacitor is switched, and according to the law of conservation of charge, the corresponding preset top plate voltage will change accordingly, and the negative preset top plate voltage will be obtained.

[0060] Exemplarily, when the capacitor bottom plate signal is 1, 0, 0, 1, that is, the first capacitor bottom plate signal, i.e., the P_CA signal, is 1, the second capacitor bottom plate signal, i.e., the P_CB signal, is 0, the third capacitor bottom plate signal, i.e., the N_CA signal, is 0, and the fourth capacitor bottom plate signal, i.e., the N_CB signal, is 1, the first positive terminal capacitor is switched according to the first capacitor bottom plate signal, and the first positive terminal capacitor is switched to GND, and the second positive terminal capacitor is switched according to the second capacitor bottom plate signal, and the second positive terminal capacitor is switched to , to obtain a preset top plate voltage at the positive end; switch the first negative terminal capacitor according to the bottom plate signal of the third capacitor, and switch the first negative terminal capacitor to , switching the second negative terminal capacitor according to the fourth capacitor bottom plate signal, switching the second negative terminal capacitor to GND to obtain a negative terminal preset top plate voltage.

[0061] In this embodiment, the preset top plate voltage includes a positive end preset top plate voltage and a negative end preset top plate voltage, the input voltage of the positive input terminal of the comparator is the positive end preset top plate voltage, and the input voltage of the negative input terminal of the comparator is the negative end preset top plate voltage.

[0062] In this embodiment, the preset code value includes a first preset code value and a second preset code value, and the comparator is specifically used to determine whether the input voltage of the positive input terminal is less than the input voltage of the negative input terminal. If not, the positive output terminal outputs the first preset code value corresponding to the high level, and the negative output terminal outputs a low level. If so, the positive output terminal outputs the second preset code value corresponding to the low level, and the negative output terminal outputs a high level.

[0063] Specifically, when the comparator determines that the input voltage of the positive input terminal is not less than the input voltage of the negative input terminal, the positive output terminal outputs a first preset code value corresponding to a high level, and the negative output terminal outputs a low level, and the first preset code value is transmitted to the SAR logic module; when the comparator determines that the input voltage of the positive input terminal is less than the input voltage of the negative input terminal, the positive output terminal outputs a second preset code value corresponding to a low level, and the negative output terminal outputs a high level, and the second preset code value is transmitted to the SAR logic module.

[0064] In this embodiment, the pre-assigned value determination module is specifically used to determine whether the preset code values ​​of the NM bits are all 0 or all 1, and if so, output a low logic level, and if not, output a high logic level.

[0065] Specifically, the input signals of the multi-input AND gate and the multi-input NOR gate in the pre-assigned judgment module are all NM-bit preset code values ​​of the previous cycle. The pre-assigned bit code value is an M-bit preset high-order code value.

[0066] The pre-assignment judgment module is specifically used to judge whether the preset code values ​​of the NM bits except the pre-assigned bit code values ​​in the previous cycle are all 0 or all 1. If the preset code values ​​of the NM bits except the pre-assigned bit code values ​​in the previous cycle are all 0 or all 1, the high-order code pre-assignment method of the SAR logic module is incorrect, and a low logic level is output; if the preset code values ​​of the NM bits except the pre-assigned bit code values ​​in the previous cycle are both 0 and 1, the high-order code pre-assignment method of the SAR logic module is correct, and a high logic level is output.

[0067] The high-order code pre-assignment method refers to a method of using the M-bit preset high-order code value of the previous cycle as the M-bit high-order code value of the current cycle.

[0068] Figure 3 The output spectrum of normal quantization modeled using matlab is schematically shown. Figure 4 The output spectrum diagram of the low-power, low-delay, high-precision analog-to-digital converter with high-order code pre-assignment of the present invention is schematically shown, see Figure 3 and Figure 4 As shown, Figure 3 and Figure 4The horizontal axis represents the frequency, and the unit is MHz, and the vertical axis represents the full-scale normalized amplitude, and the unit is dB. When the sampling frequency is 4 MSps and the input signal frequency is 3.90625 KHz, the 16-bit SAR ADC of the low-power, low-latency, high-precision analog-to-digital converter with high-order code pre-assignment of the present invention achieves the ideal SAR ADC performance modeled using matlab, and the spurious free dynamic range (SFDR), total harmonic distortion (THD), signal-to-noise ratio (SNR), signal-to-noise distortion ratio (SNDR), and effective number of bits (ENOB) are 117.2dB, -115.9dB, 97.7dB, 97.6dB, and 15.92bit, respectively.

[0069] The low-power, low-latency, high-precision analog-to-digital converter based on high-order code pre-assignment of the embodiment of the present invention comprises a sampling network, a differential DAC capacitor array, a comparator, a pre-assignment judgment module and a SAR logic module; the sampling network is used to collect input signals and keep the input signals on the differential DAC capacitor array; the differential DAC capacitor array is used to determine the preset top plate voltage according to the preset capacitor bottom plate signal when the input signal is kept on the differential DAC capacitor array; the comparator is respectively connected to the sampling network and the differential DAC capacitor array, and is used to determine the preset code value corresponding to the comparator output terminal level of the preset period according to the preset top plate voltage; the SAR logic module is respectively connected to the comparator and the differential DAC capacitor array, and is used to store and output the preset code value; the pre-assignment judgment module is connected to the sampling network and the differential DAC capacitor array, and is used to store and output the preset code value; the pre-assignment judgment module is connected to the sampling network and the differential DAC capacitor array, and is used to determine the preset top plate voltage according to the preset top plate voltage. The SAR logic module is connected to output a logic level according to an NM-bit preset code value; the SAR logic module is also used to store the preset code value, and when the logic level is a high logic level, use the M-bit preset high-order code value as the M-bit high-order code value of the current cycle, and use the first target code value as the code value other than the M-bit high-order code value of the current cycle to output the first N-bit code value, the preset cycle is the previous cycle of the current cycle, the first target code value is the target code value corresponding to the comparator output terminal level of the current cycle determined by the comparator according to the current first top plate voltage corresponding to the capacitor other than the high M-bit capacitor in the differential DAC capacitor array, and the current first top plate voltage is the voltage determined by the differential DAC capacitor array according to the current first capacitor bottom plate signal when the input signal is maintained on the differential DAC capacitor array. In this way, the corresponding logic level is outputted using the remaining NM-bit preset code values ​​of the previous cycle, and the corresponding logic level is used as the basis for whether the SAR logic module is pre-assigned. At the same time, when the logic level is a high logic level, the SAR logic module uses the M-bit preset high-order code value of the previous cycle as the M-bit high-order code value of the current cycle. That is to say, the high M-bit capacitor is pre-assigned using the M-bit preset high-order code value of the previous cycle, which can reduce the number of clock cycles required for the analog-to-digital converter conversion, so that the conversion power consumption is lower and the conversion delay is shorter, so as to achieve low latency and high energy efficiency.

[0070] Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should be understood by those skilled in the art that the above embodiments may be modified or some technical features may be replaced by equivalents without departing from the scope and spirit of the present invention. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there is no structural conflict.

[0071] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A low-power, low-delay, high-precision analog-to-digital converter based on high-order code pre-assignment, characterized in that: The low-power, low-delay, high-precision analog-to-digital converter based on high-order code pre-assignment includes a sampling network, a differential DAC capacitor array, a comparator, a pre-assignment judgment module and a SAR logic module; The sampling network is used to collect input signals and keep the input signals on the differential DAC capacitor array; The differential DAC capacitor array is used to determine a preset top plate voltage according to a preset capacitor bottom plate signal when the input signal is maintained on the differential DAC capacitor array, wherein the preset capacitor bottom plate signal is a signal converted by the SAR logic module according to a preset control signal; The comparator is connected to the sampling network and the differential DAC capacitor array, respectively, and is used to determine a preset code value corresponding to the level of the comparator output terminal of a preset period according to the preset top plate voltage, wherein the preset top plate voltage includes a positive preset top plate voltage and a negative preset top plate voltage, the input voltage of the positive input terminal of the comparator is the positive preset top plate voltage, the input voltage of the negative input terminal of the comparator is the negative preset top plate voltage, and the preset code value includes a first preset code value and a second preset code value; The SAR logic module is connected to the comparator and the differential DAC capacitor array, respectively, and is used to store and output the preset code value, where the preset code value is an N-bit preset code value, and the N-bit preset code value includes an M-bit preset high-order code value and an NM-bit preset code value; The pre-assigned value determination module is connected to the SAR logic module and is used to output a logic level according to the NM bit preset code value; The SAR logic module is further used to store the preset code value, and when the logic level is a high logic level, use the M-bit preset high-order code value as the M-bit high-order code value of the current cycle, and use the first target code value as the code value other than the M-bit high-order code value of the current cycle to output a first N-bit code value, wherein the preset cycle is the previous cycle of the current cycle, and the first target code value is the target code value corresponding to the comparator output terminal level of the current cycle determined by the comparator according to the current first top plate voltage corresponding to the capacitors other than the high M-bit capacitors in the differential DAC capacitor array, and the current first top plate voltage is the voltage determined by the differential DAC capacitor array according to the current first capacitor bottom plate signal when the input signal is maintained on the differential DAC capacitor array; The comparator is specifically used to determine whether the input voltage of the positive input terminal is less than the input voltage of the negative input terminal. If not, the positive output terminal outputs the first preset code value corresponding to the high level, and the negative output terminal outputs a low level. If so, the positive output terminal outputs the second preset code value corresponding to the low level, and the negative output terminal outputs a high level.

2. The low-power, low-delay, high-precision analog-to-digital converter based on high-order code pre-assignment according to claim 1, characterized in that: The SAR logic module is also used to use the second target code value as the second N-bit code value of the current cycle to output the second N-bit code value when the logic level is a low logic level, wherein the second target code value is the target code value corresponding to the comparator output terminal level of the current cycle determined by the comparator according to the current second top plate voltage corresponding to the most significant bit capacitor in the differential DAC capacitor array, and the current second top plate voltage is the voltage determined by the differential DAC capacitor array according to the current second capacitor bottom plate signal when the input signal is maintained on the differential DAC capacitor array.

3. The low-power, low-delay, high-precision analog-to-digital converter based on high-order code pre-assignment according to claim 1, characterized in that: The pre-assignment discrimination module includes a multi-input AND gate, a multi-input NOR gate and a two-input OR gate, the output end of the multi-input AND gate and the output end of the multi-input NOR gate are both connected to the input end of the two-input OR gate, the input end of the multi-input AND gate and the input end of the multi-input NOR gate are both connected to the SAR logic module, and the output end of the two-input OR gate is connected to the SAR logic module.

4. The low-power, low-delay, high-precision analog-to-digital converter based on high-order code pre-assignment according to claim 1, characterized in that: The differential DAC capacitor array includes a first group of capacitors, a second group of capacitors, and a capacitor ,capacitance , first set of switches, second set of switches, switches ,switch ,switch ,switch ,switch , the first group of capacitors includes first high M-bit capacitors, and the second group of capacitors includes second high M-bit capacitors; The top plate of each capacitor in the first group of capacitors is connected to the positive input terminal of the comparator, the switch The bottom plates of the capacitors in the first group of capacitors are connected to one end of each switch in the first group of switches in a one-to-one correspondence, and the other end of each switch in the first group of switches is connected to the SAR logic module; the top plates of the capacitors in the second group of capacitors are connected to the negative input end of the comparator, the switch The bottom plates of the capacitors in the second group of capacitors are connected to one end of each switch in the second group of switches in a one-to-one correspondence, and the other end of each switch in the second group of switches is connected to the SAR logic module; the switches The other end and the switch The other end of The signals are connected; The capacitor One end of is connected to the top plate of the first high M-bit capacitor, the capacitor The other end is connected to the top plate of the capacitor except the first high M-bit capacitor, the capacitor One end of is connected to the top plate of the second high M-bit capacitor, the capacitor The other end of is connected to the top plates of the capacitors except the second highest M-bit capacitor; The switch One end of the switch is connected to the positive input terminal of the comparator. The other end of signal is connected, the switch One end of the switch is connected to the positive input terminal of the comparator. The other end of the switch is connected to the negative input terminal of the comparator. One end of the switch is connected to the negative input terminal of the comparator. The other end of Signals are connected.

5. The low-power, low-delay, high-precision analog-to-digital converter based on high-order code pre-assignment according to claim 4, characterized in that: The first group of capacitors and the second group of capacitors each include 2N capacitors, and the first group of switches and the second group of switches each include 2N switches.

6. The low-power, low-delay, high-precision analog-to-digital converter based on high-order code pre-assignment according to claim 1, characterized in that: The pre-assigned value determination module is specifically used to determine whether the NM bit preset code values ​​are all 0 or all 1, and if so, output a low logic level, and if not, output the high logic level.

7. The low-power, low-delay, high-precision analog-to-digital converter based on high-order code pre-assignment according to claim 1, characterized in that: The control signal includes a first control signal and a second control signal. The SAR logic module is further used to convert the first control signal and the second control signal into the capacitor bottom plate signal before storing the preset code value, and feed it back to the differential DAC capacitor array. The capacitor bottom plate signal includes a first capacitor bottom plate signal, a second capacitor bottom plate signal, a third capacitor bottom plate signal and a fourth capacitor bottom plate signal.

8. The low-power, low-delay, high-precision analog-to-digital converter based on high-order code pre-assignment according to claim 7, characterized in that: The differential DAC capacitor array includes a first group of capacitors and a second group of capacitors, the first group of capacitors includes a first positive capacitor and a second positive capacitor, the second group of capacitors includes a first negative capacitor and a second negative capacitor, and the differential DAC capacitor array is specifically used to switch the first positive capacitor according to the first capacitor bottom plate signal and switch the second positive capacitor according to the second capacitor bottom plate signal when the input signal is maintained on the differential DAC capacitor array to obtain the positive end preset top plate voltage, switch the first negative capacitor according to the third capacitor bottom plate signal, and switch the second negative capacitor according to the fourth capacitor bottom plate signal to obtain the negative end preset top plate voltage.

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