Silicon modulator with lateral capacitance structure

Abstract

The present invention relates to a silicon modulator with a lateral capacitance structure, belonging to the field of semiconductor technology. The silicon modulator comprises, from bottom to top, a substrate, a dielectric layer, a ridge waveguide, a capacitor dielectric layer, a first transparent electrode, a second transparent electrode, a first contact metal, a second contact metal, a third contact metal, a fourth contact metal and an upper cladding layer; the ridge waveguide comprises a P-doped region, an N-doped region, a P+ region, a P++ region, an N+ region and an N++ region. The present invention can improve the bandwidth of the silicon modulator.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a silicon modulator with a lateral capacitance structure. Background Art

[0002] Silicon-based optoelectronic devices refer to optoelectronic devices that use silicon as an optical waveguide. Silicon-based optoelectronic devices are transparent in the near-infrared band and have important applications in fiber-optic communication systems. Since silicon is commonly used as a substrate for integrated circuits, silicon-based optoelectronics can integrate optical and electronic devices on a single chip. This hybrid device can be manufactured using existing semiconductor manufacturing technology and can provide optical interconnects for faster data transmission between chips and within chips. Therefore, people's interest in silicon-based optoelectronics has increased.

[0003] Silicon modulators are responsible for loading electrical signals into the optical domain in optical fiber communication systems and are core components that affect system bandwidth, energy consumption, and signal integrity. Silicon modulators based on plasma dispersion effects use the charge and discharge of carriers in the PN junction region to achieve high-speed modulation, but the series resistance of the PN junction limits the charge and discharge speed of the PN junction, resulting in low bandwidth for silicon modulators, which require corresponding technologies for improvement. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a silicon modulator with a lateral capacitor structure to solve the problem of increasing the bandwidth of the silicon modulator in the prior art.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A silicon modulator with a lateral capacitor structure includes a substrate 3, a dielectric layer 2, a ridge waveguide 10, a capacitor dielectric layer 20, a first transparent electrode 108, a second transparent electrode 101, a first contact metal 130, a second contact metal 131, a third contact metal 132, a fourth contact metal 133 and an upper cladding layer 4.

[0007] The dielectric layer 2 is disposed on a substrate 3 .

[0008] The ridge waveguide 10 is arranged on the dielectric layer 2; the ridge waveguide 10 includes a PN junction, a P+ region 106, a P++ region 107, an N+ region 103 and an N++ region 104; the PN junction includes a P-doped region 105 and an N-doped region 102 adjacent to its right side; the right side of the P+ region 106 is adjacent to the lower half of the left side of the P-doped region 105; the right side of the P++ region 107 is adjacent to the left side of the P+ region 106; the left side of the N+ region 103 is adjacent to the lower half of the right side of the N-doped region 102; the left side of the N++ region 104 is adjacent to the right side of the N+ region 103.

[0009] The capacitor dielectric layer 20 is disposed on the ridge waveguide 10 .

[0010] The first transparent electrode 108 is arranged above the left side of the capacitor dielectric layer 20, and the first transparent electrode 108, the capacitor dielectric layer 20, the P-doped region 105, the P+ region 106 and the P++ region 107 form a P-region lateral capacitor structure; the second transparent electrode 101 is arranged above the right side of the capacitor dielectric layer 20, and the second transparent electrode 101, the capacitor dielectric layer 20, the N-doped region 102, the N+ region 103 and the N++ region 104 form an N-region lateral capacitor structure;

[0011] The first contact metal 130 is arranged on the P++ region 107; the second contact metal 131 is arranged on the N++ region 104; the third contact metal 132 is arranged on the first transparent electrode 108; the fourth contact metal 133 is arranged on the second transparent electrode 101; the lower parts of the first contact metal 130, the second contact metal 131, the third contact metal 132 and the fourth contact metal 133 are all embedded in the upper cladding layer 4.

[0012] The upper cladding layer 4 is disposed on the dielectric layer 2 . The ridge waveguide 10 , the capacitor dielectric layer 20 , the first transparent electrode 108 , and the second transparent electrode 101 are embedded in the upper cladding layer 4 .

[0013] Preferably, a radio frequency signal RF is applied between the first contact metal 130 and the second contact metal 131; a direct current voltage DC1 is applied between the first contact metal 130 and the third contact metal 132 to regulate the capacitance value formed by the first transparent electrode 108 and the capacitor dielectric layer 20, the P-doped region 105, the P+ region 106 and the P++ region 107, wherein the amplitude of the direct current voltage is 0V to 10V, and 0V represents that no direct current voltage is applied between the first contact metal 130 and the third contact metal 132.

[0014] A DC voltage DC2 is applied between the second contact metal 131 and the fourth contact metal 133 to regulate the capacitance value formed by the second transparent electrode 101 and the capacitor dielectric layer 20, the N-doped region 102, the N+ region 103 and the N++ region 104, wherein the amplitude of the DC voltage is 0V to 10V, and 0V represents that no DC voltage is applied between the second contact metal 131 and the fourth contact metal 133.

[0015] Preferably, the thickness h3 of the capacitor dielectric layer 20 is 0 nm to 100 nm, wherein the thickness 0 nm represents that the first transparent electrode 108 and the second transparent electrode 101 are in direct contact with the ridge waveguide 10 at the same time.

[0016] Preferably, the thickness h1 of the slab region of the ridge waveguide 10 is ≥ 0 nm, wherein 0 nm represents the transformation of the ridge waveguide into a strip waveguide.

[0017] Preferably, a distance w2 between the first transparent electrode 108 and the second transparent electrode 101 is 50 nm to 500 nm.

[0018] Preferably, the thickness h4 of the first transparent electrode 108 and the second transparent electrode 101 is 10 nm to 1000 nm. Preferably, the first transparent electrode 108 and the second transparent electrode 101 are made of transparent conductive oxide material. The refractive index of the first transparent electrode 108 and the second transparent electrode 101 between 1.2 μm and 1.7 μm is 1.0 to 2.5, and the extinction coefficient is 1×10 -5 ~1×10 -3 , the resistivity is 1×10 -4 Ω.cm~1×10 -2 Ω.cm.

[0019] Preferably, the dielectric layer 2 is made of silicon dioxide SiO2 material.

[0020] Preferably, the ridge waveguide 10 is made of single crystal silicon material.

[0021] The beneficial effect of the present invention is that: the present invention connects a transparent electrode with high conductivity, low extinction coefficient and low refractive index in parallel on the conventional PN junction series resistor, so that the modulator has lower series resistance and higher bandwidth.

[0022] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0024] Figure 1 is a cross-sectional view of a silicon modulator having a lateral capacitor structure;

[0025] Figure 2 yes Figure 1 The equivalent circuit diagram of the modulator;

[0026] Figure 3 yes Figure 1 The lateral capacitance of the ridge region of the modulator, where (a) transparent electrode / SiO2 / p-Si, (b) transparent electrode / SiO2 / n-Si

[0027] Figure 4 yes Figure 1The 3dB electro-optical bandwidth of the modulator;

[0028] Reference numerals:

[0029] Figure 1 In the figure, 1-upper semiconductor layer, 2-dielectric layer (insulator), 3-substrate (semiconductor), 4-upper cladding, 10-ridge waveguide, 20-capacitor dielectric layer, 102-N doped region, 103-N+ region, 104-N++ region, 105-P doped region, 106-P+ region, 107-P++ region, 108-first transparent electrode, 101-second transparent electrode, 130-first contact metal, 131-second contact metal, 132-third contact metal, 133-fourth contact metal; 140-RF voltage signal applied by the modulator, 141 and 142 are DC signals on the left and right sides respectively, which are used to control the working point of the device. DETAILED DESCRIPTION

[0030] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0031] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0032] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0033] Silicon modulators can use interferometers such as Mach-Zehnder interferometers and ring oscillators to form optical modulators. Modulator efficiency, optical insertion loss, and modulation bandwidth can be defined by the phase section within the interferometer or within the oscillator. The refractive index of the phase section can be changed by applying a voltage, which can change the electron and hole density. Changes in the refractive index can change the intensity and phase of the interferometer or oscillator output.

[0034] The bandwidth of the silicon modulator is limited by the PN junction capacitance C j and series resistance R j The bandwidth and R j and C j Negatively correlated, as shown in the following equation. Bandwidth and C j The traditional method is to reduce C j To improve the bandwidth of the modulator, but this is at the expense of modulation efficiency. Ideally, reducing the PN junction series resistance R j , which can effectively improve the modulator bandwidth without affecting the modulation efficiency.

[0035]

[0036] Where ZMOD is the characteristic impedance of the modulator PN junction phase shifter, and LMOD is the length of the phase shifter.

[0037] Embodiment 1:

[0038] Figure 1 Schematic diagram of a silicon modulator with a transparent electrode according to this embodiment. The modulator provides an improvement over the existing silicon modulator. The modulator provides a variety of benefits and advantages, including: for example, a transparent electrode with high conductivity, low extinction coefficient and low refractive index is connected in parallel to the conventional PN junction series resistor, so that the modulator has a lower series resistance and a higher bandwidth. Figure 1 As shown, the modulator is formed on a portion of an SOI wafer having a semiconductor substrate 3, a dielectric layer (insulator) 2 and an upper semiconductor layer 1. The modulator also includes a ridge waveguide 10, a capacitor dielectric layer 20, a first transparent electrode 108, a second transparent electrode 101, a first contact metal 130, a second contact metal 131, a third contact metal 132, and a fourth contact metal 133.

[0039] The ridge waveguide 10 can be formed by, for example, etching away some portions of the upper semiconductor layer 1. Although the sidewalls of the ridge waveguide 10 are Figure 110 is drawn as vertical, but it should be appreciated that the sidewalls of the ridge waveguide 10 may be slightly rounded or inclined in view of the semiconductor manufacturing process. The ridge waveguide 10 includes a PN junction, the PN junction including a P-doped region 105 and an adjacent N-doped region 102. The ridge waveguide 10 also includes a P+ region 106 adjacent to the P-doped region 105, a P++ region 107 adjacent to the P+ region 106, an N+ region 103 adjacent to the N-doped region 102, and an N++ region 104 adjacent to the N+ region 103.

[0040] The first transparent electrode 108 is arranged above the left side of the capacitor dielectric layer 20, and the first transparent electrode 108, the capacitor dielectric layer 20, the P-doped region 105, the P+ region 106 and the P++ region 107 form a P-region lateral capacitor structure; the second transparent electrode 101 is arranged above the right side of the capacitor dielectric layer 20, and the second transparent electrode 101, the capacitor dielectric layer 20, the N-doped region 102, the N+ region 103 and the N++ region 104 form an N-region lateral capacitor structure; under high-frequency signal loading conditions, the flat region current of the ridge waveguide flows into the transparent electrode through the lateral capacitor, and flows to the PN junction through the transparent electrode, forming a low-impedance high-frequency path, thereby improving microwave dielectric loss.

[0041] In the present embodiment, the substrate 3 is formed of silicon, a silicon-containing material, or another suitable substrate material. The dielectric layer 2 is disposed on the substrate 3. In the present embodiment, the dielectric layer 2 is a buried oxide (BOX), such as, for example, silicon dioxide or other suitable insulators. The upper semiconductor layer 1 is disposed on the dielectric layer 2. In the present embodiment, the upper semiconductor layer 1 is formed of silicon or other suitable semiconductor materials.

[0042] In this embodiment, the doping concentration of the P-doped region 105 and the N-doped region 102 is 100 Å / cm3. 3 )5×10 17 atoms. The doping concentration of P+ region 106 and N+ region 103 is per cubic centimeter (cm 3 )2×10 18 atoms. The doping concentration of P++ region 107 and N++ region 104 is per cubic centimeter (cm 3 )1×10 20 In Embodiment 1, the thickness h2 of the upper semiconductor layer 1 is between about 110 nm and about 220 nm. The width w1 of the ridge waveguide 10 is between about 300 nm and about 1000 nm.

[0043] The capacitor dielectric layer 20 is silicon dioxide or other suitable insulators, and is formed by, for example, thermal oxidation or atomic layer deposition. In Example 1, thermally oxidized silicon dioxide is used, and the thickness h3 is between 2 nm and 10 nm.

[0044] In this embodiment, the thickness of the first transparent electrode 108 and the second transparent electrode 101 is 100nm-300nm, and the transparent electrode spacing w2 is about 100nm-500nm. In one embodiment, the refractive index of the first transparent electrode 108 and the second transparent electrode 101 between 1.3μm and 1.6μm is 1.5-2.0, and the extinction coefficient is 1×10 -5 ~1×10 -3 , the resistivity is 1×10 -4 Ω.cm~1×10 -3 Ω.cm. In Example 1, the first transparent electrode 108 and the second transparent electrode 101 are transparent conductive oxides (including but not limited to indium tin oxide (ITO), indium tungsten oxide (IWO), indium oxide (IO), indium hydroxide-doped indium (IOH), tungsten-doped indium tin oxide (IWTO), indium titanium oxide (ITiO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), tungsten-doped tin dioxide (SnO2:W), zinc oxide (ZnO), etc.).

[0045] The first contact metal 130 is disposed on the P++ region 107, the second contact metal 131 is disposed on the N++ region 104, the third contact metal 132 is disposed on the first transparent electrode 108, and the fourth contact metal 133 is disposed on the second transparent electrode 101. In Embodiment 1, the first contact metal 130 and the second contact metal 131 are aluminum, tungsten or any other material that forms a low ohmic contact resistance with silicon, and the third contact metal 132 and the fourth contact metal 133 are aluminum, tungsten or any other material that forms a low ohmic contact resistance with a transparent conductive material.

[0046] A radio frequency signal RF is applied between the first contact metal 130 and the second contact metal 131; a direct current voltage DC1 is applied between the first contact metal 130 and the third contact metal 132 to adjust the capacitance value formed by the first transparent electrode 108 and the capacitor dielectric layer 20, the P-doped region 105, the P+ region 106 and the P++ region 107. In an embodiment, according to the work function of the transparent conductive material and the work function of p-type silicon, the direct current voltage between the first contact metal 130 and the third contact metal 132 is 0V, and a large flat-band capacitance can be obtained; a direct current voltage DC2 is applied between the second contact metal 131 and the fourth contact metal 133 to adjust the capacitance value formed by the second transparent electrode 101 and the capacitor dielectric layer 20, the P-doped region 102, the P+ region 103 and the P++ region 104. In an embodiment, according to the work function of the transparent conductive material and the work function of n-type silicon, -1V is applied between the second contact metal 131 and the fourth contact metal 133, so that the energy band of n-type silicon at the Si / SiO2 interface is a flat band.

[0047] Figure 2 for Figure 1The equivalent circuit diagram of the modulator. The lateral capacitors Cslab and Crib provide a high-frequency path for the modulator PN junction series resistance, which is connected by the low resistance R TCO , transparent electrode and capacitor dielectric layer and doped plate area to form capacitors Cslab and Crib. In the high-frequency component of the modulated signal, the current will flow along R TCO The lateral capacitor circulates with Cslab and Crib to reduce the plate area resistance rslab. Since the plate resistance is the main part of the entire series resistance, the lateral capacitor can significantly reduce the overall series resistance and improve the bandwidth.

[0048] Figure 3 for Figure 2 The lateral capacitance Crib of the ridge region of the modulator exceeds 3000pF / m at the appropriate DC voltage operating point, which is much larger than the PN junction capacitance of about 200pF / m, ensuring the voltage division of the PN junction. Since the planar capacitance Cslab is much larger than Crib, only the value of Crib is given.

[0049] Figure 4 for Figure 1 In one embodiment, the thickness of the capacitor dielectric layer is 2 nm, no voltage is applied between the first contact metal 130 and the third contact metal 132, and a voltage of -1 V is applied between the second contact metal 131 and the fourth contact metal 133. The 3dB electro-optical bandwidth is increased from 40 GHz in the conventional structure to 120 GHz.

[0050] Although the present invention has provided some embodiments, it should be understood that the disclosed systems and methods may be embodied in many other specific forms without departing from the spirit or scope of the present disclosure. The present embodiments are to be considered illustrative rather than restrictive, and the intention is not to be limited to the details given herein. For example, various elements or components may be combined or integrated in another system, or specific features may be omitted or not implemented.

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A silicon modulator having a lateral capacitance structure, characterized in that: The silicon modulator comprises a substrate (3), a dielectric layer (2), a ridge waveguide (10), a capacitor dielectric layer (20), a first transparent electrode (108), a second transparent electrode (101), a first contact metal (130), a second contact metal (131), a third contact metal (132), a fourth contact metal (133) and an upper cladding layer (4); The dielectric layer (2) is arranged on a substrate (3); The ridge waveguide (10) is arranged on the dielectric layer (2); the ridge waveguide (10) comprises a PN junction, a P+ region (106), a P++ region (107), an N+ region (103) and an N++ region (104); the PN junction comprises a P-doped region (105) and an N-doped region (102) adjacent to the right side thereof; the right side of the P+ region (106) is adjacent to the lower half of the left side of the P-doped region (105); the right side of the P++ region (107) is adjacent to the left side of the P+ region (106); the left side of the N+ region (103) is adjacent to the lower half of the right side of the N-doped region (102); and the left side of the N++ region (104) is adjacent to the right side of the N+ region (103); The capacitor dielectric layer (20) is arranged on the ridge waveguide (10); The first transparent electrode (108) is arranged above the left side of the capacitor dielectric layer (20), and the first transparent electrode (108) forms a P-region lateral capacitor structure with the capacitor dielectric layer (20), the P-doped region (105), the P+ region (106) and the P++ region (107); the second transparent electrode (101) is arranged above the right side of the capacitor dielectric layer (20), and the second transparent electrode (101) forms an N-region lateral capacitor structure with the capacitor dielectric layer (20), the N-doped region (102), the N+ region (103) and the N++ region (104); The first contact metal (130) is arranged on the P++ region (107); the second contact metal (131) is arranged on the N++ region (104); the third contact metal (132) is arranged on the first transparent electrode (108); the fourth contact metal (133) is arranged on the second transparent electrode (101); the lower parts of the first contact metal (130), the second contact metal (131), the third contact metal (132) and the fourth contact metal (133) are all embedded in the upper cladding layer (4); the first contact metal (130) and the second contact metal (131) are connected to each other. A radio frequency signal RF is applied between the first contact metal (130) and the third contact metal (132); a direct current voltage DC1 is applied between the first contact metal (130) and the third contact metal (132) to adjust the capacitance value formed by the first transparent electrode (108) and the capacitor dielectric layer (20), the P-doped region (105), the P+ region (106) and the P++ region (107); a direct current voltage DC2 is applied between the second contact metal (131) and the fourth contact metal (133) to adjust the capacitance value formed by the second transparent electrode (101) and the capacitor dielectric layer (20), the N-doped region (102), the N+ region (103) and the N++ region (104); The upper cladding layer (4) is arranged on the dielectric layer (2); the ridge waveguide (10), the capacitor dielectric layer (20), the first transparent electrode (108), and the second transparent electrode (101) are embedded in the upper cladding layer (4).

2. The silicon modulator according to claim 1, characterized in that A DC voltage DC1 is applied between the first contact metal (130) and the third contact metal (132), wherein the amplitude of the DC voltage is 0V-10V, and 0V represents that no DC voltage is applied between the first contact metal (130) and the third contact metal (132); A DC voltage DC2 is applied between the second contact metal (131) and the fourth contact metal (133), wherein the amplitude of the DC voltage is 0V-10V, and 0V represents that no DC voltage is applied between the second contact metal (131) and the fourth contact metal (133).

3. The silicon modulator according to claim 1, characterized in that The thickness h3 of the capacitor dielectric layer (20) is 0 nm to 100 nm, wherein a thickness of 0 nm represents that the first transparent electrode (108) and the second transparent electrode (101) are in direct contact with the ridge waveguide (10) at the same time.

4. The silicon modulator according to claim 1, characterized in that The thickness h1 of the slab region of the ridge waveguide (10) is ≥ 0 nm, wherein 0 nm represents the transformation of the ridge waveguide into a strip waveguide.

5. The silicon modulator according to claim 1, characterized in that The distance w2 between the first transparent electrode (108) and the second transparent electrode (101) is 50 nm to 500 nm.

6. The silicon modulator according to claim 1, characterized in that The thickness h4 of the first transparent electrode (108) and the second transparent electrode (101) is 10 nm to 1000 nm.

7. The silicon modulator according to claim 1, 5 or 6, characterized in that: The first transparent electrode (108) and the second transparent electrode (101) are made of transparent conductive oxide material.

8. The silicon modulator according to claim 1, characterized in that The dielectric layer (2) is made of silicon dioxide SiO2 material.

9. The silicon modulator according to claim 1, characterized in that The ridge waveguide (10) is made of single crystal silicon material.

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