Check code generation method and memory

Abstract

The present application discloses a verification code generation method and a memory. The verification code generation method first generates a corresponding verification code based on storage data and programming data corresponding to first address data and obtained synchronously, and then stores the verification code in a storage space corresponding to second address data in a page buffer. The corresponding verification code can be generated based on the storage data and programming data obtained synchronously. Compared with generating the corresponding verification code based on storage data and programming data obtained asynchronously, the time required for the verification code processing process is reduced, thereby improving the verification code processing efficiency.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a verification code generation method and a memory. Background Art

[0002] In some applications, such as in-vehicle applications, in order to further improve reliability, it has become a necessary function for the memory to verify the programming data input by the user and generate a corresponding verification code.

[0003] Since the programming operation of some memories can only rewrite the "1" in the storage unit to "0" but cannot rewrite "0" to "1", when the user enters the programming instruction, the memory must first compare the programming data entered by the user with the previously stored data, and then obtain the correct check code based on the processing result and write it into the storage array together with the programming data.

[0004] However, the above-mentioned verification code processing process takes a long time, which reduces the processing efficiency of the verification code. Summary of the invention

[0005] The present application provides a verification code generation method and a memory to alleviate the technical problem of low verification code processing efficiency.

[0006] In a first aspect, the present application provides a verification code generation method, which includes: generating a corresponding verification code based on storage data and programming data corresponding to first address data and acquired synchronously; storing the verification code in a storage space corresponding to second address data in a page buffer, wherein before storing the verification code, the second address data is the same as the first address data.

[0007] In some of the embodiments, a corresponding verification code is generated based on the storage data and programming data corresponding to the first address data and obtained synchronously, including: synchronously obtaining the storage data and programming data corresponding to the first address data; generating intermediate data according to the logical operation results of the storage data and the programming data; and verifying the intermediate data to generate a verification code.

[0008] In some embodiments, synchronously acquiring storage data and programming data corresponding to first address data includes: outputting storage data corresponding to the first address data from a storage array in a first time period according to a first control signal; and outputting programming data corresponding to the first address data from a page buffer in the first time period according to a second control signal.

[0009] In some embodiments, outputting storage data corresponding to first address data from a storage array in a first time period according to a first control signal includes: configuring the first time period to be the duration of a pulse of the first control signal; and outputting storage data corresponding to the first address data from the storage array in response to a falling edge of the first control signal in the first time period.

[0010] In some embodiments, outputting programming data corresponding to first address data from a page buffer in a first time period according to a second control signal includes: configuring the second control signal to have at least one pulse in the first time period; and outputting programming data corresponding to the first address data from the page buffer in response to the second control signal.

[0011] In some embodiments, intermediate data is generated based on the logical operation results of the storage data and the programming data, including: generating intermediate data at the beginning of the second time period; and the intermediate data is verified to generate a verification code, including: generating a verification code at the end of the second time period.

[0012] In some embodiments, storing the check code in the storage space corresponding to the second address data in the page buffer includes: configuring a third time period after the second time period; in the third time period, in response to a pulse of a third control signal, storing the check code in the storage space corresponding to the second address data in the page buffer.

[0013] In some embodiments, the verification code generating method further includes: configuring the first address data and the second address data to be generated in the first address counter and the second address counter respectively; before storing the verification code, updating the second address data in the second address counter to the first address data; automatically carrying the first address data in the first address counter; and executing storage data and programming data corresponding to the first address data and synchronously acquired to generate a corresponding verification code.

[0014] In some implementation modes, the verification code generation method further includes: before the first verification code corresponding to each write instruction starts to be generated, assigning the first address data as the starting address data corresponding to the programming data.

[0015] In a second aspect, the present application provides a memory comprising a first address counter, a second address counter and a processing module, wherein the first address counter is used to generate first address data; the second address counter is used to generate second address data identical to the first address data before storing a verification code; the processing module is used to generate a corresponding verification code based on storage data and programming data corresponding to the first address data and acquired synchronously, and is used to store the verification code in a page buffer corresponding to the second address data.

[0016] In some embodiments, the processing module includes a storage array, a page buffer, a data processing unit and a verification generation unit, the storage array is used to output storage data corresponding to the first address data according to a first control signal; the page buffer is used to output programming data corresponding to the first address data according to a second control signal, and store the verification code to the storage space corresponding to the second address data according to a third control signal; the data processing unit is used to generate intermediate data based on the logical operation results of the storage data and the programming data; the verification generation unit is used to verify the intermediate data to generate a corresponding verification code.

[0017] In a third aspect, the present application provides a verification code generation method, which includes: generating a corresponding verification code based on storage data and programming data that are synchronously acquired and correspond to different address data; and storing the verification code in a corresponding storage space in a page buffer.

[0018] In some of the embodiments, a corresponding verification code is generated based on the storage data and programming data that are synchronously acquired and correspond to different address data, including: in the n-1th cycle, the storage data corresponding to the n-1th address data and the programming data corresponding to the n-2th address data are synchronously acquired; in the nth cycle, the storage data corresponding to the nth address data and the programming data corresponding to the n-1th address data are synchronously acquired; and the verification code is obtained according to the logical operation result of the storage data corresponding to the n-1th address data and the programming data corresponding to the n-1th address data.

[0019] In some implementations, storing the check code in a corresponding storage space in the page buffer includes: in an (n+1)th cycle, storing the check code in a storage space corresponding to an (n-1)th address data in the page buffer.

[0020] The verification code generation method and memory provided in the present application generate corresponding verification codes based on storage data and programming data acquired synchronously, thereby reducing the time required for the verification code processing process compared to generating corresponding verification codes based on storage data and programming data acquired asynchronously, thereby improving the processing efficiency of the verification code. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0022] Figure 1 A schematic diagram of the processing flow of the verification code provided in an embodiment of the present application.

[0023] Figure 2 A first flow chart of a verification code generation method provided in an embodiment of the present application.

[0024] Figure 3A second flow chart of the verification code generation method provided in an embodiment of the present application.

[0025] Figure 4 A first principle block diagram of a memory provided in an embodiment of the present application.

[0026] Figure 5 A second principle block diagram of the memory provided in an embodiment of the present application.

[0027] Figure 6 A timing diagram of a memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0029] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. The features specified as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0030] Figure 1 The entire verification process of the programming data corresponding to each programming instruction is divided into three steps:

[0031] The first step: read out the corresponding storage data from the storage array, for example, obtain the storage data corresponding to A1, obtain the storage data corresponding to A2, obtain the storage data corresponding to A3, obtain the storage data corresponding to A4, obtain the storage data corresponding to A5... obtain the storage data corresponding to An, etc.

[0032] Step 2: Read the corresponding programming data from the page buffer, and process it with the read storage data to obtain the check code through calculation. Read the corresponding programming data from the page buffer, for example, obtain the programming data corresponding to A1, obtain the programming data corresponding to A2, obtain the programming data corresponding to A3, obtain the programming data corresponding to A4... obtain the programming data corresponding to An-1, obtain the programming data corresponding to An, etc.

[0033] Step 3: Store the check code in the page buffer, for example, store the check code in the storage space corresponding to B1, store the check code in the storage space corresponding to B2, store the check code in the storage space corresponding to B3...store the check code in the storage space corresponding to Bn-2, store the check code in the storage space corresponding to Bn-1, and store the check code in the storage space corresponding to Bn.

[0034] Among them, A1 is the starting address corresponding to the programming data input by the user, and A2...An is the address data automatically carried forward based on A1. B1...Bn is the address data, which is respectively the same as A1...An, that is, B1 is equal to A1, B2 is equal to A2... and so on, Bn is equal to An. The storage space corresponding to any address data in A1...An and B1...Bn can be used to store the corresponding data and / or check code.

[0035] The verification code stored in the storage space corresponding to B1 is obtained after processing the storage data corresponding to A1 and the programming data corresponding to A1. Similarly, the verification code stored in the storage space corresponding to Bn is obtained after processing the storage data corresponding to An and the programming data corresponding to An.

[0036] In order to improve efficiency, the above process is operated in a pipeline manner, so that the verification code corresponding to the programming data input by the user can be quickly obtained and stored in the corresponding page buffer.

[0037] The above pipeline method is specifically as follows: from the first cycle to the nth cycle, the storage data corresponding to A1...An is obtained in sequence, from the second cycle to the n+1th cycle, the programming data corresponding to A1...An is obtained in sequence, and from the third cycle to the n+2th cycle, the verification code is stored in sequence in the storage space corresponding to B1...Bn. In the first cycle, the storage data corresponding to A1 is obtained; in the second cycle, the storage data corresponding to A2 is obtained, and the programming data corresponding to A1 is obtained; in the third cycle, the storage data corresponding to A3 is obtained, and the programming data corresponding to A2 is obtained, and the verification code is stored in the storage space corresponding to B1; and so on, in the nth cycle, the storage data corresponding to An is obtained, and the programming data corresponding to An-1 is obtained, and the verification code is stored in the storage space corresponding to Bn-2; in the n+1th cycle, the programming data corresponding to An is obtained, and the verification code is stored in the storage space corresponding to Bn-1; in the n+2th cycle, the verification code is stored in the storage space corresponding to Bn.

[0038] Based on this, this embodiment provides a verification code generation method, which includes: generating a corresponding verification code based on storage data and programming data that are synchronously acquired and correspond to different address data; storing the verification code in a corresponding storage space in a page buffer.

[0039] It can be understood that since the storage data and programming data corresponding to different address data are obtained synchronously, compared with the non-pipelined operation mode, the number of cycles used is reduced and the processing efficiency of the check code is improved.

[0040] Wherein, based on the storage data and programming data corresponding to different address data that are synchronously acquired, a corresponding verification code is generated, including: in the n-1th cycle, the storage data corresponding to the n-1th address data and the programming data corresponding to the n-2th address data are synchronously acquired; in the nth cycle, the storage data corresponding to the nth address data and the programming data corresponding to the n-1th address data are synchronously acquired; and the verification code is obtained according to the logical operation result of the storage data corresponding to the n-1th address data and the programming data corresponding to the n-1th address data.

[0041] The step of storing the check code in a corresponding storage space in the page buffer includes: in the (n+1)th cycle, storing the check code in a storage space corresponding to the (n-1)th address data in the page buffer.

[0042] In the above process, obtaining the storage data corresponding to An and obtaining the programming data corresponding to An are not performed synchronously, but are performed one after another. Therefore, obtaining the A1...An required for storing the data requires a group of address lines, obtaining the A1...An required for programming data requires another group of address lines, and storing the B1...Bn required for the verification code requires another group of address lines. Therefore, the pipeline operation requires three groups of address lines.

[0043] It is understandable that if the programming data input by the user at one time needs to be divided into n operations to generate n verification codes, it takes (n+2) cycles to generate and store n verification codes. Compared with the non-pipelined operation method, the number of cycles used is reduced and the processing efficiency of the verification codes is improved.

[0044] This embodiment provides a verification code generation method. Figures 2 to 6 ,like Figure 2 As shown, the verification code generation method includes the following steps:

[0045] Step S10: Generate a corresponding verification code based on the storage data and programming data corresponding to the first address data and acquired synchronously.

[0046] Step S20: storing the check code into the storage space corresponding to the second address data in the page buffer.

[0047] It can be understood that the verification code generation method provided in this embodiment is that the storage data IOSA and the programming data PBOUT corresponding to the same first address data AX are obtained synchronously, and only one set of address lines for transmitting the first address data AX is needed to achieve it, and the second address data BX required for storing the verification code ECCOUT only needs another set of address lines to be transmitted. Compared with the three sets of address lines required to generate and store the verification code ECCOUT, the number of address line groups required for generating the verification code ECCOUT is further reduced.

[0048] Furthermore, compared with the storage data IOSA and programming data PBOUT corresponding to the same first address data AX, which are acquired step by step, in the pipeline generation process of n check codes ECCOUT, it takes n+2 working cycles to complete, while in the present embodiment, the storage data IOSA and programming data PBOUT corresponding to the same first address data AX are acquired synchronously, in the pipeline generation process of n check codes ECCOUT, it only takes n+1 working cycles to complete, which reduces the number of working cycles used and improves the processing efficiency of the check code ECCOUT.

[0049] It should be noted that the first address data is not always equal to the second address data at all times before the check code ECCOUT is stored, but the second address data is equal to the first address data only after the second address data in the second address counter is updated to the first address data. The second address data BX is the same as the first address data AX, so that the generated check code ECCOUT is stored in the storage space corresponding to the same address data as the programming data PBOUT. In some embodiments, the programming data PBOUT and the check code ECCOUT corresponding to the same address data are respectively stored in different buffers in the page buffer, which is conducive to writing the programming data PBOUT and the check code ECCOUT together into the storage array 31 according to the same address data.

[0050] Specifically, Figure 3 As shown, the above step S10 can be exemplarily obtained by obtaining the storage data IOSA and programming data PBOUT corresponding to A1, obtaining the storage data IOSA and programming data PBOUT corresponding to A2, obtaining the storage data IOSA and programming data PBOUT corresponding to A3... obtaining the storage data IOSA and programming data PBOUT corresponding to An, etc., and generating the corresponding check code ECCOUT. The above step S20 can be exemplarily obtained by storing the check code ECCOUT to the storage space corresponding to B1, storing the check code ECCOUT to the storage space corresponding to B2... storing the check code ECCOUT to the storage space corresponding to Bn-1, storing the check code ECCOUT to the storage space corresponding to Bn, etc.

[0051] Among them, A1 is the starting address corresponding to the programming data PBOUT input by the user, and A2...An is the address data automatically carried forward based on A1. B1...Bn is the address data, which is respectively the same as A1...An, that is, B1 is equal to A1, B2 is equal to A2... and so on, Bn is equal to An.

[0052] The check code ECCOUT stored in the storage space corresponding to B1 is obtained after processing the storage data IOSA corresponding to A1 and the programming data PBOUT corresponding to A1. By analogy, the check code ECCOUT stored in the storage space corresponding to Bn is obtained after processing the storage data IOSA corresponding to An and the programming data PBOUT corresponding to An.

[0053] In some of the embodiments, based on the storage data IOSA and programming data PBOUT corresponding to the first address data AX and obtained synchronously, a corresponding check code ECCOUT is generated, including: synchronously obtaining the storage data IOSA and programming data PBOUT corresponding to the first address data AX; generating intermediate data SAP according to the logical operation result of the storage data IOSA and the programming data PBOUT; and verifying the intermediate data SAP to generate the check code ECCOUT.

[0054] It should be noted that the logic operation result can be but is not limited to an AND logic operation result. In some other embodiments, different logic operation results can also be selected according to the verification technology.

[0055] In some of the embodiments, synchronously obtaining storage data IOSA and programming data PBOUT corresponding to the first address data AX includes: outputting storage data IOSA corresponding to the first address data AX from the storage array 31 in the first time period T1 according to the first control signal RDARY; and outputting programming data PBOUT corresponding to the first address data AX from the page buffer 32 in the first time period T1 according to the second control signal RSRAM.

[0056] In some of the embodiments, storage data IOSA corresponding to the first address data AX is output from the storage array 31 in the first time period T1 according to the first control signal RDARY, including: configuring the first time period T1 as the duration of a pulse of the first control signal RDARY; and outputting the storage data IOSA corresponding to the first address data AX from the storage array 31 in response to the falling edge of the first control signal RDARY in the first time period T1.

[0057] In some of the embodiments, outputting programming data PBOUT corresponding to the first address data AX from the page buffer 32 in the first time period T1 according to the second control signal RSRAM includes: configuring the second control signal RSRAM to have at least one pulse in the first time period T1; and outputting programming data PBOUT corresponding to the first address data AX from the page buffer 32 in response to the second control signal RSRAM.

[0058] It should be noted that, in response to the second control signal RSRAM, specifically, it may be at a rising edge of the second control signal RSRAM and / or during a high level period of the second control signal RSRAM.

[0059] In some of the embodiments, intermediate data SAP is generated according to the logical operation result of the storage data IOSA and the programming data PBOUT, including: at the beginning of the second time period T2, triggering the generation of the intermediate data SAP; verifying the intermediate data SAP to generate the check code ECCOUT, including: at the end of the second time period T2, generating the check code ECCOUT.

[0060] It should be noted that the start time of the second time period T2 and the end time of the first time period T1 may be at the same time; or, in other embodiments, there may be an interval between the two.

[0061] In some of the embodiments, storing the check code ECCOUT to the storage space corresponding to the second address data BX in the page buffer 32 includes: configuring the third time period T3 after the second time period T2; in the third time period T3, in response to the pulse of the third control signal WSRAM, storing the check code ECCOUT to the storage space corresponding to the second address data BX in the page buffer 32.

[0062] In some of the embodiments, the verification code generating method further includes: configuring the first address data AX and the second address data BX to be generated in the first address counter 10 and the second address counter 20 respectively; before storing the verification code ECCOUT, updating the second address data BX in the second address counter 20 to the first address data AX; automatically carrying the first address data AX in the first address counter 10; and executing the storage data IOSA and the programming data PBOUT corresponding to the first address data AX and obtained synchronously to generate the corresponding verification code ECCOUT.

[0063] In some of the embodiments, the verification code generation method further includes: before the first verification code ECCOUT corresponding to each write instruction starts to be generated, assigning the first address data AX to the starting address data corresponding to the programming data PBOUT.

[0064] This embodiment provides a memory such as Figure 4 As shown, the memory includes a first address counter 10, a second address counter 20 and a processing module 30, the first address counter 10 is used to generate first address data AX; the second address counter 20 is used to generate second address data BX that is the same as the first address data AX before storing the check code ECCOUT; the processing module 30 is used to generate the corresponding check code ECCOUT based on the storage data IOSA and programming data PBOUT corresponding to the first address data AX and obtained synchronously, and is used to store the check code ECCOUT to the page buffer 32 corresponding to the second address data BX.

[0065] It can be understood that, in the memory provided in this embodiment, the storage data IOSA and the programming data PBOUT corresponding to the same first address data AX are obtained synchronously, and only one group of address lines for transmitting the first address data AX is needed to achieve it, and the second address data BX required for storing the check code ECCOUT only requires another group of address lines to be transmitted. Compared with three groups of address lines required to generate and store the check code ECCOUT, the number of address line groups required to generate the check code ECCOUT is further reduced.

[0066] Furthermore, compared with the storage data IOSA and programming data PBOUT corresponding to the same first address data AX, which are acquired step by step, in the pipeline generation process of n check codes ECCOUT, it takes n+2 working cycles to complete, while in the present embodiment, the storage data IOSA and programming data PBOUT corresponding to the same first address data AX are acquired synchronously, in the pipeline generation process of n check codes ECCOUT, it only takes n+1 working cycles to complete, which reduces the number of working cycles used and improves the processing efficiency of the check code ECCOUT.

[0067] It should be noted that the first address counter 10 is connected to the processing module 30 and the second address counter 20 to transmit the first address data AX to the processing module 30 and the second address counter 20 through the first group of address lines. The second address counter 20 is connected to the processing module 30 to transmit the second address data BX to the processing module 30 through the second group of address lines.

[0068] The memory may be, but is not limited to, Nor Flash, and may also be other applicable memory chips.

[0069] In some embodiments, such as Figure 5As shown, the processing module 30 includes a storage array 31, a page buffer 32, a data processing unit 33 and a check generating unit 34. The storage array 31 is used to output the storage data IOSA corresponding to the first address data AX according to the first control signal RDARY; the page buffer 32 is used to output the programming data PBOUT corresponding to the first address data AX according to the second control signal RSRAM, and to store the check code ECCOUT to the storage space corresponding to the second address data BX according to the third control signal WSRAM; the data processing unit 33 is used to generate the intermediate data SAP according to the logic operation result of the storage data IOSA and the programming data PBOUT; the check generating unit 34 is used to check the intermediate data SAP to generate the corresponding check code ECCOUT.

[0070] It should be noted that the first address counter 10 is connected to the storage array 31 and the page buffer 32 to transmit the first address data AX to the storage array 31 and the page buffer 32 through the first group of address lines, so that the storage array 31 and the page buffer 32 can synchronously output the corresponding storage data IOSA and programming data PBOUT according to the first address data AX. The page buffer 32 is connected to the second address counter 20 and the check generating unit 34 to transmit the second address data BX to the page buffer 32 through the second group of address lines, so that the page buffer 32 can store the corresponding check code ECCOUT to the storage space corresponding to the second address data BX. The data processing unit 33 is connected to the storage array 31 and the page buffer 32 to perform an AND logic operation on the received storage data IOSA and the programming data PBOUT. The check generating unit 34 is connected to the data processing unit 33 to check the received intermediate data SAP.

[0071] Figure 6 A timing diagram of the memory provided in the embodiment of the present application. The multiple time periods of its pipeline operation are as follows:

[0072] First period T1: Initialize the first address data AX as the starting address data, which is the starting storage address corresponding to the programming data PBOUT under each write instruction. When the falling edge of the first control signal RDARY arrives and the second control signal RSRAM is at a high level or during the pulse duration, control the storage array 31 and the page buffer 32 to synchronously output the corresponding first storage data IOSA and the first programming data PBOUT.

[0073] Second period T2: Perform an AND logic operation on the first storage data IOSA and the first programming data PBOUT to generate the first intermediate data SAP, and verify the first intermediate data SAP to generate the corresponding first verification code ECCOUT. At the end of the second period T2, the first address data AX of the first address counter 10 is latched in the second address counter 20, and the first address data AX in the first address counter 10 is automatically carried.

[0074] Third period T3: When the third control signal WSRAM is at a high level, the first check code ECCOUT is stored in the page buffer 32 corresponding to the second address data BX. At the same time, the storage array 31 and the page buffer 32 are controlled to synchronously output the corresponding second storage data IOSA and the second programming data PBOUT.

[0075] Fourth period T4: Perform an AND logic operation on the second storage data IOSA and the second programming data PBOUT to generate the second intermediate data SAP, and verify the second intermediate data SAP to generate the corresponding second verification code ECCOUT. At the end of the fourth period T4, the first address data AX of the first address counter 10 is latched in the second address counter 20, and the first address data AX in the first address counter 10 is automatically carried.

[0076] Fifth period T5: When the third control signal WSRAM is at a high level, the second check code ECCOUT is stored in the page buffer 32 corresponding to the second address data BX. At the same time, the memory array 31 and the page buffer 32 are controlled to synchronously output the corresponding third storage data IOSA and third programming data PBOUT.

[0077] This cycle is repeated until all programming data PBOUT corresponding to a write instruction are processed completely. The process of generating the check code ECCOUT for all programming data PBOUT corresponding to the next write instruction can be restarted from the first period T1.

[0078] In some embodiments, taking the first transmission bandwidth from the storage array 31 to the data processing unit 33 and the second transmission bandwidth from the page buffer 32 to the data processing unit 33 as 128 bits and 32 bits respectively, the number of pulses of the second control signal RSRAM in the first period T1, the third period T3, and the fifth period T5 should be 4 times the number of pulses of the first control signal RDARY. If the first transmission bandwidth is the same as the second transmission bandwidth, the number of pulses of the second control signal RSRAM is equal to the number of pulses of the first control signal RDARY in the first period T1, the third period T3, and the fifth period T5.

[0079] Similarly, the number of pulses of the third control signal WSRAM in each time period is determined by the number of IO ports for writing the check code ECCOUT of the page buffer 32. Taking the check code ECCOUT as 8 bits as an example, if the number of IO ports for writing the check code ECCOUT is 2, the third control signal WSRAM needs four pulses to write one check code ECCOUT; if the number of IO ports for writing the check code ECCOUT is 4, the third control signal WSRAM needs two pulses to write one check code ECCOUT.

[0080] The check code ECCOUT may be, but is not limited to, generated by an error checking and correction (ECC) technology, and may also be generated by other check technologies.

[0081] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0082] The above is a detailed introduction to the verification code generation method and memory provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for generating a verification code, characterized in that: The verification code generation method comprises: Generate a corresponding verification code based on the storage data and programming data corresponding to the first address data and obtained synchronously; The check code is stored in a storage space corresponding to the second address data in the page buffer, wherein before the check code is stored, the second address data is the same as the first address data.

2. The method for generating a verification code according to claim 1, characterized in that: The step of generating a corresponding verification code based on the storage data and programming data corresponding to the first address data and obtained synchronously includes: Synchronously acquiring storage data and programming data corresponding to the first address data; Generate intermediate data according to the result of logic operation between the stored data and the programmed data; The intermediate data is verified to generate a verification code.

3. The method for generating a check code according to claim 2, characterized in that: The synchronously acquiring the storage data and programming data corresponding to the first address data includes: outputting storage data corresponding to the first address data from the storage array in a first time period according to the first control signal; Program data corresponding to the first address data is output from the page buffer in a first period according to the second control signal.

4. The method for generating a check code according to claim 3, characterized in that: The step of outputting storage data corresponding to the first address data from the storage array in a first time period according to the first control signal includes: Configure the first time period as the duration of a pulse of the first control signal; In response to a falling edge of the first control signal in the first period, storage data corresponding to the first address data is output from the storage array.

5. The method for generating a check code according to claim 4, characterized in that: Outputting programming data corresponding to the first address data from the page buffer in the first period according to the second control signal includes: configuring the second control signal to have at least one pulse in the first time period; In response to the second control signal, program data corresponding to the first address data is output from the page buffer.

6. The method for generating a check code according to claim 3, characterized in that: The generating of intermediate data according to the logical operation result of the storage data and the programming data comprises: At the beginning of the second period, generating intermediate data; Verify the intermediate data to generate a verification code, including: At the end of the second period, a verification code is generated.

7. The method for generating a check code according to claim 6, characterized in that: The storing of the check code to the storage space corresponding to the second address data in the page buffer includes: Configure the third period after the second period; In a third period, in response to a pulse of a third control signal, a check code is stored in a storage space corresponding to the second address data in the page buffer.

8. A verification code generation method according to any one of claims 1 to 7, characterized in that: The verification code generation method further comprises: Configure the first address data and the second address data to be generated in the first address counter and the second address counter respectively; Before storing the check code, updating the second address data in the second address counter to the first address data; Automatically carry the first address data in the first address counter; Execute storage data and programming data corresponding to the first address data and obtained synchronously to generate corresponding verification codes.

9. The method for generating a check code according to claim 8, characterized in that: The verification code generation method further comprises: Before the first check code corresponding to each write instruction starts to be generated, the first address data is assigned as the starting address data corresponding to the programming data.

10. A memory, characterized in that: The memory comprises: a first address counter, wherein the first address counter is used to generate first address data; a second address counter, the second address counter being used to generate second address data identical to the first address data before storing the check code; A processing module is used to generate a corresponding check code based on the storage data and programming data corresponding to the first address data and obtained synchronously, and to store the check code in a page buffer corresponding to the second address data.

11. The memory according to claim 10, characterized in that The processing module comprises: A storage array, the storage array is used to output storage data corresponding to the first address data according to the first control signal; A page buffer, the page buffer is used to output programming data corresponding to the first address data according to the second control signal, and store the check code to the storage space corresponding to the second address data according to the third control signal; A data processing unit, the data processing unit is used to generate intermediate data according to the result of logic operation between the storage data and the programming data; The check generating unit is used to check the intermediate data to generate a corresponding check code.

12. A method for generating a verification code, characterized in that: The verification code generation method comprises: Generate a corresponding verification code based on the storage data and programming data corresponding to the different address data acquired synchronously; The verification code is stored in a corresponding storage space in the page buffer.

13. The verification code generation method according to claim 12, characterized in that: The generating corresponding verification codes based on the storage data and programming data corresponding to different address data obtained synchronously includes: In the n-1th cycle, the storage data corresponding to the n-1th address data and the programming data corresponding to the n-2th address data are synchronously acquired; In the nth cycle, the storage data corresponding to the nth address data and the programming data corresponding to the n-1th address data are synchronously acquired; The verification code is obtained according to a logic operation result of the storage data corresponding to the n-1th address data and the programming data corresponding to the n-1th address data.

14. The method for generating a check code according to claim 13, characterized in that: The storing the check code to a corresponding storage space in the page buffer includes: In the (n+1)th cycle, the check code is stored in the storage space corresponding to the (n-1)th address data in the page buffer.

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