Chip verification method, device, server and storage medium

Abstract

The embodiment of the present application provides a chip verification method, device, server and storage medium, which are applied to a first CPU core. The method includes: obtaining a simulation task for chip verification, the simulation task includes multiple subtasks; assigning an idle second CPU core to each subtask, and creating an underlying communication space for multiple subtasks; sending multiple subtasks to the corresponding second CPU core, so that each second CPU core executes the corresponding subtask, and using the underlying communication space to interact with other second CPU cores to generate data during the execution of the subtask. This solution can reduce the cost of chip verification while improving the efficiency of chip verification.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a chip verification method, device, server and storage medium. Background Art

[0002] Before the chip is taped out for production, it is necessary to use a dedicated processor such as a server or a field programmable gate array (FPGA) or emulation accelerator to verify the chip to ensure that the chip's functions meet the EDA design requirements and to ensure the quality of the chip.

[0003] However, with the rapid development of artificial intelligence (AI), the demand for data centers has gradually increased, and the scale of single chips, chiplets, and chip networks used in data centers has expanded rapidly. Using a server to verify a chip actually means that a central processing unit (CPU) core in the server performs chip verification. As the scale of single chips, chiplets, and chip networks increases, a single CPU core performs chip verification, and the verification efficiency is low. Using a dedicated processor to verify large-scale single chips, chiplets, or chip networks has a higher verification efficiency, but the verification cost is also high. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a chip verification method, device, server and storage medium to improve chip verification efficiency and reduce chip verification costs. The specific technical solution is as follows:

[0005] In a first aspect, an embodiment of the present application provides a chip verification method, which is applied to a first CPU core, and the method includes:

[0006] Acquire a simulation task for chip verification, wherein the simulation task includes multiple subtasks;

[0007] Allocate an idle second CPU core to each subtask respectively, and create an underlying communication space for the multiple subtasks;

[0008] The multiple subtasks are sent to corresponding second CPU cores, so that each second CPU core executes the corresponding subtask, and the underlying communication space is used to interact with other second CPU cores to generate data during the execution of the subtasks.

[0009] In some embodiments, the method further comprises:

[0010] Continuously obtain the simulation time of multiple second CPU cores;

[0011] When the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to the first preset duration, instructing the third CPU core to suspend execution of the subtask; the third CPU core is any second CPU core among the multiple second CPU cores, and the fourth CPU core is the second CPU core with the slowest simulation time among the multiple second CPU cores;

[0012] When the difference between the simulation time of the third CPU core and the simulation time of the fourth CPU core is less than or equal to a second preset duration, the third CPU core is instructed to resume executing the subtask.

[0013] In some embodiments, when the difference between the simulation time of the third CPU core and the simulation time of the fourth CPU core is greater than or equal to the first preset duration, the step of instructing the third CPU core to suspend execution of the subtask includes:

[0014] When the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to the first preset duration, and the simulation time of the third CPU core reaches one simulation cycle, the third CPU core is instructed to suspend execution of the subtask.

[0015] In some embodiments, the second preset duration is zero;

[0016] The step of instructing the third CPU core to resume executing the subtask when the difference between the simulation time of the third CPU core and the fourth CPU core is less than or equal to the second preset duration includes:

[0017] When the simulation time of the fourth CPU core reaches one simulation cycle, the third CPU core is instructed to resume executing the subtask.

[0018] In some embodiments, the step of creating an underlying communication space for the plurality of subtasks includes:

[0019] Determine, according to the topological structure of the multiple subtasks, two second CPU cores with which data interaction exists;

[0020] An underlying communication space is created for the two second CPU cores.

[0021] In some embodiments, the method further comprises:

[0022] Detect each second CPU core to obtain the execution status of the subtask in each second CPU core;

[0023] The subtasks in each CPU core are subjected to post-processing corresponding to the execution status.

[0024] In some embodiments, the underlying communication space is a shared file, a shared memory, or a Unix domain socket.

[0025] In some embodiments, the first CPU core and the plurality of second CPU cores are located on the same server.

[0026] In a second aspect, an embodiment of the present application provides a chip verification device, which is applied to a first CPU core, and the device includes:

[0027] A first acquisition module is used to acquire a simulation task for chip verification, wherein the simulation task includes multiple subtasks;

[0028] An allocation module, used for respectively allocating an idle second CPU core to each subtask and creating an underlying communication space for the multiple subtasks;

[0029] The sending module is used to send the multiple subtasks to the corresponding second CPU cores so that each second CPU core executes the corresponding subtask, and uses the underlying communication space to interact with other second CPU cores to exchange data generated during the execution of the subtasks.

[0030] In some embodiments, the apparatus further comprises:

[0031] A second acquisition module, used for continuously acquiring simulation time of multiple second CPU cores;

[0032] An indication module is used to instruct the third CPU core to suspend execution of a subtask when the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to a first preset duration; the third CPU core is any second CPU core among the multiple second CPU cores, and the fourth CPU core is the second CPU core with the slowest simulation time among the multiple second CPU cores; when the difference between the simulation time of the third CPU core and the fourth CPU core is less than or equal to a second preset duration, instruct the third CPU core to resume execution of the subtask.

[0033] In some embodiments, the indication module is specifically used to:

[0034] When the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to the first preset duration, and the simulation time of the third CPU core reaches one simulation cycle, the third CPU core is instructed to suspend execution of the subtask.

[0035] In some embodiments, the second preset duration is zero;

[0036] The instructing module is specifically used to instruct the third CPU core to resume executing the subtask when the simulation time of the fourth CPU core reaches one simulation cycle.

[0037] In some embodiments, the allocation module is specifically used to:

[0038] Determine, according to the topological structure of the multiple subtasks, two second CPU cores with which data interaction exists;

[0039] An underlying communication space is created for the two second CPU cores.

[0040] In some embodiments, the apparatus further comprises:

[0041] A detection module, used to detect each second CPU core to obtain the execution status of the subtask in each second CPU core;

[0042] The processing module is used to perform post-processing corresponding to the execution status on the subtasks in each CPU core.

[0043] In some embodiments, the underlying communication space is a shared file, a shared memory, or a Unix domain socket.

[0044] In some embodiments, the first CPU core and the plurality of second CPU cores are located on the same server.

[0045] In a third aspect, an embodiment of the present application provides a server, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0046] Memory, used to store computer programs;

[0047] The processor is used to implement any of the above methods when executing the program stored in the memory.

[0048] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, any of the above-described methods is implemented.

[0049] In a fifth aspect, an embodiment of the present application further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any of the methods described above.

[0050] Beneficial effects of the embodiments of the present application:

[0051] In the technical solution provided in the embodiment of the present application, the first CPU core splits a chip verification simulation task into multiple subtasks; and allocates an idle second CPU core to each subtask, and each second CPU core executes the subtask respectively, so that multiple second CPU cores execute the subtasks in parallel to complete the simulation task, thereby improving the chip verification efficiency. In addition, in the embodiment of the present application, it is completed by the CPU core on the server, without the need to use an expensive dedicated processor, thereby reducing the cost of chip verification.

[0052] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0054] Figure 1 A schematic diagram of a chip verification scenario;

[0055] Figure 2 A schematic diagram of a process flow of a chip verification method provided in an embodiment of the present application;

[0056] Figure 3 A schematic diagram of creating a shared file provided in an embodiment of the present application;

[0057] Figure 4 A schematic diagram of a first flow chart of a time synchronization method provided in an embodiment of the present application;

[0058] Figure 5 A second flow chart of the time synchronization method provided in the embodiment of the present application;

[0059] Figure 6 A schematic diagram of time synchronization during the execution of a simulation task provided in an embodiment of the present application;

[0060] Figure 7 A schematic diagram of a chipset network provided in an embodiment of the present application;

[0061] Figure 8 A schematic diagram of the topological structure of subtasks provided in an embodiment of the present application;

[0062] Fig. 9 A schematic diagram of an abstract model of the topological structure of a chipset network provided in an embodiment of the present application;

[0063] Fig.10A schematic diagram of the first structure of a chip verification device provided in an embodiment of the present application;

[0064] Fig.11 A second structural diagram of a chip verification device provided in an embodiment of the present application;

[0065] Fig.12 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0066] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0067] Verification Intellectual Property (VIP): A set of pre-packaged codes used for chip verification.

[0068] The current chip verification method is based on Electronic Design Automation (EDA) tools, which mainly include the following two methods:

[0069] Method 1: Use a server to verify the chip.

[0070] like Figure 1 In the chip verification scenario shown, the user writes a simulation task for chip verification on the client, and the client submits the simulation task to the management server in the Load Sharing Facility (LSF) cluster. The management server can send the simulation task to an execution server in the LSF cluster in a load balancing manner. The execution server includes multiple CPU cores. The execution server assigns the simulation task to an idle CPU core. The CPU core uses EDA tools to build multiple threads that match the simulation task to simulate the circuit design of the chip or chip network. The computing resources between multiple threads coordinate work to complete chip verification. The execution server is a server that executes the simulation task, and the management server is a server that manages the execution server.

[0071] In this method, a single CPU core executes a simulation task. However, with the rapid development of AI technology, the scale of single chips, chiplets, and chipset networks has expanded rapidly, and the corresponding simulation task data volume size has increased rapidly. When a single CPU core executes a large-scale chipset verification (LCV) simulation task, the CPU core will be overloaded, the CPU core will run slowly, the chip verification efficiency will be low, and even the chip verification will fail.

[0072] Method 2: Use a dedicated processor to perform chip verification.

[0073] The user writes the simulation task of chip verification on the client, and the client submits the simulation task to a dedicated processor such as FPGA or simulation accelerator. The dedicated processor uses EDA tools to build multiple threads that match the simulation task to simulate the circuit design of the chip or chip network. The computing resources between multiple threads coordinate work to complete chip verification.

[0074] Dedicated processors can meet the computing resource requirements of LCV simulation tasks, and the chip verification efficiency is high. However, the cost of dedicated processors is high, and in order to meet the computing resource requirements of simulation tasks with larger data volumes, the cost of dedicated processors will be even higher.

[0075] To solve the above problems, while improving chip verification efficiency and reducing chip verification costs, the present application embodiment provides a chip verification method, such as Figure 2 As shown, applied to the first CPU core, the method includes the following steps:

[0076] Step S201, obtaining a simulation task for chip verification, where the simulation task includes multiple subtasks;

[0077] Step S202, allocating an idle second CPU core to each subtask, and creating an underlying communication space for the multiple subtasks;

[0078] Step S203, sending the multiple subtasks to the corresponding second CPU cores, so that each second CPU core executes the corresponding subtask, and uses the underlying communication space to interact with other second CPU cores to obtain data generated during the execution of the subtasks.

[0079] In the technical solution provided in the embodiment of the present application, the first CPU core splits a chip verification simulation task into multiple subtasks; and allocates an idle second CPU core to each subtask, and each second CPU core executes the subtask respectively, so that multiple second CPU cores execute the subtasks in parallel to complete the simulation task, thereby improving the chip verification efficiency. In addition, in the embodiment of the present application, it is completed by the CPU core on the server, without the need to use an expensive dedicated processor, thereby reducing the cost of chip verification.

[0080] The technical solution provided by the embodiment of the present application supports the verification of large-scale chip networking with a second number of CPU cores. For example, if the server has 144 CPU cores, theoretically, the embodiment of the present application can realize the networking verification of 144 chips.

[0081] In the embodiment of the present application, the first CPU core may be any CPU core in any server (such as the execution server) in the LSF cluster. The first CPU core is responsible for controlling and detecting each CPU core (such as the second CPU core) executing the current simulation task.

[0082] In the above step S201, the simulation task may be a simulation task for a single chip, or a simulation task for a large-scale chipset network. A simulation task includes multiple subtasks, and a subtask forms a simulation test bench (Sim TB) when running in the CPU core. When the simulation task is a simulation task for a single chip, the single chip is the object to be tested, and a subtask is a part of the logic circuit that can be independently run in the single chip. When the simulation task is a simulation task for a large-scale chipset network, the chipset network is the object to be tested, and a subtask can be a part of the logic circuit that can be independently run in the single chip, or it can be the overall logic circuit of a chip in the chipset network.

[0083] The user writes a simulation task for chip verification on the client, and the client submits the simulation task to the management server in the LSF cluster. The management server can send the simulation task to an execution server in the LSF cluster in a load balancing manner, and then a CPU core (such as the first CPU core) on the execution server obtains the simulation task.

[0084] In the above step S202, the first CPU core can select multiple CPU cores (such as the second CPU core) from the idle CPU cores, and assign the selected second CPU cores to each subtask. One subtask corresponds to one second CPU core. The second CPU core is assigned to a subtask, which means that the second CPU core executes the subtask.

[0085] In the embodiment of the present application, the first CPU core and the plurality of second CPU cores may be located on the same server (such as the above-mentioned execution server). In this way, it is convenient for the first CPU core to control and detect the plurality of second CPU cores. In addition, when the plurality of second CPU cores are located on the same server and the plurality of second CPU cores perform subtask interaction, the data transmission and reception delay of the second CPU core interaction can be greatly reduced, thereby solving the problem of data transmission instability caused by the large transmission and reception delay and obtaining stable data acquisition.

[0086] In the embodiment of the present application, the first CPU core and the plurality of second CPU cores may also be located on a plurality of servers, that is, the plurality of second CPU cores may be located on a plurality of servers. In order to solve the problem of unstable data transmission caused by large transmission and reception delay and obtain stable data acquisition, the data transmission bandwidth between the plurality of servers is greater than or equal to the bandwidth required for data exchange between the second CPU cores.

[0087] When allocating a second CPU core to a subtask, the first CPU core creates an underlying communication space for multiple subtasks. The underlying communication space is a medium for data generated during the execution of multiple second CPU core interactive subtasks. In an embodiment of the present application, the underlying communication space can be a shared file, a shared memory, or a Unix domain socket. One or more underlying communication spaces can be established between two second CPU cores, and the underlying communication spaces between different second CPU cores can be the same or different.

[0088] In some embodiments, the first CPU core can obtain the topological structure of multiple subtasks; determine two second CPU cores with data interaction based on the topological structure of the multiple subtasks; and create an underlying communication space for the two second CPU cores. Through the topological structure of the multiple subtasks, the first CPU core can accurately know the two second CPU cores for which the underlying communication space needs to be established, and establish the corresponding underlying communication space.

[0089] In the embodiment of the present application, the user may also input two second CPU cores that need to establish the underlying communication space through the user interaction interface; the first CPU core obtains the information for establishing the underlying communication space input by the user through the user interface, and then establishes the corresponding underlying communication space. The first CPU core may also establish the underlying communication space in other ways, which are not limited.

[0090] Communication based on the server's local underlying communication space can avoid the large delay caused by transmitting data in the Local Area Network (LAN), greatly reduce the data transmission and reception delay between the second CPU cores, and thus solve the problem of unstable data transmission caused by large transmission and reception delay.

[0091] In the above step S203, the first CPU core sends multiple subtasks to the corresponding second CPU core. After receiving the subtasks, the second CPU core can create a process and call the process to execute the received subtasks. The execution of subtasks by multiple second CPU cores is independent of each other, which enables multiple second CPU cores to execute subtasks in parallel, thereby giving full play to the maximum efficiency of parallel computing of multiple CPU core resources in the server, thereby improving the chip verification efficiency at the system level and network level.

[0092] In the process of executing the subtask, the second CPU core can write the generated data into the underlying communication space through the process, and read the required data from the underlying communication space. Correspondingly, other second CPU cores can read the data written by the second CPU core from the underlying communication space; and write the data generated in the process of executing the subtask and required by the second CPU core into the underlying communication space.

[0093] For example, the simulation task includes subtask 1 to subtask 3. Subtask 1 is assigned to CPU core 1, subtask 2 is assigned to CPU core 2, and subtask 3 is assigned to CPU core 3. CPU core 1 executes subtask 1 to form a simulation test platform Sim TB1, CPU core 2 executes subtask 2 to form a simulation test platform Sim TB2, and CPU core 3 executes subtask 3 to form a simulation test platform Sim TB3. Figure 3 As shown. Data needs to be exchanged between CPU core 1 and CPU core 2, and data needs to be exchanged between CPU core 2 and CPU core 3, that is, data needs to be exchanged between SimTB1 and SimTB2, and data needs to be exchanged between SimTB2 and SimTB3, and then shared files 1 and 2 are established between CPU core 1 and CPU core 2, and shared files 3 and 4 are established between CPU core 2 and CPU core 3, as shown. Figure 3 shown.

[0094] Sim TB1 writes the data generated during the execution of subtask 1 into shared file 1; Sim TB2 reads the data written by Sim TB1 from shared file 1; Sim TB2 writes the data generated during the execution of subtask 2 into shared file 2 and shared file 3; Sim TB1 reads the data written by Sim TB2 from shared file 2; Sim TB3 reads the data written by Sim TB12 from shared file 3; Sim TB3 writes the data generated during the execution of subtask 3 into shared file 4; SimTB2 reads the data written by Sim TB3 from shared file 4.

[0095] In an embodiment of the present application, while creating the underlying communication space, if multiple second CPU cores and the first CPU core are located on the same server, the problem of unstable data transmission caused by large transmission and reception delays can be further solved, the resource utilization of multiple CPU cores of the server can be maximized, the EDA verification performance of the LSF cluster can be fully utilized, the simulation efficiency of EDA verification can be improved, and the verification cost of large-scale chipset networking can be reduced as a whole.

[0096] In some embodiments, in order to reduce delay jitter and ensure long-term stability of data delay, the embodiment of the present application also provides a time synchronization method, such as Figure 4 As shown, applied to the first CPU core, the following steps may be included;

[0097] Step S401, continuously obtaining simulation time of multiple second CPU cores;

[0098] In the embodiment of the present application, the simulation time is the time within a simulation cycle. For example, the duration of a simulation cycle is 100 picoseconds (ps), and the simulation time can be any value between 0ps and 100ps.

[0099] During the process of the plurality of second CPU cores executing the subtasks, each second CPU core may periodically send the simulation time to the first CPU core. The first CPU core continuously obtains the simulation time of the plurality of second CPU cores.

[0100] To facilitate the first CPU core to obtain the simulation time of each second CPU core, an underlying communication space is established between the first CPU core and multiple second CPU cores. In this way, each second CPU core can periodically write the simulation time of the second CPU core into the underlying communication space; and the first CPU core can periodically read the simulation time of each second CPU core from the underlying communication space. The underlying communication space for writing simulation time can be the same or different for different second CPU cores.

[0101] Step S402, when the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to the first preset time, instruct the third CPU core to suspend execution of the subtask; the third CPU core is any second CPU core among the plurality of second CPU cores, and the fourth CPU core is the second CPU core with the slowest simulation time among the plurality of second CPU cores;

[0102] Due to the differences in the performance of the CPU cores themselves and the differences in the data body sizes of the subtasks executed by the CPU cores, different CPU cores have different efficiencies in processing subtasks. That is, under the same system time (CPU running time), some second CPU cores execute subtasks faster, while some second CPU cores execute subtasks slower. Accordingly, there are differences in the simulation times of different second CPU cores, resulting in different simulation times.

[0103] After the first CPU core obtains the simulation time of multiple second CPU cores each time, it determines the second CPU core with the slowest simulation time from the multiple second CPU cores as the fourth CPU core, and compares the simulation time of other second CPU cores (such as the third CPU core) with the simulation time of the fourth CPU core.

[0104] If the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to the first preset time, it means that the simulation time of the third CPU core is not synchronized with the simulation time of the fourth CPU core, and the first CPU core can instruct the third CPU core to suspend the execution of the subtask to avoid the problem of unstable data transmission between CPU cores caused by the asynchronization of the simulation time. For example, the first CPU core writes a first control signal indicating the suspension to the underlying communication space, and the third CPU core reads the first control signal from the underlying communication space, and then suspends the execution of the subtask according to the first control signal.

[0105] If the difference between the simulation time of the third CPU core and the fourth CPU core is less than the first preset duration, it means that the simulation time of the third CPU core is synchronized with the simulation time of the fourth CPU core, and the first CPU core can perform no processing on the third CPU core, that is, the third CPU core can continue to execute the subtask.

[0106] Step S403: when the difference between the simulation time of the third CPU core and the simulation time of the fourth CPU core is less than or equal to the second preset duration, instruct the third CPU core to resume executing the subtask.

[0107] In the embodiment of the present application, the second preset duration may be less than or equal to the first preset duration.

[0108] While the third CPU core suspends the execution of the subtask, the fourth CPU core continues to execute the subtask, and the difference in simulation time between the third CPU core and the fourth CPU core gradually decreases. During this period, the first CPU core continuously obtains the simulation time of the fourth CPU core, and compares the obtained simulation time of the fourth CPU core with the simulation time when the third CPU core suspends the execution of the subtask. When the difference in simulation time between the third CPU core and the fourth CPU core is less than or equal to the second preset duration, it means that the simulation time of the third CPU core has been synchronized with the simulation time of the fourth CPU core, and the first CPU core instructs the third CPU core to resume the execution of the subtask. For example, the first CPU core writes a second control signal indicating resumption to the underlying communication space, and the third CPU core reads the second control signal from the underlying communication space, and then resumes the execution of the subtask according to the second control signal.

[0109] If the difference between the simulation time of the third CPU core and the fourth CPU core is greater than the second preset duration, the first CPU core may not perform any processing on the third CPU core, that is, the third CPU core may continue to suspend the execution of the subtask.

[0110] In order to avoid frequently pausing the third CPU core to execute subtasks, which affects the smoothness of task execution, the second preset duration is less than the first preset duration, and the difference between the first preset duration and the second preset duration is greater than or equal to the preset difference. The preset difference can be set according to actual needs. The preset difference can ensure that the third CPU core will not be suspended from executing subtasks again within a certain period of time.

[0111] In the embodiment of the present application, the first CPU core compares the simulation time of the two CPU cores, and pauses the faster simulating CPU core to execute subtasks, thereby achieving time synchronization between the two CPU cores. Even if the CPU cores simulate for a long time and execute subtasks, the delay jitter of the simulation time of the two CPU cores is controlled within the first preset time length, effectively solving the problem of large delay jitter and unstable data transmission caused by long-term simulation. The technical solution provided by the embodiment of the present application is suitable for chipset verification scenarios with high requirements for system time synchronization.

[0112] In some embodiments, the above step S403 may be: when the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to the first preset duration, and the simulation time of the third CPU core reaches a simulation cycle, instructing the third CPU core to suspend execution of the subtask.

[0113] In the embodiment of the present application, the first CPU core may instruct the third CPU core to suspend execution of the subtask in any of the following ways.

[0114] Method 1: After the first CPU core obtains the simulation time of multiple second CPU cores each time, it compares the simulation time of the third CPU core with the simulation time of the fourth CPU core. If the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to the first preset duration, the first CPU core will not immediately instruct the third CPU core to suspend the execution of the subtask. The third CPU core continues to execute the subtask. When the simulation time of the third CPU core obtained by the first CPU core reaches a simulation cycle, the first CPU core again instructs the third CPU core to suspend the execution of the subtask.

[0115] Method 2: The first CPU core obtains the simulation time of multiple second CPU cores each time to determine whether there is a second CPU core that has reached a simulation cycle; if so, the second CPU core that has reached a simulation cycle is the third CPU core; the first CPU core compares the simulation time of the third CPU core with the simulation time of the fourth CPU core. If the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to the first preset time, the first CPU core immediately instructs the third CPU core to suspend the execution of the subtask.

[0116] In the embodiment of the present application, the first CPU core performs a time synchronization operation only once at a specified time (the time when the simulation cycle is reached), that is, the above step S403. This can simplify the complexity of the time synchronization operation, and can also control the time synchronization at the simulation cycle level. The performance difference between CPU cores is relatively small, and the cycle-level time synchronization can be sufficient to ensure the stability of the buffer waterline of the underlying communication space.

[0117] In some embodiments, in order to maximize the time synchronization between CPU cores and reduce the frequency of executing synchronization operations, the second preset duration may be zero. In this case, the embodiment of the present application further provides a time synchronization method, such as Figure 5 As shown, applied to the first CPU core, the following steps may be included.

[0118] Step S501, continuously obtaining the simulation time of multiple second CPU cores; the same as the above step S401, which will not be repeated here.

[0119] Step S502, when the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to the first preset time length, and the simulation time of the third CPU core reaches a simulation cycle, instruct the third CPU core to suspend the execution of the subtask; the third CPU core is any second CPU core among the multiple second CPU cores, and the fourth CPU core is the second CPU core with the slowest simulation time among the multiple second CPU cores; for details, please refer to the relevant description of the above step S402, which will not be repeated here.

[0120] Step S503: When the simulation time of the fourth CPU core reaches one simulation cycle, instruct the third CPU core to resume executing the subtask.

[0121] In the embodiment of the present application, when the third CPU core suspends the execution of the subtask, the simulation time of the third CPU core reaches one simulation cycle. After the third CPU core suspends the execution of the subtask, the fourth CPU core continues to execute the subtask, and the simulation time of the fourth CPU core continues to increase. Correspondingly, the difference between the simulation time of the fourth CPU core and the third CPU core continues to decrease. When the simulation time of the fourth CPU core reaches one simulation cycle, the difference between the simulation time of the fourth CPU core and the third CPU core is 0, and then the first CPU core instructs the third CPU core to resume the execution of the subtask.

[0122] In an embodiment of the present application, the first CPU core performs a time synchronization operation only once at a specified time (the time when the simulation cycle is reached), that is, the above-mentioned step S403. This can simplify the complexity of the time synchronization operation, and at the same time, the time synchronization can be controlled at the simulation cycle level. The performance difference between CPU cores is relatively small, and the cycle-level time synchronization can be sufficient to ensure the stability of the buffer waterline of the underlying communication space. In addition, when the difference in simulation time between the fourth CPU core and the third CPU core is 0, that is, when the difference in simulation time between the fourth CPU core and the third CPU core is the smallest, the third CPU core resumes executing the subtask, which maximizes the time synchronization between the CPU cores and prolongs the duration of the difference in simulation time between the fourth CPU core and the third CPU core after the synchronization operation, thereby reducing the frequency of executing the synchronization operation.

[0123] For example, the simulation task includes subtask 1 to subtask 3. Subtask 1 is assigned to CPU core 1 (i.e., the second CPU core), subtask 2 is assigned to CPU core 2 (i.e., the second CPU core), and subtask 3 is assigned to CPU core 3 (i.e., the second CPU core). CPU core 1 executes subtask 1 to form a simulation test platform Sim TB1, CPU core 2 executes subtask 2 to form a simulation test platform Sim TB2, and CPU core 3 executes subtask 3 to form a simulation test platform Sim TB3. Figure 6 As shown. CPU core 0 executes the time synchronization task and acts as the time synchronization manager. CPU cores 1 to 3 have different efficiencies in processing subtasks. The processing efficiency of CPU core 2 is greater than that of CPU core 3, and the processing efficiency of CPU core 3 is greater than that of CPU core 1. Accordingly, the simulation duration of a simulation cycle of CPU cores 1 to 3 is the same, but the CPU running time consumed is different. Figure 6In the example, a high level and a low level constitute a simulation cycle. For example, a simulation cycle of 100ps, a first preset duration of 0, and a second preset duration of 0. t0~t3 are the CPU running time.

[0124] CPU core 1 to CPU core 3 start to execute subtasks from time t0. During the process of CPU core 1 to CPU core 3 executing subtasks, CPU core 1 to CPU core 3 can send simulation time to CPU core 0 every certain simulation time (such as 10ps). At time t1, CPU core 0 obtains the simulation time of CPU core 2 as 100ps, while the simulation time of CPU core 1 and the simulation time of CPU core 3 do not reach 100ps, then CPU core 0 instructs CPU core 2 to suspend the execution of subtask 2; at time t2, CPU core 0 obtains the simulation time of CPU core 3 as 100ps, while the simulation time of CPU core 3 does not reach 100ps, then CPU core 0 instructs CPU core 3 to suspend the execution of subtask 3; at time t3, CPU core 0 obtains the simulation time of CPU core 1 as 100ps, and CPU core 1 is the CPU core with the slowest simulation time. At this time, CPU core 0 instructs CPU core 2 to resume the execution of subtask 2 and instructs CPU core 3 to resume the execution of subtask 3. The same is true for the rest, and no further description is given.

[0125] By adopting the technical solution provided in the embodiment of the present application, for the same simulation cycle but inconsistent CPU running time, the execution of subtasks in each CPU core can be dynamically adjusted to ensure that subtasks in all CPU cores can jump consistently under the same clock, thereby achieving system time synchronization.

[0126] In some embodiments, in order to improve the accuracy and flexibility of the chip verification process, the first CPU core can monitor multiple second CPU cores, which can specifically include: detecting each second CPU core to obtain the execution status of the subtasks in each second CPU core; performing post-processing corresponding to the execution status of the subtasks in each CPU core.

[0127] The execution status may include but is not limited to execution exception, exception reason, operation required parameters, execution end, etc. The post-processing varies according to the execution status.

[0128] For example, the second CPU core sends information indicating execution abnormality to the first CPU core, and the first CPU core generates abnormal prompt information and inputs the abnormal prompt information so that the user can locate the cause of the abnormality in time and improve chip quality.

[0129] For another example, the first CPU core detects that the subtask executed by the second CPU core needs to increase the required operation parameters, the first CPU core obtains the required operation parameters, and writes the required operation parameters into the subtask executed by the second CPU core to ensure the execution of the subtask.

[0130] By monitoring the second CPU core, the first CPU core can adjust the chip verification process in time according to actual needs, thereby improving the flexibility of chip verification.

[0131] Combine the following Figure 7 The chipset network shown is used to describe in detail the chip verification method provided in the embodiment of the present application. Figure 7 The chipset network shown includes 22 chips, including 6 switch cards and 16 line cards. The 16 line cards are divided into 8 groups, and each line card is connected to an AI card. The AI ​​card can communicate with the switch card through the line card. The underlying communication space is used as a shared file as an example.

[0132] for Figure 7 The topology of the chipset network shown in FIG. 1 and the topology of the subtasks corresponding to the topology are shown in FIG. Figure 8 As shown. Verification environment (ENV) 1-1~ENV1-6 corresponds to 6 switch cards, and ENV2-1~ENV2-16 corresponds to 16 line cards. ENV1-1~ENV1-6, ENV2-1~ENV2-16 are respectively Figure 7 The subtasks of chipset network verification are shown. Each AI card is abstracted as a VIP.

[0133] CPU core 0 on server 1 gets Figure 7 The topology of the chipset network shown in the figure creates a process, which includes a time synchronization thread, a control and inspection thread. Among them, the time synchronization thread, the control and inspection thread can be regarded as a subtask respectively. The control and inspection thread assigns the 22 subtasks ENV1-1 to ENV1-6, ENV2-1 to ENV2-16 to the 22 idle CPU cores on the server 1, such as CPU core 1 to CPU core 22. These 22 CPU cores create processes corresponding to the subtasks respectively, and the CPU core calls the process to execute the received subtasks.

[0134] In addition, control and inspection threads are based on Figure 8 The topology shown creates shared files for subtasks that need to interact with each other. Figure 8 In the example, the connection between subtasks indicates that subtasks need to communicate to exchange data. Combined with the time synchronization thread, it also needs to communicate with each subtask to achieve time synchronization. The topology of the above chipset network can be abstracted as Fig. 9 Model shown. Fig. 9In the process, the control and inspection threads can inspect and control the execution of subtasks according to the corresponding messages, such as creating shared files.

[0135] When the CPU core 1 to the CPU core 22 call the process to execute the subtask, they send the simulation time to the time synchronization thread through the shared file.

[0136] The time synchronization thread dynamically adjusts the processes of each CPU core according to the simulation time of each CPU core 1 to CPU core 22, such as pausing the process in the CPU core with faster simulation time; when the simulation time of the slowest CPU core reaches a simulation cycle, the process in the CPU core with faster simulation time is resumed to continue executing the subtask. In this way, the processes of the 22 CPU cores are synchronized under the same system clock, achieving system time synchronization.

[0137] In the embodiment of the present application, 22 CPU cores execute 22 subtasks in parallel to complete the verification of the chipset network composed of 22 chips, thereby improving the chip verification efficiency of EDA simulation and eliminating the need for expensive dedicated processors, thereby reducing the verification cost of large-scale chipset networks as a whole.

[0138] Corresponding to the above chip verification method, the present application embodiment also provides a chip verification device, such as Fig.10 As shown, applied to the first CPU core, the device includes:

[0139] A first acquisition module 1001 is used to acquire a simulation task for chip verification, where the simulation task includes multiple subtasks;

[0140] An allocation module 1002 is used to allocate an idle second CPU core to each subtask and create an underlying communication space for multiple subtasks;

[0141] The sending module 1003 is used to send multiple subtasks to the corresponding second CPU cores, so that each second CPU core executes the corresponding subtask, and uses the underlying communication space to interact with other second CPU cores to exchange data generated during the execution of the subtasks.

[0142] In some embodiments, Fig.11 As shown, the chip verification device may further include:

[0143] A second acquisition module 1101 is used to continuously acquire simulation time of multiple second CPU cores;

[0144] The indication module 1102 is used to instruct the third CPU core to suspend the execution of the subtask when the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to a first preset duration; the third CPU core is any second CPU core among the multiple second CPU cores, and the fourth CPU core is the second CPU core with the slowest simulation time among the multiple second CPU cores; when the difference between the simulation time of the third CPU core and the fourth CPU core is less than or equal to a second preset duration, instruct the third CPU core to resume the execution of the subtask.

[0145] In some embodiments, the indication module 1102 may be specifically configured to:

[0146] When the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to the first preset duration, and the simulation time of the third CPU core reaches one simulation cycle, the third CPU core is instructed to suspend execution of the subtask.

[0147] In some embodiments, the second preset duration is zero;

[0148] The instructing module 1102 may be specifically used to instruct the third CPU core to resume executing the subtask when the simulation time of the fourth CPU core reaches one simulation cycle.

[0149] In some embodiments, the allocation module 1002 may be specifically configured to:

[0150] According to the topological structure of the multiple subtasks, two second CPU cores with data interaction are determined;

[0151] Create low-level communication space for the two second CPU cores.

[0152] In some embodiments, the chip verification device may further include:

[0153] A detection module, used to detect each second CPU core to obtain the execution status of the subtask in each second CPU core;

[0154] The processing module is used to perform post-processing corresponding to the execution status of the subtasks in each CPU core.

[0155] In some embodiments, the underlying communication space is a shared file, shared memory, or a Unix domain socket.

[0156] In some embodiments, the first CPU core and the plurality of second CPU cores are located on the same server.

[0157] In the technical solution provided in the embodiment of the present application, the first CPU core splits a chip verification simulation task into multiple subtasks; and allocates an idle second CPU core to each subtask, and each second CPU core executes the subtask respectively, so that multiple second CPU cores execute the subtasks in parallel to complete the simulation task, thereby improving the chip verification efficiency. In addition, in the embodiment of the present application, it is completed by the CPU core on the server, without the need to use an expensive dedicated processor, thereby reducing the cost of chip verification.

[0158] Corresponding to the above chip verification method, the embodiment of the present application also provides an electronic device, such as Fig.12 As shown, it includes a processor 1201 , a communication interface 1202 , a memory 1203 and a communication bus 1204 , wherein the processor 1201 , the communication interface 1202 , and the memory 1203 communicate with each other via the communication bus 1204 .

[0159] Memory 1203, used for storing computer programs;

[0160] The processor 1201 is used to implement the following steps when executing the program stored in the memory 1203:

[0161] Acquire a simulation task for chip verification, wherein the simulation task includes multiple subtasks;

[0162] Allocate an idle second CPU core to each subtask respectively, and create an underlying communication space for the multiple subtasks;

[0163] The multiple subtasks are sent to corresponding second CPU cores, so that each second CPU core executes the corresponding subtask, and the underlying communication space is used to interact with other second CPU cores to generate data during the execution of the subtasks.

[0164] The communication bus mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0165] The communication interface is used for communication between the above electronic device and other devices.

[0166] The memory may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0167] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0168] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above chip verification methods are implemented.

[0169] In another embodiment provided in the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute any chip verification method in the above embodiments.

[0170] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0171] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0172] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the chip verification device, electronic device, storage medium and program product embodiments, since they are basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0173] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A chip verification method, characterized in that: Applied to the first CPU core, the method comprises: Acquire a simulation task for chip verification, wherein the simulation task includes multiple subtasks; Allocate an idle second CPU core to each subtask respectively, and create an underlying communication space for the multiple subtasks; Sending the multiple subtasks to corresponding second CPU cores so that each second CPU core executes the corresponding subtask, and using the underlying communication space to interact with other second CPU cores for data generated during the execution of the subtasks; Continuously obtain the simulation time of multiple second CPU cores; When the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to the first preset duration, instructing the third CPU core to suspend execution of the subtask; the third CPU core is any second CPU core among the multiple second CPU cores, and the fourth CPU core is the second CPU core with the slowest simulation time among the multiple second CPU cores; When the difference between the simulation time of the third CPU core and the simulation time of the fourth CPU core is less than or equal to a second preset duration, the third CPU core is instructed to resume executing the subtask.

2. The method according to claim 1, characterized in that The step of instructing the third CPU core to suspend execution of the subtask when the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to the first preset duration includes: When the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to the first preset duration, and the simulation time of the third CPU core reaches one simulation cycle, the third CPU core is instructed to suspend execution of the subtask.

3. The method according to claim 2, characterized in that The second preset duration is zero; The step of instructing the third CPU core to resume executing the subtask when the difference between the simulation time of the third CPU core and the fourth CPU core is less than or equal to the second preset duration includes: When the simulation time of the fourth CPU core reaches one simulation cycle, the third CPU core is instructed to resume executing the subtask.

4. The method according to claim 1, characterized in that The step of creating an underlying communication space for the multiple subtasks includes: Determine, according to the topological structure of the multiple subtasks, two second CPU cores with which data interaction exists; An underlying communication space is created for the two second CPU cores.

5. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: Detect each second CPU core to obtain the execution status of the subtask in each second CPU core; The subtasks in each CPU core are subjected to post-processing corresponding to the execution status.

6. The method according to any one of claims 1 to 4, characterized in that: The underlying communication space is a shared file, a shared memory or a Unix domain socket.

7. The method according to any one of claims 1 to 4, characterized in that: The first CPU core and the plurality of second CPU cores are located on the same server.

8. A chip verification device, characterized in that: Applied to a first CPU core, the device comprises: A first acquisition module is used to acquire a simulation task for chip verification, wherein the simulation task includes multiple subtasks; An allocation module, used for respectively allocating an idle second CPU core to each subtask and creating an underlying communication space for the multiple subtasks; A sending module, used to send the multiple subtasks to the corresponding second CPU cores, so that each second CPU core executes the corresponding subtask, and to interact with other second CPU cores using the underlying communication space to generate data during the execution of the subtasks; A second acquisition module, used for continuously acquiring simulation time of multiple second CPU cores; An indication module is used to instruct the third CPU core to suspend execution of a subtask when the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to a first preset duration; the third CPU core is any second CPU core among the multiple second CPU cores, and the fourth CPU core is the second CPU core with the slowest simulation time among the multiple second CPU cores; when the difference between the simulation time of the third CPU core and the fourth CPU core is less than or equal to a second preset duration, instruct the third CPU core to resume execution of the subtask.

9. The device according to claim 8, characterized in that The indication module is specifically used for: When the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to the first preset duration, and the simulation time of the third CPU core reaches one simulation cycle, the third CPU core is instructed to suspend execution of the subtask.

10. The device according to claim 9, characterized in that The second preset duration is zero; The instructing module is specifically used to instruct the third CPU core to resume executing the subtask when the simulation time of the fourth CPU core reaches one simulation cycle.

11. The device according to claim 8, characterized in that The allocation module is specifically used for: Determine, according to the topological structure of the multiple subtasks, two second CPU cores with which data interaction exists; An underlying communication space is created for the two second CPU cores.

12. The device according to any one of claims 8 to 11, characterized in that: The device also includes: A detection module, used to detect each second CPU core to obtain the execution status of the subtask in each second CPU core; The processing module is used to perform post-processing corresponding to the execution status on the subtasks in each CPU core.

13. The device according to any one of claims 8 to 11, characterized in that: The underlying communication space is a shared file, a shared memory or a Unix domain socket.

14. The device according to any one of claims 8 to 11, characterized in that: The first CPU core and the plurality of second CPU cores are located on the same server.

15. A server, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, for implementing any of the methods described in claims 1-7 when executing a program stored in a memory.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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