Method for realizing universal transmission interface of audio data, audio device and storage medium

Abstract

The present application relates to electronic digital data processing, and discloses a method for realizing a universal transmission interface of audio data, an audio device, and a storage medium, including: based on a clock module, receiving or generating a bus protocol clock, and generating an internal first clock signal and a second clock signal; based on a synchronization module, receiving or generating a synchronization signal; using the first clock signal as the clock of a first logic module and a first counter, using the second clock signal as the clock of a second logic module and a second counter, and capturing the rising edge of the synchronization signal as a trigger signal; when the first counter is triggered, the first logic module receives serial data from the bus of the audio interface for storage; when the second counter is triggered, the second logic module reads out multi-bit wide audio data from a storage unit for transmission. The present application aims to realize a universal transmission interface of audio data supporting multiple audio protocols in a low-cost manner.

Description

Technical Field

[0001] The present application relates to the field of electronic digital data processing, and in particular to a method for realizing a universal transmission interface of audio data, an audio device, and a computer-readable storage medium. Background Art

[0002] In the current audio data transmission technology, various audio data transmission protocols are widely used to meet different audio processing and transmission requirements. Common audio data transmission protocols include I2S (Inter-IC Sound), PCM (Pulse Code Modulation) and TDM (Time-Division Multiplexing).

[0003] I2S is a standard protocol for connecting digital audio devices. It transmits audio data through clock signals and data lines, but does not include clock generation. It usually needs to be used with other components. Although I2S has good performance in audio data transmission, it has high hardware requirements and is not easily compatible with other protocols.

[0004] PCM is a coding method that converts analog signals into digital signals and is widely used in audio storage and transmission. PCM coding has a high data transmission rate and requires a large bandwidth. Compared with I2S, PCM requires higher data processing capabilities and storage resources.

[0005] TDM is a technology that distributes multiple audio streams to different time segments. It is suitable for applications that transmit multiple audio signals at the same time. TDM technology can effectively improve the efficiency of data transmission, but it requires precise time synchronization and control. This technology is very useful when processing complex audio signals, but its design and implementation are relatively complex.

[0006] Due to the different characteristics of I2S, PCM, and TDM protocols, not all audio devices can support the formats of these protocols at the same time. Even for audio devices that can support these protocol formats at the same time, there are problems in design and implementation, such as inflexible configuration (in order to support multiple protocols, the device often needs to be configured with hardware, but this configuration is usually fixed and difficult to flexibly adjust according to actual needs), complex circuit design (to be compatible with different protocol requirements), the need to use multiple audio interfaces, and occupy more device space, resulting in high preparation costs for audio equipment.

[0007] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art. Summary of the invention

[0008] The main purpose of the present application is to provide a method for realizing a universal transmission interface for audio data, an audio device and a computer-readable storage medium, aiming to realize a universal transmission interface for audio data that supports multiple audio protocols in a low-cost manner.

[0009] To achieve the above-mentioned purpose, the present application provides a method for realizing a universal transmission interface of audio data, which is applied to a data transmission circuit of an audio device, wherein the data transmission circuit includes a clock module, a synchronization module and a logic module connected to the audio interface, and the logic module includes a first counter, a second counter, a first logic module and a second logic module; the data transmission circuit is connected to a host or a slave corresponding to the audio device through the audio interface; the method for realizing a universal transmission interface of audio data includes:

[0010] Based on the clock module, a bus protocol clock is received or generated, and an internal first clock signal and a second clock signal are generated according to the bus protocol clock; wherein the first clock signal and the second clock signal are clock signals corresponding to the receiving and sending logic requirements respectively;

[0011] Based on the synchronization module, receiving or generating a synchronization signal corresponding to the bus protocol clock;

[0012] Using the first clock signal as the clock of the first logic module and the first counter, using the second clock signal as the clock of the second logic module and the second counter, and capturing the rising edge of the synchronization signal as the trigger signal of the first counter and the second counter;

[0013] When the first counter is triggered, the first logic module receives serial data from the bus of the audio interface, and writes the data into the storage unit after performing serial-to-parallel processing through the shift register; when the second counter is triggered, the second logic module reads multi-bit-wide audio data from the storage unit, and outputs the data to the protocol data line of the audio interface after performing parallel-to-serial processing through the reverse shift register.

[0014] To achieve the above object, the present application further provides an audio device, the audio device comprising a data transmission circuit, the data transmission circuit comprising a clock module, a synchronization module and a logic module connected to an audio interface, and the logic module comprising a first counter, a second counter, a first logic module and a second logic module; the data transmission circuit is connected to a host or a slave corresponding to the audio device through the audio interface;

[0015] The audio device further comprises: a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the method for implementing the universal transmission interface of audio data as described above.

[0016] To achieve the above objectives, the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for implementing the universal transmission interface for audio data as described above are implemented.

[0017] The universal transmission interface implementation method for audio data, audio device and computer-readable storage medium provided by the present application integrate clock, synchronization and logic modules in the data transmission circuit of the audio device, can effectively support multiple audio protocols, and solve the problems of compatibility of different protocols, inflexible configuration and complex circuit design. Not only can its flexibility and modular design help reduce the preparation cost of audio devices and improve design efficiency, but also the data transmission circuit only needs to use one audio interface to be compatible with multiple different audio protocols, which simplifies the design of the data transmission circuit of the audio device, effectively saves the equipment space occupied by the data transmission circuit, and further reduces the preparation cost of the audio device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of the structure of a data transmission circuit in one embodiment of the present application;

[0019] Figure 2 This is a schematic diagram of the steps of a method for implementing a universal transmission interface for audio data in an embodiment of the present application;

[0020] Figure 3 This is a schematic diagram of a logic circuit when the audio device is a slave in one embodiment of the present application;

[0021] Figure 4 This is a schematic diagram of signal synchronization in the I2S philip format in an embodiment of the present application;

[0022] Figure 5 This is a schematic diagram of signal synchronization in a PCM long frame format in an embodiment of the present application;

[0023] Figure 6 Schematic diagram of the internal structure of an audio device according to an embodiment of the present application.

[0024] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0025] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0026] In addition, if the descriptions of "first", "second", etc. are involved in this application, they are only used for descriptive purposes (such as for distinguishing the same or similar features), and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0027] In one embodiment, a method for realizing a universal transmission interface of audio data is provided, which is applied to a data transmission circuit of an audio device; Figure 1 The data transmission circuit includes a clock module, a synchronization module and a logic module connected to the audio interface, and the logic module includes a first counter, a second counter, a first logic module and a second logic module; the data transmission circuit is connected to the host or slave corresponding to the audio device through the audio interface.

[0028] Based on the data transmission circuit of the above audio equipment, refer to Figure 2 , the method for implementing the universal transmission interface of audio data includes:

[0029] Step S10: Based on the clock module, a bus protocol clock is received or generated, and an internal first clock signal and a second clock signal are generated according to the bus protocol clock; wherein the first clock signal and the second clock signal are clock signals corresponding to the receiving and sending logic requirements, respectively;

[0030] Step S20: Based on the synchronization module, receiving or generating a synchronization signal corresponding to the bus protocol clock;

[0031] Step S30, using the first clock signal as the clock of the first logic module and the first counter, using the second clock signal as the clock of the second logic module and the second counter, and capturing the rising edge of the synchronization signal as the trigger signal of the first counter and the second counter;

[0032] Step S40, when the first counter is triggered, the first logic module receives serial data from the bus of the audio interface, and writes it to the storage unit after serial-to-parallel processing through the shift register; when the second counter is triggered, the second logic module reads out multi-bit width audio data from the storage unit, and outputs it to the protocol data line of the audio interface after parallel-to-serial processing through the reverse shift register.

[0033] In this embodiment, the execution terminal of the embodiment may be an audio device, or may be other equipment or devices that control the audio device (such as a host to which the audio device as a slave belongs).

[0034] As described in step S10, when the audio device acts as a slave, the clock module is connected to the host through the audio interface and receives the bus protocol clock generated by the host; when the audio device acts as a host, the clock module directly generates the bus protocol clock and provides the generated bus protocol clock to the connected slave through the audio interface. In this way, the data transmission timing between the slave and the host can be ensured to be consistent.

[0035] It should be understood that the bus protocol clock is the basic clock signal for all data transmission in the system. It defines the basic rhythm of data transmission, and all data exchange, synchronization and timing control are based on this clock.

[0036] In addition, in addition to receiving or generating the bus protocol clock, the clock module also generates an internal first clock signal and a second clock signal according to the received or generated bus protocol clock, wherein the first clock signal and the second clock signal are clock signals corresponding to the receiving and sending logic requirements respectively.

[0037] Optionally, based on the bus protocol clock, a first clock signal generated by the clock module is used to drive a data receiving logic; similarly, the clock module also generates a second clock signal to drive a data sending logic.

[0038] In actual applications, the first and second clock signals can be used for data reception and transmission logic according to the positive and negative edges of the bus protocol clock, such as negative transmission and positive reception of I2S and positive transmission and negative reception of PCM. In this embodiment, fixed transmission and reception edges are not limited, but the transmission and reception logic can be flexibly implemented as positive transmission and negative reception, positive transmission and positive reception, negative transmission and positive reception, or negative transmission and negative reception according to the configuration parameters of the specific protocol.

[0039] In some optional embodiments, a phase lock loop (PLL) or a digital frequency synthesizer may be provided in the clock module, so that when the audio device acts as a host, its clock module can dynamically adjust the frequency of the bus protocol clock according to the requirements of the currently transmitted audio protocol.

[0040] Optionally, a set of clock frequency values ​​are preset for various audio protocols (such as I2S, PCM, TDM, etc.), and the corresponding frequency is selected to generate the bus protocol clock after the audio protocol is identified.

[0041] As described in step S20, when the audio device acts as a slave, it receives the synchronization signal corresponding to the bus protocol clock generated by the host through the audio interface based on the synchronization module; when the audio device acts as a host, it generates a synchronization signal corresponding to the bus protocol clock based on the synchronization module, and provides the generated synchronization signal to the slave connected to it through the audio interface.

[0042] It should be understood that the bus protocol clock is the basic clock signal, which provides a time reference for the data transmission of the entire system, so the host needs to generate a synchronization signal based on this clock signal. The synchronization signal is synchronized with the bus protocol clock and can be a pulse signal, which is used to coordinate the timing of data transmission so that the receiving and sending operations can be performed according to the predetermined time.

[0043] Among them, the pulse width and timing of the synchronization signal can be achieved through the counter inside the synchronization module, that is, using an internal counter (such as a binary counter) and logic gates to generate a pulse signal synchronized with the bus protocol clock. The internal counter can be set to generate a pulse at a specific count value to form a synchronization signal.

[0044] Optionally, the synchronization signal may be encoded in different ways, such as a single pulse, a frame synchronization signal, or a data embedded synchronization signal. A suitable encoding method may be selected according to requirements to match system requirements.

[0045] Optionally, the internal counter can generate a flag signal for the synchronization signal to flip according to the configuration parameters (such as frame length). The initial state of the synchronization signal reset can be a low level. When the high level maintenance length begins, the counter count jumps to a high level, and the synchronization signal maintains a high level before the flag signal is generated. After the flag signal is detected, the level is flipped (changed to a low level) until the frame end signal is detected and then returns to the initial high level of the next frame, and then the phase of the "initial synchronization signal" is adjusted (reverse or maintain) according to the polarity parameter. Among them, the synchronization module can count the frame length of the data frame and generate a frame end signal.

[0046] As described in step S30, after the clock module generates the internal first clock signal and the second clock signal, the first clock signal is transmitted to the first logic module and the first counter to serve as the clock of the first logic module and the first counter; and the second clock signal is transmitted to the second logic module and the second counter to serve as the clock of the second logic module and the second counter.

[0047] Thereafter, the first counter will count according to the frequency of the first clock signal, and the second counter will count according to the frequency of the second clock signal; the first logic module will perform corresponding operations according to the first clock signal (after being triggered), such as data receiving, processing and storing; the second logic module will perform corresponding operations according to the second clock signal (after being triggered), such as data sending and transmitting.

[0048] At the same time, the rising edge of the synchronization signal from the synchronization module is captured as a trigger signal for the first counter and the second counter to count.

[0049] As described in step S40, when the first counter is triggered, the first counter starts counting and generates a flag signal for triggering the first logic module to receive data, so that the first logic module sequentially receives the serial data (i.e., serial audio data) of each receiving channel (i.e., receiving channel of audio data) of the bus of the audio interface based on the first clock signal, and performs serial-to-parallel processing through the shift register. Wherein, after the first logic module receives and processes the serial data of a receiving channel, the obtained parallel data is written into the storage unit.

[0050] Optionally, when the second counter is triggered, the second counter starts counting and generates a flag signal that triggers the second logic module to send data, so that the second logic module reads out the multi-bit width audio data of each sending channel (i.e., the sending channel of the audio data) from the storage unit in sequence based on the second clock signal, and after parallel-to-serial processing through the reverse shift register, outputs it bit by bit to the corresponding protocol data line of the audio interface.

[0051] Optionally, in circuit implementation, the implementation of the first clock signal and the second clock signal for the data reception and transmission logic requirements only requires the use of two inverters plus two selectors: one group of inverters + selectors is responsible for controlling the phase relationship between the first clock signal of the receiving channel and the bus protocol clock; the other group of inverters + selectors is responsible for controlling the phase relationship between the second clock signal of the sending channel and the bus protocol clock, and the two are independent of each other.

[0052] Optional, see Figure 3, taking the audio device as a slave as an example: inside the device, the bus protocol clock input from the outside through the audio interface is used as the input of the logic circuit composed of the first inverter F1 and the first selector X1, and the logic circuit composed of the first inverter F1 and the first selector X1 is responsible for controlling the output of the first clock signal rc to the shift register J1, and then the shift register J1 receives and processes the data input from the outside through the audio interface based on the first clock signal rc (of course, as a slave, it will also receive the external input synchronization signal); and the bus protocol clock input from the outside through the audio interface is also used as the input of the logic circuit composed of the second inverter F2 and the second selector X2, and the logic circuit composed of the second inverter F2 and the second selector X2 is responsible for controlling the output of the second clock signal tc to the reverse shift register J2, and then the reverse shift register J2 reads and processes the corresponding data based on the second clock signal tc, and then sends the data to the outside.

[0053] In this way, the circuit design is simplified, and the timing requirements of the data receiving and transmitting logic can be effectively met by controlling the phase relationship of the clock signal using a combination of two sets of inverters and selectors.

[0054] In one embodiment, the first clock signal and the second clock signal generated by the clock module can meet the clock requirements of the receiving and sending logics respectively; at the same time, the synchronization signal can ensure the timing consistency of data transmission and support the requirements of different protocols for data synchronization (whether it is a synchronous audio stream (such as PCM) or an asynchronous audio stream (such as I2S), the accuracy of data transmission can be ensured by this synchronization signal); and the counter and logic processing unit contained in the logic module can be adjusted and configured according to the requirements of the protocol to ensure that the system can process audio data streams of various protocols. In this way, through the abstract clock and synchronization processing mechanism, the specific protocol requirements are converted into a universal clock signal and data processing logic, thereby supporting multiple protocols at the abstract level without the need to design hardware separately for each protocol.

[0055] This method for implementing a universal transmission interface for audio data integrates clock, synchronization and logic modules in the data transmission circuit of an audio device, can effectively support multiple audio protocols, and solves the problems of compatibility of different protocols, inflexible configuration and complex circuit design. Not only can its flexibility and modular design help reduce the preparation cost of audio equipment and improve design efficiency, but also the data transmission circuit can be compatible with multiple different audio protocols using only one audio interface (for example, the audio interface can use a set of standard I2S interfaces to implement a universal audio interface, which can be compatible with PCM, TDM and other protocols other than I2S, that is, it is compatible with the universal standard I2S format of two channels, left-aligned and right-aligned I2S derivative formats, multi-channel PCM formats and TDM formats for time-sharing multiple devices, and can also support the simultaneous reception and transmission of audio data with different data format requirements in the same data frame), which simplifies the design of the data transmission circuit of the audio device, effectively saves the equipment space occupied by the data transmission circuit, and further reduces the preparation cost of the audio device.

[0056] Furthermore, when the universal transmission interface implementation method for audio data and the data transmission circuit of audio equipment are applied in the R&D scenario of audio acquisition chips, the R&D team does not need to develop specific interface circuits for each protocol separately, which greatly reduces the workload of repeated design and verification and shortens the R&D cycle. That is, by reducing repeated development work, simplifying circuit design and testing processes, improving design flexibility and scalability, and reducing R&D costs and risks, the R&D efficiency of audio acquisition chips can be significantly improved.

[0057] In one embodiment, based on the above embodiment, a phase-locked loop or a digital frequency synthesizer may be provided in the clock module, so that when the audio device is used as a host, its clock module can dynamically adjust the frequency of the bus protocol clock according to the requirements of the currently transmitted audio protocol. Among them, a set of clock frequency values ​​are preset for various audio protocols, and the corresponding frequency is selected to generate the bus protocol clock after the audio protocol is identified.

[0058] In this embodiment, the audio device acts as a host and can also monitor changes in data flow during data transmission, and analyze whether there is an increase in error rate or data loss under the current clock frequency.

[0059] Optionally, if an increased error rate or abnormal data traffic is detected, the host recognizes that the frequency of the current bus protocol clock does not match the current audio protocol and automatically adjusts the clock frequency to an appropriate value.

[0060] Among them, during the data transmission process, the host can use the preset parameter table to adaptively adjust the frequency of the bus protocol clock; that is, a series of predefined clock frequencies are set in advance according to different sampling rates and bits, so that the required frequency can be quickly determined according to the needs of the audio protocol. Alternatively, an adaptive clock frequency adjustment algorithm is used to dynamically adjust the clock frequency according to the data transmission status and performance indicators (such as data error rate, transmission delay, etc.).

[0061] Optionally, the clock frequency adjustment algorithm can set a target data error rate and transmission delay range (e.g., the error rate should be lower than a preset threshold, and the delay should be within a predetermined range), and calculate the error between the actual performance indicator and the target value (the error is calculated for the data error rate and the delay separately). The clock frequency is then adjusted according to the error size, wherein the larger the error, the larger the amplitude of the adjustment of the clock frequency.

[0062] Then, the frequency of the bus protocol clock is adjusted according to the calculated adjustment amplitude value of the clock frequency. Among them, the adjustment method can adopt a progressive adjustment strategy, divide the required adjustment amplitude value into multiple parts, and adjust the frequency of the bus protocol clock in multiple times to avoid interference to the system caused by large changes in the clock.

[0063] Alternatively, considering that there are multiple protocol formats under audio protocols such as I2S, PCM, and TDM, the host can also select the most suitable protocol format from multiple audio protocol formats (such as I2S philip format, I2S philip format in TDM mode, left-aligned I2S format, left-aligned I2S format in TDM mode, right-aligned I2S format, right-aligned I2S format in TDM mode, PCM short frame format, PCM short frame format in TDM mode, PCM long frame format, PCM format driven by the negative edge of the bus protocol clock, etc.) according to the data characteristics of the audio data to be transmitted, and generate a bus protocol clock corresponding to the protocol format.

[0064] Among them, the data characteristics of the analyzed audio data may include: identifying the sampling rate of the audio data (such as 44.1kHz, 48kHz, 96kHz, etc.), determining the bit depth of the audio data (such as 16 bits, 24 bits, 32 bits), judging the number of channels of the audio data (such as mono, stereo, 5.1 channels), etc.

[0065] Then, from the candidate protocol formats, select the protocol format that meets the following conditions:

[0066] (1) Select a protocol format that supports the required sampling rate of audio data;

[0067] (2) Select a protocol format that supports the required bit depth of audio data;

[0068] (3) Select a protocol format that can handle the number of audio data channels.

[0069] Finally, the corresponding bus protocol clock is generated according to the clock frequency applicable to the selected protocol format.

[0070] Optionally, if there are multiple selected protocol formats, the clock frequency applicable to the audio data can also be calculated: clock frequency = sampling rate × bit depth × number of channels. Then, based on the calculated clock frequency, a protocol format that is compatible with the applicable clock frequency can be further selected.

[0071] In this way, a flexible protocol selection algorithm can be implemented, which can select the most suitable protocol from a variety of audio protocol formats according to the characteristics of the audio data (such as sampling rate, bit depth, number of channels), and generate the corresponding bus protocol clock. This design can effectively improve the efficiency and stability of audio data transmission. Such a solution provides greater flexibility, compatibility and optimization capabilities. Compared with the traditional fixed audio protocol and bus protocol clock solution, it can better adapt to different audio data characteristics, improve system performance and reduce hardware complexity.

[0072] In one embodiment, based on the above embodiment, the synchronization module is further used to receive or generate left and right channel selection signals.

[0073] In this embodiment, when the audio device itself acts as a slave, it also receives the left and right channel selection signals generated by the host through the audio interface based on the synchronization module; when the audio device itself acts as a host, it generates left and right channel selection signals based on the synchronization module, and provides the generated left and right channel selection signals to the slave connected to it through the audio interface.

[0074] The left and right channel selection signals are used to specify whether the current audio data stream is the left channel or the right channel. In a stereo or multi-channel audio system, this signal ensures that the data is correctly allocated to the corresponding channel, thereby achieving spatial positioning and clarity of the audio.

[0075] That is, the synchronization module can generate a corresponding synchronization signal based on the bus protocol clock and the left and right channel selection signals.

[0076] In one embodiment, based on the above embodiment, the method for implementing the universal transmission interface of audio data further includes:

[0077] When the synchronization module generates a synchronization signal, the high level maintenance length and polarity of the synchronization signal are configured according to the requirements of different protocol formats.

[0078] In this embodiment, when the audio device acts as a host, the synchronization module needs to generate a synchronization signal according to the bus protocol clock.

[0079] At this time, the synchronization module can configure the high-level maintenance length (or maintenance time) and polarity of the synchronization signal according to the requirements of different protocol formats.

[0080] Optionally, the high-level maintenance length of the synchronization signal can be calculated or set based on the specification of the currently used audio protocol (usually determined by the time window specified in the protocol specification); the polarity is used to determine whether the high level is valid or the low level is valid.

[0081] Based on the high level maintenance length and polarity of the configured synchronization signal, the counter inside the synchronization module will generate a synchronization signal flip flag signal according to the configuration parameters (such as frame length).

[0082] Generally, the longest commonly used frame length is 256 clock cycles, but in order to adapt to frames of different lengths and to save resources, this embodiment can provide a configuration register, which can set the frame length step to 8, that is, 8 multiples of a single clock cycle (8~256). At the same time, the rising edge of the synchronization signal generated by the synchronization module is used as a trigger signal for the first and second counters to count.

[0083] Reference Figure 4 , taking the signal synchronization of I2S philip format as an example: set the high level maintenance length to lrck_w, the frame length to frm_w, the polarity = 1, and reverse the polarity of the original high level to achieve low level maintenance. This format configures 1 / lrck_w=1 / 2frm_w.

[0084] Reference Figure 5 , taking the signal synchronization of PCM long frame format as an example: the high level maintenance length lrck_w can be configured to 1~128 (that is, maintain 1~128 times the corresponding clock cycle; 1 / lrck_w≤1 / 2frm_w), polarity = 0, then the original high level polarity is not reversed, that is, the high level is maintained.

[0085] In one embodiment, based on the above embodiment, after the step of using the first clock signal as the clock of the first logic module and the first counter, using the second clock signal as the clock of the second logic module and the second counter, and capturing the rising edge of the synchronization signal as the trigger signal of the first counter and the second counter, the method further includes:

[0086] Based on the configuration register, selecting whether to trigger the first counter again when receiving the next valid edge after the rising edge of the synchronization signal;

[0087] Alternatively, based on the configuration register, it is selected whether to trigger the second counter again when the next valid edge after the rising edge of the synchronization signal is received.

[0088] In this embodiment, the configuration register is set to determine the triggering timing of the counter and perform related data processing and operations.

[0089] Optionally, when the audio protocol is a protocol format such as the I2S Philip standard format, PCM short frame format, etc., in which the received data is one clock cycle later than the synchronization signal, then based on the configuration register, it is selected to trigger the first counter when the next valid edge after the rising edge of the synchronization signal is received; otherwise (such as when the audio protocol is a protocol format such as the I2S left-aligned format, PCM long frame format, etc., in which the received data and the synchronization signal are in the same clock cycle), the first counter is directly triggered when the first rising edge of the synchronization signal is received.

[0090] Optionally, when the audio protocol is a protocol format such as the I2S Philip standard format, PCM short frame format, etc., which sends data one clock cycle later than the synchronization signal, then based on the configuration register, it is selected to trigger the second counter when the next valid edge after the rising edge of the synchronization signal is received; otherwise (such as when the audio protocol is a protocol format such as the I2S left-aligned format, PCM long frame format, etc., which sends data and the synchronization signal in the same clock cycle), the second counter is directly triggered when the first rising edge of the synchronization signal is received.

[0091] In one embodiment, based on the above embodiment, when the first counter is triggered, the step of causing the first logic module to receive serial data from the bus of the audio interface and write the serial data into the storage unit after serial-to-parallel processing through the shift register includes:

[0092] When the first counter is triggered, the first counter starts counting and generates a flag signal for triggering the first logic module to receive data;

[0093] The first logic module sequentially receives serial data from each receiving channel of the bus of the audio interface, and performs serial-to-parallel processing through a shift register; wherein, after receiving and processing the serial data of a receiving channel, the obtained parallel data is written into the storage unit.

[0094] In this embodiment, when the first counter is triggered, the first counter starts counting and generates a flag signal for triggering the first logic module to receive data, so that the first logic module starts receiving serial data from the bus of the audio interface.

[0095] The first logic module receives serial data from each receiving channel of the audio interface bus in turn, and performs serial-to-parallel processing through the shift register. The shift register shifts the received serial data one bit at a time to the higher bit, and the received data is first shifted to bit0, then from bit0 to bit1, bit1 to bit2, ..., bit(N-1) to bitN, and so on; through this shift operation, the shift register can flexibly arrange the data of each receiving channel in the data frame to form the final parallel data (i.e., multi-bit wide audio data). For example, a shift register can be configured with an 8-bit width to convert the received 8-bit serial data into 8-bit parallel data (i.e., 8-bit wide audio data) for subsequent processing.

[0096] After the data of the current receiving channel is processed and written into the storage unit, the serial data of the next receiving channel begins to be received and processed, and so on, until the serial data of all receiving channels are processed and stored.

[0097] In this way, accurate reception, processing and storage of audio data can be ensured, thereby achieving efficient data management and processing.

[0098] In some optional embodiments, after the serial data of all receiving channels are converted into multi-bit-width audio data and written into the storage unit, it is detected whether the multi-bit-width audio data stored in the current round is stored across two data blocks in the storage unit.

[0099] If so, the data block where the first bit of stored data is located is defined as the front data block, the data block where the last bit of stored data is located is defined as the rear data block, and the number of storage bits occupied by the multi-bit width audio data stored in the current round in the rear data block is detected (marked as the first storage bit number).

[0100] According to the first storage bit number, the multi-bit width audio data (marked as other audio data) not stored in the current round is searched in the previous data block, and the storage bit number occupied by the other audio data in the previous data block is marked as the second storage bit number. Then, the storage position of a portion of other audio data whose second storage bit number is greater than or equal to the first storage bit number is moved to after the storage position of the multi-bit width audio data stored in the current round to free up space in the previous data block. Then, starting from the first storage data of the multi-bit width audio data stored in the current round, the first and subsequent storage data are moved forward in sequence to occupy the vacated storage position of the previous data block, so that the multi-bit width audio data stored in the current round can be stored in the same data block in order.

[0101] This can effectively manage the data blocks in the storage unit and optimize the storage layout, thereby improving the efficiency of subsequent reading of multi-bit width data from the storage unit and reducing access latency.

[0102] In one embodiment, based on the above embodiment, the method for implementing the universal transmission interface of audio data further includes:

[0103] When the first count value of the first counter is greater than or equal to the starting position parameter of the current receiving channel and less than the ending position parameter, the serial data of the current receiving channel is received and processed, and when the first count value is equal to the ending position parameter, the parallel data obtained in the shift register is written into the storage unit;

[0104] Wherein, a corresponding starting position parameter and a transmission data length are provided in advance for each receiving channel, and an ending position parameter of each receiving channel is equal to the starting position parameter plus the transmission data length.

[0105] In this embodiment, corresponding configuration parameters are provided for each receiving channel, including a starting position parameter and a transmission data length. The starting position parameter determines the starting position of the receiving channel in the entire receiving data frame, and the transmission data length determines the length of data transmitted by the receiving channel. Therefore, the starting position parameter plus the transmission data length equals the ending position parameter (used to determine the ending position of the receiving channel in the entire receiving data frame).

[0106] The configuration parameters of different receiving channels are independent of each other and cannot overlap or be superimposed, that is, the timing corresponding to the end position parameter of the previous receiving channel should be before the start position parameter of the next receiving channel.

[0107] Optionally, when the first counter is triggered, the first counter starts counting and generates a first count value. When the first count value is greater than or equal to the starting position parameter of the current receiving channel and less than the ending position parameter, the first logic module is responsible for receiving and processing the serial data of the current receiving channel, and performing serial-to-parallel processing through the shift register, and when the first count value is equal to the ending position parameter of the current receiving channel, the parallel data obtained in the shift register is written into the storage unit. Then, the serial data of the next receiving channel is received and processed.

[0108] In this way, it can be ensured that the data reception, processing and storage of each receiving channel are independent and accurate. Using the first counter to control the timing of data reception and using the shift register for serial-parallel processing can effectively manage and store data while avoiding data overlap between receiving channels.

[0109] In one embodiment, based on the above embodiment, when the second counter is triggered, the second logic module reads out the multi-bit width audio data from the storage unit, performs parallel-serial processing through the reverse shift register, and then outputs it to the protocol data line of the audio interface, including the following steps:

[0110] When the second counter is triggered, the second counter starts counting and generates a flag signal for triggering the second logic module to send data;

[0111] The second logic module reads the multi-bit width audio data of each transmission channel from the storage unit in sequence, performs parallel-serial processing through the reverse shift register, and outputs the data bit by bit to the corresponding protocol data line of the audio interface.

[0112] In this embodiment, when the second counter is triggered, the second counter starts counting and generates a flag signal for triggering the second logic module to send data, so that the second logic module starts reading the data to be sent by each sending channel from the storage unit.

[0113] The second logic module reads out the multi-bit width audio data of each transmission channel from the storage unit in turn, and performs parallel and serial processing through the reverse shift register. The reverse shift register sends the read multi-bit width audio data one by one to the corresponding protocol data line of the audio interface. Taking the protocol data line as bus sdi as an example, the reverse shift register sends bitN to bus sdi, and shifts bit(N-1) to bitN, bit(N-2) to bit(N-1),..., bit1 to bit2, bit0 to bit1, and 0 to bit0; through this shift operation, the reverse shift register can convert the multi-bit width audio data into corresponding serial data for output.

[0114] After the data of the current sending channel is processed and sent, the data of the next sending channel is processed and sent, and so on, until the data of all sending channels are processed and sent.

[0115] In this way, accurate reading, processing and sending of audio data can be ensured, thereby achieving efficient data management and transmission.

[0116] In one embodiment, based on the above embodiment, the method for implementing the universal transmission interface of audio data further includes:

[0117] When the second count value of the second counter is greater than or equal to the start position parameter of the current sending channel and less than the end position parameter, read out and process the multi-bit width audio data of the current sending channel;

[0118] Wherein, a corresponding starting position parameter and a transmission data length are provided in advance for each transmission channel, and an ending position parameter of each transmission channel is equal to the starting position parameter plus the transmission data length.

[0119] In this embodiment, corresponding configuration parameters are provided for each sending channel, including a starting position parameter and a transmission data length. The starting position parameter determines the starting position of the sending channel in the entire sending data frame, and the transmission data length determines the length of data transmitted by the sending channel. Therefore, the starting position parameter plus the transmission data length equals the ending position parameter (used to determine the ending position of the sending channel in the entire sending data frame).

[0120] Among them, the configuration parameters of different sending channels are independent of each other and cannot be superimposed or overlapped, that is, the timing corresponding to the end position parameter of the previous sending channel should be before the start position parameter of the next sending channel.

[0121] Optionally, when the second counter is triggered, the second counter starts counting and generates a second count value. While the second count value is greater than or equal to the starting position parameter of the current transmission channel and less than the ending position parameter, the second logic module is responsible for reading out and processing the multi-bit width audio data of the current transmission channel from the storage unit, and performing parallel-serial processing through the reverse shift register, and outputting it bit by bit to the corresponding protocol data line of the audio interface. Then, after the multi-bit width audio data of the current transmission channel is converted from parallel to serial and sent, the multi-bit width audio data of the next transmission channel is read out and sent.

[0122] In this way, it can be ensured that the data reading, processing and transmission of each transmission channel are independent and accurate. Using the second counter to control the timing of data transmission and using the reverse shift register for parallel and serial processing can effectively manage and transmit data while avoiding data overlap between transmission channels.

[0123] In addition, an audio device is also provided in an embodiment of the present application, and the audio device includes a data transmission circuit; Figure 2 The data transmission circuit includes a clock module, a synchronization module and a logic module connected to the audio interface, and the logic module includes a first counter, a second counter, a first logic module and a second logic module; the data transmission circuit is connected to the host or slave corresponding to the audio device through the audio interface.

[0124] The internal structure of the audio device can be as follows Figure 6As shown, it includes a processor, a memory, a communication interface and an input interface connected by a system bus. The processor is used to provide computing and control capabilities. The memory includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database is used to store data called by the computer program. The communication interface is used to communicate data with an external terminal. The input interface is used to receive a signal input by an external device. When the computer program is executed by the processor, a universal transmission interface implementation method for audio data as described in the above embodiment is implemented.

[0125] Those skilled in the art will understand that Figure 6 The structure shown in the figure is only a block diagram of a part of the structure related to the present application scheme, and does not constitute a limitation on the audio device to which the present application scheme is applied. For example, in some optional embodiments, the audio device may also include an output interface (not shown in the figure), and the output interface is also connected to the system bus and is used to output corresponding signals to the peripheral device.

[0126] In addition, the present application also proposes a computer-readable storage medium, the computer-readable storage medium includes a computer program, and when the computer program is executed by a processor, the steps of the method for implementing a universal transmission interface for audio data as described in the above embodiment are implemented. It can be understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0127] In summary, the universal transmission interface implementation method for audio data, the audio device and the computer-readable storage medium provided in the embodiments of the present application integrate clock, synchronization and logic modules in the data transmission circuit of the audio device, which can effectively support multiple audio protocols and solve the problems of compatibility of different protocols, inflexible configuration and complex circuit design. Not only can its flexibility and modular design help reduce the preparation cost of audio devices and improve design efficiency, but also the data transmission circuit only needs to use one audio interface to be compatible with multiple different audio protocols, which simplifies the design of the data transmission circuit of the audio device, effectively saves the equipment space occupied by the data transmission circuit, and further reduces the preparation cost of the audio device.

[0128] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media provided in this application and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0129] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, device, article or method including the element.

[0130] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for realizing a universal transmission interface of audio data, applied to a data transmission circuit of an audio device, It is characterized in that The data transmission circuit includes a clock module, a synchronization module and a logic module connected to the audio interface, and the logic module includes a first counter, a second counter, a first logic module and a second logic module; The data transmission circuit is connected to a host or a slave corresponding to an audio device via an audio interface; the method for implementing the universal transmission interface of audio data includes: Based on the clock module, a bus protocol clock is received or generated, and an internal first clock signal and a second clock signal are generated according to the bus protocol clock; wherein the first clock signal and the second clock signal are clock signals corresponding to the receiving and sending logic requirements respectively; Based on the synchronization module, receiving or generating a synchronization signal corresponding to the bus protocol clock; Using the first clock signal as the clock of the first logic module and the first counter, using the second clock signal as the clock of the second logic module and the second counter, and capturing the rising edge of the synchronization signal as the trigger signal of the first counter and the second counter; Based on the configuration register, select whether to trigger the first counter again when the next valid edge after the rising edge of the synchronization signal is received; or, based on the configuration register, select whether to trigger the second counter again when the next valid edge after the rising edge of the synchronization signal is received; When the first counter is triggered, the first counter starts counting and generates a flag signal for triggering the first logic module to receive data; the first logic module sequentially receives the serial data of each receiving channel of the bus of the audio interface, and performs serial-to-parallel processing through the shift register; wherein, each time the serial data of a receiving channel is received and processed, the obtained parallel data is written into the storage unit; When the second counter is triggered, the second counter starts counting and generates a flag signal that triggers the second logic module to send data; the second logic module reads out the multi-bit width audio data of each sending channel from the storage unit in turn, and after parallel-serial processing through the reverse shift register, outputs it bit by bit to the corresponding protocol data line of the audio interface.

2. The method for realizing a universal transmission interface of audio data according to claim 1, It is characterized in that The synchronization module is also used to receive or generate left and right channel selection signals.

3. The method for realizing a universal transmission interface of audio data according to claim 1 or 2, It is characterized in that The method for implementing the universal transmission interface of audio data also includes: When the synchronization module generates a synchronization signal, the high level maintenance length and polarity of the synchronization signal are configured according to the requirements of different protocol formats.

4. The method for realizing a universal transmission interface of audio data according to claim 1, It is characterized in that The method for implementing the universal transmission interface of audio data also includes: When the first count value of the first counter is greater than or equal to the starting position parameter of the current receiving channel and less than the ending position parameter, the serial data of the current receiving channel is received and processed, and when the first count value is equal to the ending position parameter, the parallel data obtained in the shift register is written into the storage unit; Wherein, a corresponding starting position parameter and a transmission data length are provided in advance for each receiving channel, and an ending position parameter of each receiving channel is equal to the starting position parameter plus the transmission data length.

5. The method for realizing a universal transmission interface of audio data according to claim 1, It is characterized in that The method for implementing the universal transmission interface of audio data also includes: When the second count value of the second counter is greater than or equal to the start position parameter of the current sending channel and less than the end position parameter, read out and process the multi-bit width audio data of the current sending channel; Wherein, a corresponding starting position parameter and a transmission data length are provided in advance for each transmission channel, and an ending position parameter of each transmission channel is equal to the starting position parameter plus the transmission data length.

6. An audio device, It is characterized in that The audio device includes a data transmission circuit, the data transmission circuit includes a clock module, a synchronization module and a logic module connected to the audio interface, and the logic module includes a first counter, a second counter, a first logic module and a second logic module; the data transmission circuit is connected to a host or a slave corresponding to the audio device through the audio interface; The audio device also includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, the steps of the method for realizing a universal transmission interface for audio data as described in any one of claims 1 to 5 are implemented.

7. A computer-readable storage medium, It is characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for realizing a universal transmission interface for audio data according to any one of claims 1 to 5 are implemented.

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