A GPIO pin control system, monitoring method and single-line communication method

Abstract

The present application relates to the field of communication, and in particular to a GPIO pin control system, a monitoring method and a single-line communication method. The system includes an input branch, an output branch, an IO pin and a processor, wherein the output branch includes an output data register; the IO pin is set to an open-drain output mode; the processor is used to monitor the data of the IO pin in real time through the input branch when the IO pin is in an idle state; wherein, when the IO pin is detected to be at a specific level, it is judged that an external device requests to send data, and a fixed value is sent to the output data register to put the IO pin in a receiving state; when the processor needs to send data, the data to be output is directly sent to the output data register to put the IO pin in an output state. The present application utilizes the specific design conventions of the existing GPIO circuit, does not add any functional circuits, improves communication efficiency and pin resource utilization, and is suitable for the design of consumer electronic products that are sensitive to price costs.

Description

Technical Field

[0001] The present application relates to the field of embedded systems and single-chip microcomputer communications, and in particular to a GPIO pin control system, a monitoring method and a single-line communication method. Background Art

[0002] GPIO (General-Purpose input / output) communication is a common communication method in embedded systems and single-chip microcomputers. Its basic principle is to transmit data by controlling the level of a single GPIO pin. These pins can be dynamically configured as input or output by the program, and their status can be controlled by software. This communication method is widely used in various application scenarios, including but not limited to sensor data acquisition, device control, peripheral device communication, etc. Due to its simplicity and flexibility, GPIO single-line communication has become an important communication method in many embedded systems.

[0003] For traditional GPIO pins, a single GPIO pin can only be set to input or output state. Therefore, a single GPIO pin can only be an input pin or an output pin. A single GPIO pin also provides the function of switching between input and output states, but the CPU needs to output multiple instructions to switch, and the switching efficiency is low. Therefore, in scenarios where the communicating parties need to frequently send information to each other, GPIO communication generally requires two data lines, namely, the data line (MOSI) output from the master device to the slave device and the data line (MISO) output from the slave device to the master device. Accordingly, the microcontrollers on the master and slave devices need to occupy two GPIO pins each, set to input and output states respectively, and connect the two data lines respectively.

[0004] However, the pin resources of microcontrollers are very scarce. In order to realize enough functions, the use of each pin needs to be compactly designed. If data communication occupies too many pins, it is easy to cause some other control functions to have insufficient idle pins, or to have to purchase a microcontroller with more pins but higher cost.

[0005] In addition, more pins mean more interconnects, which significantly increases the wiring space of the circuit board and increases the signal interference between the wires. In order to reduce signal interference, more circuit board space and more complex process technology are required, which significantly increases the cost. At the same time, too many connections between communication devices are also a cost, and will increase the chance of being interfered by the outside world and more interference with the outside world.

[0006] The above problems are particularly prominent in the design of price-sensitive consumer electronic products. Therefore, a new GPIO communication protocol is needed to provide a more flexible and efficient way of communication between devices.

[0007] Regarding the above-mentioned related technologies, the inventors believe that the SPI protocol requires four wires, which occupies too many GPIO pins of the device; the general single-wire communication protocol requires the CPU to output multiple instructions and frequently switch the input and output modes of the pins, which is inefficient and slow, and when the GPIO output circuit is working, the input circuit function is idle, there is no effective utilization, and resources are wasted. Summary of the invention

[0008] In order to reduce the required GPIO pins and eliminate the need for GPIO pins to switch input and output states during transmission and reception, so as to make the collision detection communication protocol simple and efficient, the present application provides a GPIO pin control system, a monitoring method and a single-line communication method.

[0009] In order to solve the above problems, the present application provides a GPIO pin control system, a monitoring method and a single-line communication method.

[0010] In a first aspect, the present application provides a GPIO pin control system.

[0011] A GPIO pin control system comprises: an input branch, which listens to and verifies the value corresponding to the level on the GPIO pin as receiving input data; an output branch, which is used to control data output, wherein the output branch comprises an output data register, and the output data register is used to store data sent by a processor; an IO pin, which is connected to the output end of the output branch and the input end of the input branch and is used to connect to an external device, and the IO pin is set to an open-drain output mode; a processor, which is used to monitor the data of the IO pin in real time through the input branch when the IO pin is in an idle state; wherein, when it is monitored that the IO pin is at a specific level, it is judged that the external device requests to send data, and a fixed value is sent to the output data register to put the IO pin in a receiving state; when the processor needs to send data, the data to be output is directly sent to the output data register to put the IO pin in an output state.

[0012] Further, when it is monitored that the IO pin is at a low level, it is determined that the external device requests to send data.

[0013] Furthermore, the processor is also used for: when the IO pin is in the output state, monitoring in real time through the input branch whether the data output by the output branch is correct; if not correct, determining that a data conflict has occurred with the external device.

[0014] Furthermore, the input branch includes: an input drive module, which is used to convert the level state received by the IO pin into a numerical value; an input data register, which is used to store the numerical value corresponding to the level state after processing by the input drive module; and the output branch also includes: an output controller, which receives and outputs the level state converted from the numerical value stored in the output data register according to the open-drain output mode; and an NMOS transistor, which receives and opens and closes according to the data output by the output controller.

[0015] Furthermore, the real-time monitoring of whether the data output by the output branch is correct through the input branch includes: the processor reads the data in the input data register in real time and compares it with the data to be output that has been output by the output branch to determine whether they are consistent. If they are consistent, the data is correct and continues to be sent. If they are inconsistent, the data is incorrect and it is determined that a data conflict has occurred with the external device.

[0016] Furthermore, when the data to be output that has been sent by the processor to the output branch is inconsistent with the data in the input data register, the processor stops sending data to the output branch and reads the data in the input data register in real time.

[0017] Furthermore, the real-time monitoring of the data of the IO pin through the input branch includes: saving the current state of the IO pin; reading the data in the input data register, and the processor monitors the data of the IO pin accordingly, wherein the monitoring result is jointly determined by the data of the IO pin combined with the saved current state of the IO pin.

[0018] Furthermore, saving the current state of the IO pin includes: saving the current pin output state of the IO pin; controlling the output branch to output a high impedance state; reading the actual level of the external device at the IO pin and storing it in the input data register; and restoring the state of the IO pin to the saved current state.

[0019] In a second aspect, the present application provides a monitoring method based on a GPIO pin control system.

[0020] A monitoring method based on a GPIO pin control system comprises: setting an IO pin to an open-drain output mode; when the IO pin is in an output state, a processor reads data of an input branch in real time and compares it with data sent to an output branch to determine whether they are consistent; if they are consistent, the data is correct and the data continues to be sent; if they are inconsistent, the data is incorrect and it is determined that a data conflict has occurred with an external device.

[0021] In a third aspect, the present application provides another monitoring method based on a GPIO pin control system.

[0022] A monitoring method based on a GPIO pin control system comprises: setting an IO pin to an open-drain output mode; when the IO pin is in an idle state, reading data in an input data register, and monitoring the data of the IO pin in real time; wherein, when it is monitored that the IO pin is at a specific level, it is determined that an external device requests to send data, and a fixed value is sent to the output data register to put the IO pin in a receiving state; when the processor needs to send data, the data to be output is directly sent to the output data register to put the IO pin in an output state.

[0023] In a fourth aspect, the present application provides a GPIO single-line communication method.

[0024] A GPIO single-line communication method, a sender and a receiver both include a GPIO pin control system, and the IO pins of the sender and the receiver are connected through a wire.

[0025] The sending method includes: setting a cycle timer; when requesting to send data, the output branch of the sender outputs a specific level to send a signal to enter the output state; when the cycle timer is triggered at the end of timing, the sender enters an interrupt program to monitor the level on the IO pin, and if a low level is read, the IO pin is switched to output a high level; the level on the IO pin is polled, and if a high level is read, the data sending stage is entered.

[0026] The receiving method includes: setting a cyclic timer; when the cyclic timer is triggered at the end of timing, the receiver enters the interrupt program and monitors the level on the IO pin. If a low level is read, it means that the other party has entered the sending state, and the output branch is switched to output a low level; setting a single timer; when the single timer is triggered at the end of timing, a high level is output to send a signal that the handshake is completed; and entering the data receiving stage.

[0027] In summary, the present application utilizes the specific design conventions of the existing GPIO circuit, does not add any functional circuit, independently designs the communication protocol, and implements it purely in software, which cleverly solves the problems of low efficiency and waste of pin resources in traditional GPIO communication. By using the GPIO single-line communication method, the communication efficiency is significantly improved and the GPIO pin resources are saved, which is suitable for application scenarios with tight pin resources. The processor can monitor the data of the IO pin in real time, including the status of the external device and the correctness of the output data, thereby ensuring the reliability of the system operation. The monitoring method and the single-line communication method provided simplify the design and implementation process, and are easy to integrate and apply in embedded systems. By real-time monitoring and controlling data transmission, communication failures caused by data errors are reduced, and the reliability, stability and efficiency of the system are improved. In addition, since the system has a low demand for hardware resources, it is suitable for the design of price-sensitive consumer electronic products, thereby reducing the overall cost. In addition, the present application sends a fixed value (such as setting 1, etc.) to the output data register to put the IO pin in a receiving state; or directly sends the data to be output to the output data register to put the IO pin in an output state; so that the switching between the receiving and output states does not require the setting of the mode register, which is simple, fast and efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is the structure diagram of the GPIO pin control system for this application;

[0029] Figure 2 A flowchart for verifying whether the input branch and output branch of the GPIO pin can work in parallel;

[0030] Figure 3 System structure diagram for dual devices using GPIO pins for single-wire communication;

[0031] Figure 4 This is the GPIO single-line communication handshake flow chart;

[0032] Figure 5 This is the main flow chart of GPIO single-line communication;

[0033] Figure 6 A timer interrupt function flow chart for GPIO single-wire communication;

[0034] Figure 7 Flowchart for saving the current status of IO pins for GPIO single-wire communication;

[0035] Figure 8 It is the relationship diagram between the drain output state of the NMOS transistor in the output branch of each device A and B and the actual level of the IO pin;

[0036] Fig. 9Another timer interrupt function flow chart for GPIO single-wire communication;

[0037] Fig.10 Create a new receive line flow chart for GPIO single-line communication. DETAILED DESCRIPTION

[0038] The following is a detailed description of the embodiments of the present application in conjunction with the drawings in the specification, but the embodiments should not be construed as limiting the present application.

[0039] like Figure 1 As shown, Figure 1 1 is a schematic diagram of the GPIO pin control system structure of the present application. The GPIO pin control system includes an input branch 101, an output branch 102, an IO pin 103 and a processor 117, wherein the IO pin 103 is connected to the output end of the output branch 102 and the input end of the input branch 101, and is used to connect to an external device.

[0040] The output branch 102 includes an output data register 104 and an output driver module 106. The output data register 104 and the output driver module 106 are sequentially connected in series between the processor 117 of the device and the IO pin 103. The processor 117 of the device can be, for example, a CPU (central processing chip). The output data register 104 is used to store the output data sent by the processor, and the output driver module 106 is used to output high and low levels according to the data in the output data register 104.

[0041] The output data register 104 receives the data to be output from the processor 117, and also receives the data from the bit set / clear register. The processor 117 can read the content of the output data register 104 to obtain the last written data value; the bit set / clear register 116 is used to operate a certain port (bit) of the output data register 104. The output driver module 106 includes an output controller 108, and a PMOS transistor 109 and an NMOS transistor 110 (MOS: the abbreviation of MOSFET, referring to metal-oxide semiconductor field effect transistor) controlled by the output controller 108. One end of the source of the PMOS transistor 109 is connected to the positive power supply VDD, the other end is connected to the IO pin 103, and the gate is connected to the output end of the output controller 108; one end of the source of the NMOS transistor 110 is connected to the negative power supply VSS, the other end is connected to the IO pin 103, and the gate is connected to the output end of the output controller 108. The output controller 108 determines the output mode according to the mode bit in the configuration register, and controls the gate voltage output to the PMOS transistor 109 and the NMOS transistor 110 according to the output data in the output data register 104. The NMOS transistor 110 is turned on at a high level and disconnected at a low level, and can be used to control the conduction with VSS; the PMOS transistor 109 is turned on at a low level and disconnected at a high level, and can be used to control the conduction with VDD (as described below, in the open-drain output mode, the PMOS transistor 109 remains non-conductive). Through the above steps, the data in the output data register 104 is output through the IO pin 103.

[0042] The input branch 101 includes an input data register 105 and an input driver module 107. The input data register 105 and the input driver module 107 are sequentially connected in series between the processor 117 and the IO pin 103. The input driver module 107 is used to input the data received by the IO pin 103 to the input data register 105 according to the high and low levels of the IO pin 103. The input data register 105 is used to store the received input data for the processor 117 to read.

[0043] The input driver module 107 includes a Schmitt trigger 111, a pull-up resistor R1 and a pull-down resistor R2. The Schmitt trigger 111 is used to convert the analog signal received by the IO pin 103 into a digital signal. The pull-up resistor R1 is connected to the positive power supply VDD through the switch K1, and the pull-down resistor R2 is connected to the negative power supply VSS through the switch K2. With the opening or closing of the switch K1 and the switch K2, the pull-up resistor R1 and the pull-down resistor R2 can limit the normal potential of the IO pin 103 to a high level or a low level.

[0044] The processor 117 includes a monitoring module 118, which is used to monitor the data of the IO pin in real time through the input branch when the IO pin is in an idle state, wherein when the IO pin is monitored to be at a specific level, it is determined that the external device requests to send data. For example, when the IO pin is monitored to be at a low level, it is determined that the external device requests to send data. It can be understood that the specific level can also be a high level, that is, both high and low levels are within the protection scope of this application.

[0045] Then, the processor 117 sends a fixed value to the output data register (for example, it sends data 1 to the output data register to directly set the output data register to 1, or it can send data 0 to the output data register, output a low level, and directly pull it down). Pulling it down is a handshake, and the hand is pulled back when the single timer is triggered. Only then can it be in a high-impedance state, and then it can receive data.

[0046] So that the NMOS is in the disconnected state, the IO pin is floating in a high impedance state, and the IO pin is in the receiving state. When the processor needs to send data, it directly sends the data to be output to the output data register (without any input and output state instructions). These data will control the NMOS to switch between the on and off states, so that the IO pin is in the output state, and can switch between the high level and the low level to output data 0 or 1. When the IO pin is in the output state, the processor 117 monitors the data output by the output branch in real time through the input branch to see if it is correct. If it is not correct, it is judged that a data conflict has occurred with the external device. This monitoring module 118 can be a set software program or a physical module in the circuit.

[0047] When using GPIO single-line communication, it is easier to think of using the time-division multiplexing method to achieve single-line communication by switching the input mode and the output mode. However, this method requires frequent switching of the input or output mode of the pin when sending and receiving data changes, and each time the input or output mode is switched, the CPU needs to consume multiple instructions, resulting in low efficiency and slow switching speed. Based on the time-division multiplexing method, the present application combines the method of monitoring IO pin data, and only needs to set the output data register to 1 to put the IO pin in a receiving state; or directly send the data to be sent to the output data register without any instructions, so that the IO pin can be put in an output state; or in the receiving state, if the IO pin data does not change for a long time (for example, setting a fixed value), the IO pin can be put in an idle state; or in the output state, the IO pin can be put in an idle state after the output is completed; thus, the switching between the various states of the IO pin does not require instructions (the output data register needs to be set to 1 only when switching to the receiving state), which can save a lot of instructions, improve the response speed, reduce communication delay, reduce redundancy and improve communication efficiency. In addition, in the related art, when the GPIO output branch is working, the input branch function is idle, not effectively utilized, and resources are wasted. However, in the present application, when the output branch is working, the input branch is used to monitor whether the output of the output branch is correct, thereby making the communication process more stable and reliable and effectively integrating and utilizing resources.

[0048] from Figure 1 It can be seen from the circuit that the input data register 105 and the output data register 104 are independent of each other, which means that when the processor 117 outputs data to the output data register 104, it can also read data from the input data register 105 at the same time, and the input branch 101 and the output branch 102 are implemented in parallel. Figure 1 The right side is gathered to the same IO pin 103, the input level and the output level are the same at the IO pin 103, and there is no switch controlling the unidirectional conduction. Therefore, it can be judged from the physical connection that the input branch 101 and the output branch 102 can work in parallel.

[0049] Figure 2 It is a flow chart for verifying whether the input branch and the output branch of the GPIO pin can work in parallel.

[0050] GPIO pins have multiple working modes, one of which is open-drain output mode. When the GPIO pin is configured to open-drain output mode, the PMOS transistor is not turned on, and the NMOS transistor works in a conducting or non-conducting state under the control of the output controller, so that the GPIO pin outputs a certain voltage level. The specific communication process is described as follows. The processor stores the data to be output into the output data register, and the output data register outputs the data to the output controller. The output controller receives and outputs the level state (low level and high impedance state) converted to by the above output data register value according to the open-drain output mode, that is, the output mode is judged to be the open-drain output mode according to the configuration register, and the conduction of the NMOS transistor is controlled by outputting different voltages, thereby controlling the level of the GPIO output. When the value in the output data register is 1, the controller outputs a low level, so that the gate voltage of the NMOS transistor is low, the NMOS transistor is not turned on, and the GPIO pin is in a high-impedance state. It is possible to output a high level generated by the pull-up resistor, or it is possible to output a low level determined by the external device; when the value in the output data register is 0, the controller outputs a high level, the NMOS transistor is turned on, and the GPIO pin outputs a low level determined by VSS.

[0051] In the general GPIO design, the input signal is input from the IO pin, and the received analog signal is converted into a digital signal through the Schmitt trigger and sent to the input data register; the output data register sends the digital signal to the output controller, which controls the conduction of the NMOS transistor to generate an output signal and output it to the IO pin. It can be seen that the input data register and the output data register are both connected to the IO pin in the logic circuit. In the absence of external signals, the data in the input data register is consistent with the data in the output data register.

[0052] In order to check whether the processor can read the value of the GPIO output data register through the GPIO input data register in the open-drain output mode, the inventor designed the following method for verification. Using the Qinheng CH32V208WBU8 evaluation board and GDB (GNU Debugger) for debugging, it can be easily operated in the IDE memory window. The specific operation includes the following steps:

[0053] S100, set an LED indicator light, one pin of which is connected to the positive power supply through a current limiting resistor, and the other pin is connected to one of the PAO pins of the Qinheng CH32V208WBU8 chip on the evaluation board. The voltage output by PA0 is high or low, which is determined by the end value in the input data register 0x4001080c. When the end value in the input data register 0x4001080c is 0, the PA0 pin outputs a low level, and when the end value in the input data register 0x4001080c is 1, the PA0 pin outputs a high level.

[0054] S200, configure the GPIO pin of the chip to an open-drain output mode. In common understanding, in this mode, the output branch works, and the input branch does not work or the working state is unknown.

[0055] S300, set the last bit of the output data register to 0, read GPIOA INDR, and check whether the zeroth bit is 0. At this time, LED1 lights up. GPIOA OUTDR is the value of the output data register, and GPIOA INDR is the value of the input data register.

[0056] S400, set the last bit of the output data register to 1, read GPIOA INDR, and check whether the zeroth bit is 1. At this time, LED1 is off.

[0057] S500, set the last bit of the output data register to 0 again, read GPIOA INDR, and check whether the zeroth bit is 0. At this time, LED1 is on again.

[0058] From the above process, it can be seen that although the GPIO pin is set to output mode instead of input mode, the pin level can still be correctly read from the input data register. This shows that, at least in open-drain output mode, the input circuit and the output circuit work in parallel. Even if it is configured in output mode on the surface, the input circuit is still operating normally and can be used normally. This makes it possible for the same GPIO port to be used as both an input port and an output port. Based on this, the system described below can be designed in which two devices use GPIO pins for communication.

[0059] Figure 3 This is a system structure diagram of two devices using GPIO pins to communicate. This application takes two-device communication as an example. Those skilled in the art can transform it into multi-machine communication as needed, and the transformation process does not require creative labor. Figure 3As shown, both device A and device B adopt the GPIO pin control system described above in this application. Between device A and device B, each uses only one GPIO pin for data communication. The GPIO pins of both devices are configured as open-drain output mode. A pull-up resistor R3 is configured between the IO pins of device A and device B, and the pull-up resistor R3 can be set on device A or device B.

[0060] The following describes how device A and device B achieve single-line communication through GPIO pins when using open-drain output mode.

[0061] When neither device A nor device B outputs data, the output data registers 311 and 321 are both set to 1, the output controller 312 outputs a low level to the gate of the NMOS transistor 313, and the output controller 322 outputs a low level to the gate of the NMOS transistor 323. At this time, both the NMOS transistors 313 and 323 are not turned on, and the level of the IO pin 301 is a high level determined by the pull-up resistor R3.

[0062] When device A needs to output data and device B does not output data, when device A outputs data 1, device A stores data 1 in the output data register 311, and the output controller 312 outputs a high level to the gate of the NMOS transistor 313 according to the data 1 in the output data register 311. At this time, the NMOS transistor 313 is not turned on, and the level of the IO pin 301 is a high level determined by the pull-up resistor R3; when device A outputs data 0, device A stores data 0 in the output data register 311, and the output controller 312 outputs a low level to the gate of the NMOS transistor 313 according to the data 0 in the output data register 311. At this time, the NMOS transistor 313 is turned on, and the level of the IO pin 301 is a low level determined by VSS.

[0063] It can be understood that at this time, device A is the sender, and the monitoring module 118 monitors in real time whether the output data of the processor through the output branch is correct. In device A, the input branch receives the level of the IO pin 301 in real time through the input driver module and stores it in the input data register. The processor reads the data in the input data register in real time and compares it with the data to be output sent to the output branch (specifically, the processor reads the data in the input data register in real time and compares it with the data to be output that has been output by the output branch) to determine whether they are consistent. If they are consistent, they are correct, and if they are inconsistent, they are incorrect. When the data sent by the processor to the output branch is consistent with the data in the input data register, it means that the communication is normal and can continue to work; when the data sent by the processor to the output branch is inconsistent with the data in the input data register, it is determined that a data conflict has occurred with device B (an instance of an external device), indicating that the external device needs to send information at this time, and the processor stops sending data to the output branch and reads the data in the input data register in real time (or solves it according to other collision solutions, which will be described in detail in the detection and resolution of collisions later). For example, when the data sent by the processor of device A to the output branch is 1, and the data in the real-time read input data register is also 1, it continues to work normally; when the data sent by the processor of device A to the output branch is 1, and the data in the real-time read input data register is 0, it is inconsistent, which means that device B has sent a low-level signal at this time, and there may be a data output requirement. The processor of device A can stop sending data to the output branch, and change from a sender to a receiver, and read the data in the input data register in real time.

[0064] It can be understood that, correspondingly, when device A is the sender and device B is the receiver, the monitoring module 118 monitors the state of device A (an instance of an external device) at the IO pin 103 in real time. In device B, after saving the current state of the IO pin, the data in the input data register is read, and the processor monitors the data of the IO pin accordingly, wherein the monitoring result is jointly determined by the data combination of the IO pin and the current state of the IO pin saved; for example, if the data of the IO pin is 0 and the current state of the saved IO pin is 1, the monitoring result is that device A makes a request to send; if the data of the IO pin is 1 and the current state of the saved IO pin is 0, the monitoring result is that device B makes a request to send itself. Among them, the main function of saving the current state of the IO pin is to save the existing output state and restore the existing output state after monitoring, specifically including: saving the current pin output state of the IO pin; controlling the output branch to output a high impedance state; reading the actual level of the external device at the IO pin and storing it in the input data register; restoring the state of the IO pin to the current pin output state. When device B has a need to send data and needs to switch from a receiver to a sender, it can send a demand signal such as a continuous low level in the output branch to remind device A to switch to a receiver.

[0065] It can be understood that when device A and device B are not connected, the IO pins of device A and device B are in an idle state, that is, the idle state indicates that the link is not established and the link establishment has not started. The monitoring module in device A is used to monitor the state of device B at the IO pin in real time, and the monitoring module in device B is used to monitor the state of device A at the IO pin in real time, so that the communication connection can be successfully completed when either party initiates the task of establishing a connection; when device A and device B have established a connection, for example, when device A is the sender and device B is the receiver, the monitoring module in device A is used to monitor in real time whether the output data of the processor through the output branch is correct, and the monitoring module in device B is used to receive information sent by device A in real time.

[0066] Similarly, when device B needs to output data and device A does not output data, the communication process is similar to the above.

[0067] When device A outputs data first and device B outputs data later, that is, device B has a need to send data and needs to be converted from a receiver to a sender. For example, when device A outputs data 1 first, device A stores data 1 in output data register 311, and output controller 312 outputs a high level to the gate of NMOS transistor 313 according to data 1 in output data register 311. At this time, NMOS transistor 313 is not turned on, and the level of IO pin 301 is a high level determined by pull-up resistor R3. At this time, device B outputs data 0, device B stores data 0 in output data register 321, and output controller 322 outputs a low level to the gate of NMOS transistor 323 according to data 0 in output data register 321. At this time, NMOS transistor 323 is turned on, and the level of IO pin 301 is a low level determined by VSS. At this time, the data sent by the processor of device A to the output branch is 1, and the data in the input data register read in real time is 0, which is inconsistent. This means that device B has sent a low-level signal at this time, and there may be a data output requirement. The processor of device A can stop sending data to the output branch, and change from a sender to a receiver, and read the data in the input data register in real time; or other solutions such as the collision detection mechanism and the collision solution method will be described in detail below.

[0068] Similarly, when device B outputs data first and device A outputs data later, the communication process is similar to the above.

[0069] Figure 4 This is a dual-device GPIO single-line communication handshake flow chart. Figure 5 , Figure 6 This is the main flow chart of dual-device GPIO single-line communication and the timer interrupt function flow chart. Figure 4 , Figure 5 , Figure 6 As shown, the steps for two devices to establish a connection by handshaking twice are as follows:

[0070] Step (1), establish an idle link state. When neither device A nor device B sends data, set the pin output to a high impedance state, the output data register of the GPIO output circuit is set to data 1, and the NMOS transistors of both machines are not turned on. At this time, the GPIO pin of the single-line communication is affected by the weak pull-up resistor and outputs a high level. Set the handshake state to 0. The handshake state is used to determine the progress of the handshake connection. At this time, after the system is initialized, the processors of device A and device B both set a cyclic timer with a fixed interval, and the fixed interval time of the two devices may be inconsistent. The timer repeatedly triggers an interrupt and executes the process included in the interrupt program: read the input data register to determine whether the IO pin is low level (that is, device A and device B each monitor the status of the external device at the IO pin in real time). The periodic query process lasts for a very short time, which is the length of time that can correctly read the level pulled down by machine B, and basically does not consume the processor execution time. The fixed time interval between two queries is relatively long, and varies according to the different requirements for the transmission delay, and is usually set in milliseconds or seconds. For example Figure 6 As shown, the execution process of the interrupt program in the idle connection state is as follows.

[0071] It is understandable that the process of saving the current state of the IO pin can be specifically the following method, such as Figure 7 As shown, save the pin status at this time, then set the output data register value to 1, the NMOS transistor is not turned on, the GPIO pin is floating in a high-impedance state, and the pin status is read in at this time. After the reading is completed, the pin is restored to the state saved before the interrupt is triggered. At this time, the pin level read in the process of saving the current state of the IO pin is judged. If the state at the IO pin is detected to be high, it means that the other party’s hand signal has not been received (the other party has no intention to send data). Then judge whether it is in handshake state 2. If it is not in handshake state 2, exit the interrupt program, return to the original other program that was interrupted, and continue to run. At this time, except for the time when the interval time is reached, the device A or device B triggers an interrupt to execute once to monitor the other party’s hand signal, and other times are still executing other non-GPIO communication programs, and the interrupt program basically does not consume processor execution time.

[0072] like Figure 8 As shown, in the GPIO open-drain output mode of both communicating parties, the relationship between the output circuit NMOS transistor drain output state and the actual level of the two IO pins and the metal connection between them is as follows.

[0073] If the output data register of one party is set to 1, the drain of the NMOS transistor in the output circuit is floating, and in the high-impedance state, the output may not be 1, depending on the external weak pull-up and the other party. If the drain of the other party's NMOS transistor is floating and is also in a high-impedance state, under the action of the pull-up resistor, the metal pins of both parties and the metal connection between them are all high level; if the other party's NMOS transistor is turned on and the drain is grounded, the pull-up resistor carries all the voltage difference between the power supply and the ground, and the metal pins of both parties and the metal connection between them are all low level.

[0074] If the output data register of one party is set to 0, the NMOS transistor of the output circuit is turned on, the drain is grounded, and the pull-up resistor carries all the voltage differences between the power supply and the ground. Regardless of whether the drain output state of the NMOS transistor of the other party's GPIO output circuit is on or high resistance, the metal pins of both parties and the metal connections between them are all at a low level.

[0075] Step (2), the sender reaches out, such as Figure 4 , Figure 5 As shown, when device A wants to send data, the pin outputs a specific level. It can be understood that the specific level here can be a low level or a high level, as long as it can be used to inform the external device to initiate the hand-reaching information, and this application does not limit it here. Specifically, the output data register value of device A is set to 0, and the output controller of device A outputs a high level to the gate of the NMOS transistor of device A according to the data 0 in the output data register of device A. At this time, the NMOS transistor of device A is turned on, the drain is grounded, and the pin outputs a low level, sending a signal to device B, and changing the handshake state to 1 at the same time.

[0076] Step (3), the receiver shakes hands, such as Figure 4 , Figure 6 As shown in the figure, when the cycle timer of device B reaches the interval time, an interrupt is triggered and the cycle timer interrupt program is executed. After device B saves the current state of the IO pin, it reads the data in the input data register. If it is 0, that is, when device B detects that the state of device A at the IO pin is low, it means that the first hand-reaching signal sent by device A is detected, and it is understood that device A needs to send data. The handshake state is changed to 2, indicating the combined state of the receiver's handshake and the receiver's hand-reaching.

[0077] Step (4), the receiver reaches out, such as Figure 4 , Figure 6As shown, after the handshake state of device B is changed to 2, the output data register value of device B is set to 0. The output controller of device B outputs a high level to the gate of the NMOS transistor in device B according to the data 0 in the output data register of device B. At this time, the NMOS transistor in device B is turned on, the drain is grounded, and the pin outputs a low level, sending a hand-reaching signal to device A. Then, device B sets a new single timer, and the time interval is slightly longer than the timer time set by device A in step (1) (the specific length is based on whether device A can accurately receive the second hand-reaching signal after the interrupt program responds). Before the single timer time is reached, the processor of device B continues to run other programs, and the interrupt program does not consume the processor execution time.

[0078] Step (5), the sender shakes hands, such as Figure 4 , Figure 6 As shown in the figure, when the cycle timer of device A reaches the interval time, an interrupt is triggered and the cycle timer interrupt program is executed. After device A saves the current state of the IO pin, it reads the data in the input data register. If it is 0, it means that the state of device B at the IO pin is low (the output data register of device B is set to 0 at this time). At this time, device A receives the hand-reaching signal from device B, that is, the sender handshakes successfully, and device A changes the handshake state to 3.

[0079] Step (6), the sender withdraws his hand, such as Figure 4 , Figure 6 As shown, after device A changes the handshake state to 3, the output data register is set to 1, the drain of the NMOS transistor is open, the IO pin is in a high impedance state and floats, and no longer outputs a low level. At this time, device A withdraws its hand, that is, the sender withdraws its hand. Turn off the cycle timer, and start to continuously poll whether the input data register is 1, waiting for the receiver to withdraw its hand. When device A polls the input high level, the handshake state is changed to 5, indicating that the receiver withdraws his hand, and the data is sent in the order of the start bit, data bit, check bit, and stop bit of the serial communication protocol. When sending each bit of data, the data in the input data register is read in real time. This data is the output data of the output branch. The processor compares the data sent to the output branch with the output data of the output branch to determine whether the data input by the processor is consistent with the output data of the output branch. This operation can be implemented by software or the value of the input data register can be written into the memory by DMA hardware, and a unified comparison and verification is performed after a certain amount of data is transmitted. After the transmission is completed, the pin state is changed to a high impedance state, and the handshake state returns to the initial state 0.

[0080] Step (7): There are two different design schemes for this step, which are referred to as Design Scheme 1 and Design Scheme 2 below.

[0081] Design scheme 1: The receiver withdraws his hand, such as Figure 4 , Figure 6As shown, when the time interval of the single timer of device B arrives, an interrupt is triggered and the cyclic timing interrupt program is executed. After device B performs the process of saving the current state of the IO pin, it reads the data in the input data register. At this time, the data is detected to be 1, that is, the state of device A at the IO pin is detected to be high level, and the handshake state is judged to be 2, then the output data register is set to 1, the drain of the NMOS transistor is open, the IO pin is floating in a high impedance state, and no longer outputs a low level. At this time, device B withdraws its hand, changes the handshake state to 4, and changes the pin output to a high impedance state, that is, the receiver withdraws his hand. Then the processor of device B stops running all other programs and focuses on repeatedly reading and processing the value of the input data register, that is, real-time monitoring of the state of device A at the IO pin. At this time, the single-line communication program exclusively executes the processor to read and save data. When a continuous high level is received, it means that the other party has completed the transmission, and the handshake state is changed to return to the initial state 0.

[0082] Design solution 2: The receiver withdraws his hand, such as Figure 4 , Fig. 9 As shown, when the single timer time interval of device B arrives, an interrupt is triggered and the cyclic timing interrupt program is executed. After device B performs the process of saving the current state of the IO pin, it reads the data in the input data register. At this time, the data is detected to be 1, that is, the state of device A at the IO pin is detected to be high level, and the handshake state is judged to be 2, so the output data register is set to 1, the drain of the NMOS transistor is open, and the IO pin is floating in a high-impedance state, and no longer outputs a low level. At this time, device B withdraws its hand and changes the handshake state to 4, and changes the pin output to a high-impedance state, that is, the receiver withdraws its hand. Then device B creates a new data receiving thread, as shown in Fig.10 As shown, it is used to repeatedly read and process the value of the input data register. At this time, the data receiving thread is executed in multiple threads together with other threads. When reading and saving data, the data sending process or other non-GPIO communication programs can also be performed. When a continuous high level is received, it means that the other party has completed the sending, and the handshake state returns to the initial state 0.

[0083] In Solution 2, the receiver is multi-threaded when receiving data, so there will be a situation where the receiving process is not completed but data needs to be sent. At this time, the original receiver and the original sender send data at the same time, which will cause communication confusion. It is necessary to develop a collision detection mechanism and a collision solution. The collision solution is described below.

[0084] First, it is necessary to detect whether a collision occurs during the communication process. During the data transmission and reception stage between device A and device B, the data received by the input branch is monitored and compared with the data to be output. If the two are inconsistent, a collision is determined to have occurred.

[0085] After a collision occurs and is detected, the collision should be resolved. For example, device A and device B can each generate a random number as the delay time, so that the delay time of both parties is inconsistent, thereby avoiding sending data at the same time again.

[0086] After collision detection and collision resolution, during normal data transmission and reception, when the receiver needs to send high-priority data, for example, when the receiver needs to send information related to communication control. This communication control-related information includes returning an ACK frame (acknowledgement frame, indicating that the receiver has received the data) to the sender to confirm the received data. The sender uses this as a basis to release the memory space occupied by the confirmed received data in the retransmission mechanism buffer; when the receiver's buffer is full or the receiver's data processing capacity is insufficient, the receiver sends a request to request the sender to slow down, or when the receiver's pressure is relieved, request the sender to speed up. At this time, the following two solutions are set.

[0087] Solution 1: The receiver and the sender use the only signal line in time-sharing mode. The receiver takes advantage of the sender's transmission gap and uses one line as two lines to maximize the use of resources. The receiver monitors the input data register. If a continuous high level is read, it means that the sender is in a pause period, and an ACK frame is sent at this time. If the sender continuously sends data, the timeout timer is set and waits for the sender to send a pause. After the sender pauses and the timeout triggers, an ACK frame is sent. The sender monitors the input data register and finds that the receiver is sending data and is in a pause stage. At this time, it starts to receive the data sent by the receiver. If the sender needs to send data when receiving the data sent by the receiver, the sender will suspend the action of sending data.

[0088] Solution 2: When the receiver needs to send data, the receiver will continuously output a low level on the pin, and then start sending an ACK packet after a period of time.

[0089] When the sender is sending a high level, if it detects a continuous low level in the input data register (the duration of which is determined by the receiver), it means that the other party is seizing the priority and a priority collision is detected. At this time, the sender and the receiver can remember the location of the successfully sent data for future breakpoint resumption. Then, the sender stops sending data and starts receiving ACK packets. After receiving the ACK packet, it restarts the sending process through the successfully sent data location remembered above for breakpoint resumption.

Claims

1. A GPIO pin control system, characterized in that: include: The input branch listens to and verifies the value corresponding to the level on the GPIO pin as receiving input data; An output branch, used to control data output, wherein the output branch includes an output data register, and the output data register is used to store data sent by the processor; An IO pin, connected to the output end of the output branch and the input end of the input branch, and used to connect to an external device, and the IO pin is set to an open-drain output mode; A processor, configured to monitor data of the IO pin in real time through the input branch; When it is detected that the IO pin is at a specific level, it is determined that the external device requests to send data, and a fixed value is sent to the output data register to put the IO pin in a receiving state; When the processor needs to send data, the processor directly sends the data to be output to the output data register, so that the IO pin is in an output state; Wherein, the input branch includes: An input driver module, used to convert the level state received by the IO pin into a numerical value; An input data register, used to store a value corresponding to the level state after being processed by the input drive module; Furthermore, the output branch further comprises: an output controller, receiving and outputting the level state converted from the value stored in the output data register according to the open-drain output mode; An NMOS transistor receives and turns on and off according to data output by the output controller; Wherein, the real-time monitoring of the data of the IO pin through the input branch includes: Save the current state of the IO pin; The data in the input data register is read, and the processor monitors the data of the IO pin accordingly, wherein the monitoring result is jointly determined by the data of the IO pin combined with the current state of the saved IO pin.

2. The GPIO pin control system according to claim 1, characterized in that: in, When it is detected that the IO pin is at a low level, it is determined that the external device requests to send data.

3. The GPIO pin control system according to claim 1, characterized in that: The processor is further configured to: When the IO pin is in the output state, the input branch is used to monitor in real time whether the data output by the output branch is correct. If it is not correct, it is determined that a data conflict occurs with the external device.

4. The GPIO pin control system according to claim 1, characterized in that: The real-time monitoring of whether the data output by the output branch is correct through the input branch includes: The processor reads the data in the input data register in real time and compares it with the data to be output that has been output by the output branch to determine whether they are consistent. If they are consistent, they are correct and continue to be sent. If they are inconsistent, they are incorrect and it is determined that a data conflict has occurred with the external device.

5. The GPIO pin control system according to claim 4, characterized in that: When the to-be-output data sent by the processor to the output branch is inconsistent with the data in the input data register, the processor stops sending data to the output branch and reads the data in the input data register in real time.

6. The GPIO pin control system according to claim 1, characterized in that: The saving of the current state of the IO pin comprises: Save the current pin output state of the IO pin; Controlling the output branch to output a high impedance state; Read the actual level of the external device at the IO pin and store it in the input data register; The state of the IO pin is restored to the saved current state.

7. A monitoring method for the GPIO pin control system according to any one of claims 1 to 6, characterized in that: include; Set the IO pin to open-drain output mode; When the IO pin is in the output state, the processor reads the data of the input branch in real time and compares it with the data sent to the output branch to determine whether they are consistent. If they are consistent, it is correct and continues to be sent. If they are inconsistent, it is incorrect and it is determined that a data conflict has occurred with the external device.

8. A monitoring method for the GPIO pin control system according to any one of claims 1 to 6, characterized in that: include; Set the IO pin to open-drain output mode; When the IO pin is in an idle state, reading the data in the input data register, and monitoring the data of the IO pin in real time; When it is detected that the IO pin is at a specific level, it is determined that the external device requests to send data, and a fixed value is sent to the output data register to put the IO pin in a receiving state; When the processor needs to send data, the data to be output is directly sent to the output data register, so that the IO pin is in an output state.

9. A sending method for single-wire communication based on the GPIO pin control system according to any one of claims 1 to 6, characterized in that: The sender and the receiver both include a GPIO pin control system set to an open-drain output mode, and the IO pins of the sender and the receiver are connected by a wire. The sending method includes: Set a loop timer; When requesting to send data, the output branch of the sender outputs a specific level to send a signal to enter the output state; When the cycle timer is triggered, the sender enters the interrupt program to monitor the level on the IO pin. If a low level is read, the IO pin is switched to output a high level. Poll the level on the IO pin. If a high level is read, enter the data sending phase.

10. A receiving method for single-wire communication based on the GPIO pin control system according to any one of claims 1 to 6, characterized in that: The sender and the receiver both include a GPIO pin control system, and the IO pins of the sender and the receiver are connected by a wire, and the receiving method includes: Set a loop timer; When the cycle timer is triggered, the receiver enters the interrupt program and monitors the level on the IO pin. If a low level is read, it means that the other party has entered the sending state and switches the output branch to output a low level. Set a one-shot timer; When the one-shot timer is triggered after timing, it outputs a high level to send a signal that the handshake is completed; Enter the data receiving phase.

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