Method and device for adjusting pixel clock

Abstract

The embodiment of the present invention provides a method and device for adjusting pixel clock, including: obtaining a first pixel clock, the first pixel clock is a clock obtained by compensating the theoretical pixel clock of the transmitting end through the relative deviation between the crystal oscillator of the transmitting end and the crystal oscillator of the synchronization device; determining the maximum adjustment range value and the single-step maximum adjustment value supported by the pixel clock of the receiving end; continuously outputting N signals according to a preset period, and when the actual time of the outputted i-th signal meets the preset conditions, adjusting the first pixel clock for the jth time according to the maximum adjustment range value and the single-step maximum adjustment value, N is an integer greater than 1, and i and j are integers greater than or equal to 1 and less than or equal to N. The present invention solves the problem in the related art that the clock phase-locked loop of the receiving end is unlocked due to the fact that the tolerance of the clock phase-locked loop of the receiving end is not considered when adjusting the clock of the transmitting end.

Description

Technical Field

[0001] The embodiments of the present invention relate to the communication field, and in particular, to a method and device for adjusting a pixel clock. Background Art

[0002] In a distributed display system, it is usually necessary to adjust the clock of the transmitter. In the prior art, when adjusting the clock of the transmitter, the tolerance of the clock phase-locked loop of the receiver is not considered.

[0003] However, the tolerance levels of the clock phase-locked loops of different receiving ends are different. Adjusting the clock of the sending end without limiting the adjustment range can easily cause the clock phase-locked loop of the receiving end to lose lock, resulting in problems such as no picture, black screen or flickering screen.

[0004] There is currently no effective solution to the above problems. Summary of the invention

[0005] The embodiments of the present invention provide a method and device for adjusting pixel clock, so as to at least solve the problem in the related art that the clock phase-locked loop of the receiving end is unlocked due to the adjustment of the clock of the transmitting end without considering the tolerance of the clock phase-locked loop of the receiving end.

[0006] According to one embodiment of the present invention, there is provided a method for adjusting a pixel clock, comprising: obtaining a first pixel clock, wherein the first pixel clock is a clock obtained by compensating a theoretical pixel clock of a transmitting end through a relative deviation between a crystal oscillator of the transmitting end and a crystal oscillator of a synchronization device; determining a maximum adjustment range value and a single-step maximum adjustment value supported by the pixel clock of a receiving end; and continuously outputting N signals according to a preset period, and when the actual time of the outputted ith signal satisfies a preset condition, adjusting the first pixel clock for a jth time according to the maximum adjustment range value and the single-step maximum adjustment value, wherein N is an integer greater than 1, and i and j are integers greater than or equal to 1 and less than or equal to N.

[0007] In an exemplary embodiment, when N signals are continuously output according to a preset period and the actual time of the output ith signal satisfies a preset condition, the first pixel clock is adjusted for the jth time according to the maximum adjustment range value and the single-step maximum adjustment value, including: obtaining the theoretical time and the actual time of the ith signal; determining the difference between the theoretical time and the actual time as a first time difference; and when the first time difference is greater than or equal to a preset clock threshold, adjusting the compensated pixel clock according to the maximum adjustment range value and the single-step maximum adjustment value.

[0008] In an exemplary embodiment, the compensated pixel clock is adjusted according to the maximum adjustment range value and the single-step maximum adjustment value, including: obtaining the cycle length of the preset cycle; determining an adjusted pixel clock according to the cycle length, the first time difference, and the first pixel clock; obtaining a target pixel clock according to the adjusted pixel clock and a pixel clock obtained by performing the j-1th adjustment on the first pixel clock; and adjusting the first pixel clock according to a relationship between the adjusted pixel clock and the single-step maximum adjustment value, and a relationship between the target pixel clock and the maximum adjustment range value.

[0009] In an exemplary embodiment, the first pixel clock is adjusted according to the relationship between the adjusted pixel clock and the single-step maximum adjustment value, and the relationship between the target pixel clock and the maximum adjustment range value, including: determining the difference between the target pixel clock and the first pixel clock as the first pixel clock difference; and when the first pixel clock difference is less than or equal to the maximum adjustment range value, adjusting the first pixel clock according to the relationship between the adjusted pixel clock and the single-step maximum adjustment value.

[0010] In an exemplary embodiment, when the first pixel clock difference is less than or equal to the maximum adjustment range value, the first pixel clock is adjusted according to the relationship between the adjusted pixel clock and the single-step maximum adjustment value, including: when the first pixel clock difference is less than or equal to the maximum adjustment range value, and the adjusted pixel clock is greater than the single-step maximum adjustment value, adjusting the first pixel clock to the single-step maximum adjustment value; when the first pixel clock difference is less than or equal to the maximum adjustment range value, and the adjusted pixel clock is less than or equal to the single-step maximum adjustment value, adjusting the first pixel clock to the adjusted pixel clock.

[0011] In an exemplary embodiment, the method further includes: when the first pixel clock difference is greater than the maximum adjustment range value, determining the sum of the maximum adjustment range value and the first pixel clock difference as a boundary pixel clock; determining the difference between the boundary pixel clock and the pixel clock obtained by adjusting the first pixel clock for the j-1th time as a second pixel clock difference; when the second pixel clock difference is less than or equal to the adjustment pixel clock and the second pixel clock difference is less than or equal to the single-step maximum adjustment value, adjusting the second pixel clock difference to the first pixel clock; when the second pixel clock difference is greater than the adjustment pixel clock and the adjustment pixel clock is less than or equal to the single-step maximum adjustment value, adjusting the adjustment pixel clock to the first pixel clock; when the second pixel clock difference is greater than the single-step maximum adjustment value and the adjustment pixel clock is greater than or equal to the single-step maximum adjustment value, adjusting the first pixel clock to the single-step maximum adjustment value.

[0012] In an exemplary embodiment, determining a maximum adjustment range value and a single-step maximum adjustment value supported by a pixel clock of a receiving end includes: reading state information of a clock phase-locked loop of the receiving end, gradually adjusting the pixel clock of the receiving end according to a single-step minimum adjustment value, when adjusting the pixel clock of the receiving end for the Sth time, the state information changes to an unlocked state, and determining the pixel clock of the receiving end obtained by the S-1th adjustment as the maximum adjustment range value supported by the pixel clock of the receiving end, wherein S is an integer greater than 1; within the maximum adjustment range supported by the pixel clock of the receiving end, gradually increasing the single-step adjustment value of the receiving end from the single-step minimum adjustment value, when increasing the single-step adjustment value for the Wth time, the state information changes to an unlocked state, and determining the single-step adjustment value obtained by the W-1th increase as the single-step maximum adjustment value supported by the pixel clock of the receiving end, wherein W is an integer greater than 1.

[0013] According to another embodiment of the present invention, there is provided a device for adjusting a pixel clock, comprising: an acquisition module for acquiring a first pixel clock, wherein the first pixel clock is a clock obtained by compensating a theoretical pixel clock of a transmitting end by a relative deviation between a crystal oscillator of the transmitting end and a crystal oscillator of a synchronization device; a determination module for determining a maximum adjustment range value and a single-step maximum adjustment value supported by the pixel clock of a receiving end; and an adjustment module for continuously outputting N signals according to a preset period, and when the actual time of the i-th signal output meets a preset condition, adjusting the first pixel clock for the jth time according to the maximum adjustment range value and the single-step maximum adjustment value, wherein N is an integer greater than 1, and i and j are integers greater than or equal to 1 and less than or equal to N.

[0014] According to yet another embodiment of the present invention, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, wherein the computer program implements the steps of any of the above methods when executed by a processor.

[0015] According to yet another embodiment of the present invention, there is provided an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0016] According to yet another embodiment of the present invention, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the steps of any of the above methods are implemented.

[0017] According to yet another embodiment of the present invention, a computer program product is provided, comprising computer instructions, wherein when the computer instructions are executed by a processor, the steps of any of the above methods are implemented.

[0018] Through the present invention, the theoretical pixel clock of the transmitting end is compensated by the relative deviation between the crystal oscillator of the transmitting end and the crystal oscillator of the synchronization device to obtain the first pixel clock; the transmitting end continuously outputs N signals according to the preset period, and when the actual time of the outputted i-th signal meets the preset conditions, the first pixel clock is adjusted according to the maximum adjustment range value and the single-step maximum adjustment value of the receiving end. Since the maximum adjustment range value and the single-step maximum adjustment value of the receiving end are considered when adjusting the pixel clock of the transmitting end, the clock phase-locked loop of the receiving end can be prevented from losing lock, thereby generating problems such as no picture, black screen or flickering screen, and the effect of synchronous display of distributed devices can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of a scenario of a distributed device according to an embodiment of the present invention;

[0020] Figure 2 is a hardware structure block diagram of a mobile terminal of a method for adjusting pixel clock according to an embodiment of the present invention;

[0021] Figure 3 is a flow chart of a method for adjusting a pixel clock according to an embodiment of the present invention;

[0022] Figure 4 is a schematic diagram of calculating the relative deviation between the crystal oscillator of the transmitting end and the crystal oscillator of the synchronization device according to an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of a process according to an embodiment of the present invention. Figure 1 ;

[0024] Figure 6 This is a schematic diagram of a process according to an embodiment of the present invention. Figure 2 ;

[0025] Figure 7 is a schematic diagram of a physical connection method according to an embodiment of the present invention;

[0026] Figure 8 This is a schematic diagram of a process according to an embodiment of the present invention. Figure 3 ;

[0027] Fig. 9 is a structural block diagram of a device for adjusting a pixel clock according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with the embodiments.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0030] The following is an explanation of the abbreviations involved in this application:

[0031] High-Definition Multimedia Interface: High-Definition Multimedia Interface, referred to as HDMI.

[0032] VYSNC signal (Vertical Synchronization) refers to a synchronization signal between display devices (such as monitors) and graphics cards. Its function is to control the refresh rate of the monitor to keep in sync with the frame rate output by the graphics card, avoid screen tearing and improve the stability of the displayed image. Normally, the VSYNC signal will lock the refresh rate of the monitor to a value equal to the frame rate output by the graphics card, thereby ensuring the smoothness and consistency of the image.

[0033] TMDS (Transition Minimized Differential Signaling): minimizes the transmission of differential signals.

[0034] The purpose is to solve the problem that the transmitter adjusts the pixel clock in a too large range or a too large single adjustment value, causing the receiver to lose clock lock and no picture display. This application is applicable to distributed device scenarios such as Figure 1 .

[0035] The method embodiments provided in the embodiments of the present application can be Figure 1The sending end shown is executed, and the sending end can be a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, Figure 2 FIG. 1 is a hardware structure block diagram of a mobile terminal of a method for adjusting pixel clock according to an embodiment of the present invention. Figure 2 As shown, the mobile terminal may include one or more ( Figure 2 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the mobile terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 2 The structure shown is only for illustration and does not limit the structure of the mobile terminal. Figure 2 More or fewer components as shown, or with Figure 2 Different configurations are shown.

[0036] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for adjusting the pixel clock in the embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the mobile terminal via a network. Examples of the above network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0037] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0038] In this embodiment, a method for adjusting pixel clock running on the above mobile terminal is provided. Figure 3 is a flow chart of a method for adjusting a pixel clock according to an embodiment of the present invention. Figure 3As shown, the process includes the following steps:

[0039] Step S202, obtaining a first pixel clock, wherein the first pixel clock is a clock obtained by compensating a theoretical pixel clock of the transmitting end through a relative deviation between a crystal oscillator of the transmitting end and a crystal oscillator of a synchronization device;

[0040] The transmitting end may be an HDMI transmitting end;

[0041] Specifically, the relative deviation between the crystal oscillator of the transmitting end and the crystal oscillator of the synchronization device can be calculated as follows: Figure 4 The steps shown include:

[0042] Step S1, obtain the current system time of the sender (also called the output node) (System time is world time, which is only related to the crystal oscillator of the synchronization device and has nothing to do with the crystal oscillator of the sending end) and monotonic time (The monotonic time is only related to the crystal oscillator of the transmitter itself);

[0043] Step S2, the output node enables a high-precision timer and sets the timer to 10 seconds;

[0044] Step S3: After the timer expires, obtain the current system time of the sender and monotonic time ;

[0045] Step S4, calculating the relative deviation between the crystal oscillator of the synchronization device and the crystal oscillator of the transmitting end by the following formula:

[0046]

[0047] The theoretical pixel clock in the above embodiment can be obtained by the following formula:

[0048]

[0049] in, is the total number of pixels in the horizontal direction of the image output by the sender. is the total number of pixels in the vertical direction of the image output by the sender. It is the frame rate of the image output by the sender.

[0050] As an optional implementation, when the theoretical pixel clock is less than a preset threshold (which can be set according to actual conditions, such as 340 MHZ), the calculation formula of the compensated actual pixel clock (first pixel clock) is as follows:

[0051]

[0052] When the theoretical pixel clock is greater than or equal to the preset threshold, the calculation formula of the actual pixel clock after compensation (the first pixel clock) is as follows:

[0053]

[0054] Through the above embodiments, the first pixel clock of the transmitting end after clock compensation can be obtained.

[0055] Step S204, determining the maximum adjustment range value and the single-step maximum adjustment value supported by the pixel clock of the receiving end;

[0056] The above-mentioned receiving end may be an HDMI receiving end.

[0057] Optionally, the maximum adjustment range and single-step maximum adjustment value supported by the pixel clock of the receiving end may be determined in the following manner:

[0058] Reading the state information of the clock phase-locked loop of the receiving end, gradually adjusting the pixel clock of the receiving end according to the single-step minimum adjustment value, when the pixel clock of the receiving end is adjusted for the Sth time, the state information changes to an unlocked state, and determining the pixel clock of the receiving end obtained by the S-1th adjustment as the maximum adjustment range value supported by the pixel clock of the receiving end, wherein S is an integer greater than 1;

[0059] Within the maximum adjustment range supported by the pixel clock of the receiving end, the single-step adjustment value of the receiving end is gradually increased from the single-step minimum adjustment value. When the single-step adjustment value is increased for the Wth time, the status information changes to an unlocked state, and the single-step adjustment value obtained by the W-1th increase is determined as the single-step maximum adjustment value supported by the pixel clock of the receiving end, where W is an integer greater than 1.

[0060] Specifically, the transmitting end can configure the receiving end clock phase-locked loop lock flag register;

[0061] The transmitter detects whether the hot plug detection pin (Hot Plug Detection, referred to as HPD) is pulled high. If HPD is pulled high, it means that a receiver is plugged in; otherwise, it means that no receiver is plugged in, and the HPD pin is re-checked every 100ms;

[0062] The transmitter reads the extended display identification data HDMI EDID information of the receiver, and determines whether the receiver supports the state and control data channel function through the SCDC_Present (SCDC: State and Control Data Channel) flag in the HDMI EDID information. SCDC_Present is a flag indicating whether the receiver supports the state and control data channel function. 1b: indicates that the receiver supports the state and control data channel function, 0b: indicates that the receiver does not support the state and control data channel function.

[0063] If the value of the SCDC_Present flag is 1b, it means that the receiving end supports the status and control data channel function, and the sending end can obtain the receiving end lock status information through the clock phase-locked loop unlock status register on the SCDC path. If the SCDC_Present flag is 0b, it means that the receiving end does not support the status and control channel function, so the sending end cannot obtain the clock phase-locked loop unlock status information through the register. If the receiving end does not support the clock phase-locked loop unlock detection, the sending end configures the default experience value as the pixel clock maximum range adjustment value and the single-step maximum adjustment value.

[0064] Adjust the pixel clock in a fixed direction (upward or downward) according to the single-step minimum value until the unlocked state value of the clock phase-locked loop of the receiving end is read as 1, determine the maximum adjustment range of the pixel clock of the receiving end, and set the unlocked state value of the clock phase-locked loop of the HDMI receiving end to 0;

[0065] Within the maximum adjustment range of the pixel clock at the receiving end, the single adjustment step is continuously increased until the unlocked state value of the clock phase-locked loop at the sending end is read as 1, the single maximum adjustment value of the pixel clock at the sending end is determined, and the unlocked state value of the clock phase-locked loop at the HDMI receiving end is reset to 0.

[0066] Step S206, when N signals are continuously output according to a preset period and the actual time of the outputted i-th signal satisfies a preset condition, the first pixel clock is adjusted for the jth time according to the maximum adjustment range value and the single-step maximum adjustment value, wherein N is an integer greater than 1, and i and j are integers greater than or equal to 1 and less than or equal to N.

[0067] The above-mentioned preset conditions include: the difference between the theoretical time and the actual time of the i-th signal is greater than or equal to a preset clock threshold, and the preset clock threshold can be set according to actual conditions, for example, 3 seconds, 5 seconds, 10 seconds, etc.

[0068] Specifically, Figure 5 As shown, the following steps are included:

[0069] Obtain the theoretical time and actual time of the ith signal; determine the difference between the theoretical time and the actual time as a first time difference; when the first time difference is greater than or equal to a preset clock threshold, adjust the compensated pixel clock according to the maximum adjustment range value and the single-step maximum adjustment value.

[0070] Specifically, assuming that the system time point All distributed transmitters output HDMI signals uniformly, that is, The transmitter starts to output the VSYNC signal at the starting time (i.e., the reference time). The above-mentioned ith signal is the ith VSYNC signal output by the transmitter. Then the theoretical time of the ith signal output by the transmitter is:

[0071]

[0072] in, is the theoretical time of the ith signal, is the frame rate of the sender;

[0073] The first time difference is:

[0074]

[0075] in, is the actual time (system time) of the ith signal.

[0076] As an optional implementation, the above-mentioned adjusting the compensated pixel clock according to the maximum adjustment range value and the single-step maximum adjustment value includes:

[0077] Get the period length of the preset period; where the period length is .

[0078] Determining to adjust the pixel clock according to the cycle duration, the first time difference, and the first pixel clock includes:

[0079] The above adjusted pixel clock is obtained by the following formula:

[0080]

[0081] in, is the above-mentioned first pixel clock.

[0082] Obtaining a target pixel clock according to the adjusted pixel clock and a pixel clock obtained by performing a j-1th adjustment on the first pixel clock, comprising:

[0083] The target pixel clock is obtained by the following formula:

[0084]

[0085] In the above formula is the target pixel clock, is the pixel clock obtained by the previous adjustment (the pixel clock obtained by the j-1th adjustment).

[0086] According to the relationship between the adjustment pixel clock and the single-step maximum adjustment value, and the relationship between the target pixel clock and the maximum adjustment range value, the first pixel clock is adjusted, including:

[0087] Determining a difference between the target pixel clock and the first pixel clock as a first pixel clock difference includes:

[0088] The first pixel clock difference is obtained by the following formula:

[0089]

[0090] The first pixel clock is adjusted according to the following conditions:

[0091]

[0092] in, is the maximum adjustment range value.

[0093]

[0094] in, is the maximum single-step adjustment value.

[0095] When the first pixel clock difference is less than or equal to the maximum adjustment range value, the first pixel clock is adjusted according to the relationship between the adjusted pixel clock and the single-step maximum adjustment value.

[0096] When the first pixel clock difference is less than or equal to the maximum adjustment range value, and the adjusted pixel clock is greater than the single-step maximum adjustment value, adjusting the first pixel clock by the single-step maximum adjustment value;

[0097] When the first pixel clock difference is less than or equal to the maximum adjustment range value, and the adjusted pixel clock is less than or equal to the single-step maximum adjustment value, the adjusted pixel clock is adjusted for the first pixel clock.

[0098] As an optional implementation, when the first pixel clock difference is greater than the maximum adjustment range value, the sum of the maximum adjustment range value and the first pixel clock difference is determined as the boundary pixel clock; the difference between the boundary pixel clock and the pixel clock obtained by adjusting the first pixel clock for the j-1th time is determined as the second pixel clock difference; when the second pixel clock difference is less than or equal to the adjustment pixel clock, and the second pixel clock difference is less than or equal to the single-step maximum adjustment value, the first pixel clock is adjusted to the second pixel clock difference; when the second pixel clock difference is greater than the adjustment pixel clock, and the adjustment pixel clock is less than or equal to the single-step maximum adjustment value, the first pixel clock is adjusted to the adjustment pixel clock; when the second pixel clock difference is greater than the single-step maximum adjustment value, and the adjustment pixel clock is greater than or equal to the single-step maximum adjustment value, the first pixel clock is adjusted to the single-step maximum adjustment value.

[0099] Optionally, the executor of the above steps may be a background processor, or other devices with similar processing capabilities, or a machine that integrates at least an image acquisition device and a data processing device, wherein the image acquisition device may include a graphics acquisition module such as a camera, and the data processing device may include a computer, a mobile phone or other terminal, but is not limited thereto.

[0100] As an optional implementation, the entire system in the present application has an approximate and unified system time, that is, there is a high-precision time synchronization system, such as PTP (IEEE1588) service, and the device nodes perform time synchronization operations every second; the hardware of the sending end supports HDMI pixel clock adjustment; the sending end system supports high-precision timers; and the receiving end supports pixel clock phase-locked loop unlock status feedback.

[0101] like Figure 6 The figure shows a schematic diagram of the overall scheme, which includes the following operation procedures:

[0102] Measure the maximum adjustment range and single-step maximum adjustment value of the pixel clock supported by the clock phase-locked loop of the receiving end after locking the clock; measure the relative deviation between the crystal oscillator of the sending end and the crystal oscillator of the system time synchronization device as the compensation value of the pixel clock; calculate the pixel clock after the output resolution is compensated; based on the maximum pixel clock adjustment range of the receiving end, the maximum single-step adjustment value, the system time and the vsync output reference time, periodically adjust the pixel clock of the output node HDMI.

[0103] like Figure 7The figure shows the method for measuring the maximum adjustment range and the maximum single-step adjustment value supported by the clock phase-locked loop of the receiving end after locking. The physical connection mode, the HDMI receiving end supports the SCDC (State and Control Data Channel: state and control data channel function). It is necessary to select a field in the reserved field of SCDC as a flag bit to indicate whether the clock phase-locked loop has ever lost lock. The HDMI transmitting end can know whether the clock phase-locked loop of the HDMI receiving end has ever lost lock through the lock status flag bit of SCDC. Once the clock phase-locked loop loses lock, the HDMI receiving end will set the flag bit to 1. The HDMI transmitting end is responsible for setting the flag bit to 0.

[0104] like Figure 8 The following is a schematic diagram of the specific process, which includes the following contents:

[0105] The transmitter configures the receiver clock phase-locked loop unlock flag register; the transmitter detects whether the HPD (HotPlug Detection) pin is pulled high. If the HPD is pulled high, it means that there is an HDMI receiver plugged in; otherwise, it means that there is no HDMI receiver plugged in, and the HPD pin is re-detected every 100ms; the HDMI transmitter reads the HDMI EDID information of the HDMI receiver, and the HDMI transmitter determines whether the HDMI receiver supports the state and control data channel function through the SCDC_Present (SCDC: Stateand Control DataChannel) flag in the EDID information. If the value of the SCDC_Present flag is 1b, it indicates that the HDMI receiver supports the state and control data channel function, and the HDMI transmitter can obtain the HDMI receiver lock status information through the clock phase-locked loop unlock status register on the SCDC path. If the SCDC_Present flag is 0b, it means that the HDMI receiver does not support the state and control channel function, so the HDMI transmitter cannot obtain the clock phase-locked loop unlock status information through the register.

[0106] If the HDMI receiving end does not support the clock phase-locked loop unlock detection, the HDMI sending end configures the default empirical value as the maximum range adjustment value and the single-step maximum adjustment value of the pixel clock; the pixel clock is adjusted in a fixed direction (upward or downward) until the unlocked state value of the clock phase-locked loop of the HDMI receiving end is read as 1, the maximum adjustment range value of the pixel clock of the receiving end is determined, and the unlocked state value of the clock phase-locked loop of the HDMI receiving end is set to 0; within the maximum adjustment range of the pixel clock, the single adjustment step is continuously increased until the unlocked state value of the clock phase-locked loop of the sending end is read as 1, the single maximum adjustment value of the pixel clock of the sending end is determined, and the unlocked state value of the clock phase-locked loop of the HDMI receiving end is reset to 0.

[0107] This application clarifies the maximum allowable adjustment value and the single maximum adjustment value after the clock of the receiving end is locked. These values ​​serve as the boundary conditions for the pixel clock adjustment of the sending end. Based on the boundary conditions and the difference between the actual and theoretical vsync, the sending end can not only effectively avoid the problem of black screen or no picture after the receiving end clock loses lock during the pixel clock adjustment process, but also quickly achieve the effect of synchronous display of distributed devices.

[0108] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0109] In this embodiment, a device for adjusting the pixel clock is also provided, which is used to implement the above embodiments and preferred implementation modes, and will not be repeated here. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0110] Fig. 9 is a structural block diagram of a device for adjusting a pixel clock according to an embodiment of the present invention. Fig. 9 As shown, the device includes: an acquisition module 92, used to acquire a first pixel clock, wherein the first pixel clock is a clock obtained by compensating the theoretical pixel clock of the transmitting end by the relative deviation between the crystal oscillator of the transmitting end and the crystal oscillator of the synchronization device; a determination module 94, used to determine the maximum adjustment range value and the single-step maximum adjustment value supported by the pixel clock of the receiving end; an adjustment module 96, used to continuously output N signals according to a preset period, and when the actual time of the i-th signal output meets the preset conditions, adjust the first pixel clock for the jth time according to the maximum adjustment range value and the single-step maximum adjustment value, wherein N is an integer greater than 1, and i and j are integers greater than or equal to 1 and less than or equal to N.

[0111] As an optional embodiment, the above-mentioned device is also used to obtain the theoretical time and actual time of the i-th signal; determine the difference between the theoretical time and the actual time as a first time difference; when the first time difference is greater than or equal to a preset clock threshold, adjust the compensated pixel clock according to the maximum adjustment range value and the single-step maximum adjustment value.

[0112] As an optional embodiment, the above-mentioned device is also used to obtain the cycle length of the preset cycle; determine the adjusted pixel clock based on the cycle length and the first time difference, and the first pixel clock; obtain the target pixel clock based on the adjusted pixel clock and the pixel clock obtained by adjusting the first pixel clock for the j-1th time; adjust the first pixel clock based on the relationship between the adjusted pixel clock and the single-step maximum adjustment value, and the relationship between the target pixel clock and the maximum adjustment range value.

[0113] As an optional embodiment, the above-mentioned device is also used to determine the difference between the target pixel clock and the first pixel clock as a first pixel clock difference; when the first pixel clock difference is less than or equal to the maximum adjustment range value, the first pixel clock is adjusted according to the relationship between the adjusted pixel clock and the single-step maximum adjustment value.

[0114] As an optional embodiment, the above-mentioned device is also used to adjust the single-step maximum adjustment value of the first pixel clock when the first pixel clock difference is less than or equal to the maximum adjustment range value and the adjusted pixel clock is greater than the single-step maximum adjustment value; and adjust the adjusted pixel clock of the first pixel clock when the first pixel clock difference is less than or equal to the maximum adjustment range value and the adjusted pixel clock is less than or equal to the single-step maximum adjustment value.

[0115] As an optional implementation, the above-mentioned device is also used to, when the first pixel clock difference is greater than the maximum adjustment range value, determine the sum of the maximum adjustment range value and the first pixel clock difference as the boundary pixel clock; determine the difference between the boundary pixel clock and the pixel clock obtained by adjusting the first pixel clock for the j-1th time as the second pixel clock difference; when the second pixel clock difference is less than or equal to the adjustment pixel clock, and the second pixel clock difference is less than or equal to the single-step maximum adjustment value, adjust the second pixel clock difference to the first pixel clock; when the second pixel clock difference is greater than the adjustment pixel clock, and the adjustment pixel clock is less than or equal to the single-step maximum adjustment value, adjust the adjustment pixel clock to the first pixel clock; when the second pixel clock difference is greater than the single-step maximum adjustment value, and the adjustment pixel clock is greater than or equal to the single-step maximum adjustment value, adjust the first pixel clock to the single-step maximum adjustment value.

[0116] As an optional implementation, the above-mentioned device is also used to read the status information of the clock phase-locked loop of the receiving end, and gradually adjust the pixel clock of the receiving end according to the single-step minimum adjustment value. When the pixel clock of the receiving end is adjusted for the Sth time, the status information changes to an unlocked state, and the pixel clock of the receiving end obtained by the S-1th adjustment is determined as the maximum adjustment range value supported by the pixel clock of the receiving end, wherein S is an integer greater than 1; within the maximum adjustment range supported by the pixel clock of the receiving end, the single-step adjustment value of the receiving end is gradually increased from the single-step minimum adjustment value. When the single-step adjustment value is increased for the Wth time, the status information changes to an unlocked state, and the single-step adjustment value obtained by the W-1th increase is determined as the single-step maximum adjustment value supported by the pixel clock of the receiving end, wherein W is an integer greater than 1.

[0117] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0118] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above methods are implemented.

[0119] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0120] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0121] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0122] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0123] An embodiment of the present invention further provides a computer program product, including a computer program, which implements the steps of the method described in each embodiment of the present application when executed by a processor.

[0124] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0125] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for adjusting a pixel clock, characterized in that: include: Acquire a first pixel clock, wherein the first pixel clock is a clock obtained by compensating a theoretical pixel clock of the transmitting end through a relative deviation between a crystal oscillator of the transmitting end and a crystal oscillator of a synchronization device; Determine the maximum adjustment range and single-step maximum adjustment value supported by the pixel clock of the receiving end; When N signals are continuously output according to a preset period and the actual time of the i-th signal output meets a preset condition, the first pixel clock is adjusted for the jth time according to the maximum adjustment range value and the single-step maximum adjustment value, wherein N is an integer greater than 1, and i and j are integers greater than or equal to 1 and less than or equal to N.

2. The method according to claim 1, characterized in that When N signals are continuously output according to a preset period and the actual time of the outputted i-th signal satisfies a preset condition, the first pixel clock is adjusted for the jth time according to the maximum adjustment range value and the single-step maximum adjustment value, comprising: Obtaining the theoretical time and actual time of the ith signal; Determine the difference between the theoretical time and the actual time as a first time difference; When the first time difference is greater than or equal to a preset clock threshold, the compensated pixel clock is adjusted according to the maximum adjustment range value and the single-step maximum adjustment value.

3. The method according to claim 2, characterized in that The compensated pixel clock is adjusted according to the maximum adjustment range value and the single-step maximum adjustment value, including: Obtaining the period length of the preset period; Determine to adjust the pixel clock according to the cycle duration, the first time difference, and the first pixel clock; Obtaining a target pixel clock according to the adjusted pixel clock and a pixel clock obtained by performing a j-1th adjustment on the first pixel clock; The first pixel clock is adjusted according to the relationship between the adjustment pixel clock and the single-step maximum adjustment value, and the relationship between the target pixel clock and the maximum adjustment range value.

4. The method according to claim 3, characterized in that According to the relationship between the adjustment pixel clock and the single-step maximum adjustment value, and the relationship between the target pixel clock and the maximum adjustment range value, the first pixel clock is adjusted, including: determining a difference between the target pixel clock and the first pixel clock as a first pixel clock difference; When the first pixel clock difference is less than or equal to the maximum adjustment range value, the first pixel clock is adjusted according to the relationship between the adjusted pixel clock and the single-step maximum adjustment value.

5. The method according to claim 4, characterized in that When the first pixel clock difference is less than or equal to the maximum adjustment range value, adjusting the first pixel clock according to the relationship between the adjusted pixel clock and the single-step maximum adjustment value includes: When the first pixel clock difference is less than or equal to the maximum adjustment range value, and the adjusted pixel clock is greater than the single-step maximum adjustment value, adjusting the first pixel clock by the single-step maximum adjustment value; When the first pixel clock difference is less than or equal to the maximum adjustment range value, and the adjusted pixel clock is less than or equal to the single-step maximum adjustment value, the adjusted pixel clock is adjusted for the first pixel clock.

6. The method according to claim 4, characterized in that The method further comprises: In a case where the first pixel clock difference is greater than the maximum adjustment range value, determining a sum of the maximum adjustment range value and the first pixel clock as a boundary pixel clock; determining a difference between the boundary pixel clock and a pixel clock obtained by performing a j-1th adjustment on the first pixel clock as a second pixel clock difference; When the second pixel clock difference is less than or equal to the adjusted pixel clock, and the second pixel clock difference is less than or equal to the single-step maximum adjustment value, adjusting the second pixel clock difference to the first pixel clock; When the second pixel clock difference is greater than the adjusted pixel clock, and the adjusted pixel clock is less than or equal to the single-step maximum adjustment value, adjusting the adjusted pixel clock to the first pixel clock; When the second pixel clock difference is greater than the single-step maximum adjustment value and the adjusted pixel clock is greater than or equal to the single-step maximum adjustment value, the first pixel clock is adjusted to the single-step maximum adjustment value.

7. The method according to claim 1, characterized in that Determine the maximum adjustment range and single-step maximum adjustment value supported by the pixel clock of the receiving end, including: Reading state information of the clock phase-locked loop of the receiving end, gradually adjusting the pixel clock of the receiving end according to the single-step minimum adjustment value, when the pixel clock of the receiving end is adjusted for the Sth time, the state information changes to an unlocked state, and determining the pixel clock of the receiving end obtained by the S-1th adjustment as the maximum adjustment range value supported by the pixel clock of the receiving end, wherein S is an integer greater than 1; Within the maximum adjustment range supported by the pixel clock of the receiving end, the single-step adjustment value of the receiving end is gradually increased from the single-step minimum adjustment value. When the single-step adjustment value is increased for the Wth time, the state information changes to an unlocked state, and the single-step adjustment value obtained by the W-1th increase is determined as the single-step maximum adjustment value supported by the pixel clock of the receiving end, where W is an integer greater than 1.

8. A device for adjusting a pixel clock, characterized in that: include: An acquisition module, used for acquiring a first pixel clock, wherein the first pixel clock is a clock obtained by compensating a theoretical pixel clock of the transmitting end by a relative deviation between a crystal oscillator of the transmitting end and a crystal oscillator of a synchronization device; A determination module, used to determine a maximum adjustment range value and a single-step maximum adjustment value supported by a pixel clock of a receiving end; An adjustment module is used to continuously output N signals according to a preset period, and when the actual time of the i-th signal output meets a preset condition, adjust the first pixel clock for the jth time according to the maximum adjustment range value and the single-step maximum adjustment value, wherein N is an integer greater than 1, and i and j are integers greater than or equal to 1 and less than or equal to N.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 7 when executed by a processor.

10. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 7.

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