A SAR ADC front-end circuit and synchronous sampling multiplexing analog-to-digital converter

Abstract

The present invention discloses a SAR ADC front-end circuit and a synchronous sampling multiplexed analog-to-digital converter, wherein the SAR ADC front-end circuit includes a programmable gain amplifier, an anti-aliasing filter and a driving circuit, wherein the driving circuit includes a first switch, a resistor, a filter capacitor, a buffer amplifier and a second switch; the overall input end after the first switch and the resistor are connected in series is connected to the anti-aliasing filter, the overall output end is respectively connected to one end of the filter capacitor and the input end of the capacitor array, and the other end of the filter capacitor is grounded; the buffer amplifier and the second switch are connected in series to the output end of the anti-aliasing filter, and the buffer amplifier and the second switch are connected in series to the first switch and the resistor as a whole. The present invention enhances the signal driving capability of the SAR ADC, fully attenuates the impact of the switch capacitor kickback at the ADC input end, and eliminates the impact of the noise of the buffer amplifier on the ADC, thereby solving the problems existing in the off-chip drive circuit and the on-chip drive circuit in the prior art.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a SAR ADC front-end circuit and a synchronous sampling multiplexed analog-to-digital converter. Background Art

[0002] High-precision SAR analog-to-digital converters have the characteristics of high precision and low power consumption, and have broad application scenarios in sensor monitoring, test instruments, medical electronics, biological front-ends, etc. The capacitor array is one of the core modules of the high-precision SAR analog-to-digital converter. In order to meet the capacitor matching and sampling noise required for high-precision SAR, the capacitor array is usually large, and there will be a large voltage step when the capacitor array switches from the conversion stage to the acquisition stage. Therefore, driving the capacitor array becomes a technical difficulty in the design.

[0003] In the prior art, a drive circuit is usually specially designed for a capacitor array, and the existing drive circuit includes an off-chip drive circuit and an on-chip drive circuit. The off-chip drive circuit generally uses a buffer amplifier and an RC circuit in series. Although this drive can solve the drive problem, it has many disadvantages. For example, the capacitance value in the RC circuit is large and it is only suitable for off-chip drive. The on-chip drive circuit generally directly connects the buffer amplifier to the capacitor array. Although this reduces the kickback voltage and enhances the driving ability, the introduction of the buffer amplifier will also cause large noise, and most of them require preprocessing of the signal, which increases the hardware overhead and circuit complexity of the system, and is not suitable for the structure of synchronous sampling multiplexing.

[0004] Currently, no effective solution has been proposed for the deficiencies of off-chip driving circuits and on-chip driving circuits in the prior art. Summary of the invention

[0005] In view of this, the embodiments of the present invention provide a SAR ADC front-end circuit and a synchronous sampling multiplexing analog-to-digital converter to at least solve the problems existing in the off-chip driving circuit and the on-chip driving circuit in the prior art.

[0006] The embodiment of the present invention provides the following technical solutions:

[0007] A SAR ADC front-end circuit structure provided by an embodiment of the present invention includes a programmable gain amplifier, an anti-aliasing filter and a driving circuit, wherein the programmable gain amplifier, the anti-aliasing filter and the driving circuit are sequentially connected in series, and the driving circuit includes a first switch, a resistor, a filter capacitor, a buffer amplifier and a second switch;

[0008] The first switch and the resistor are connected in series, and the overall input end of the first switch and the resistor connected in series is connected to the anti-aliasing filter, and the overall output end is respectively connected to one end of the filter capacitor and the input end of the capacitor array, and the resistor and the filter capacitor together form an RC filter;

[0009] The buffer amplifier and the second switch are connected in series and connected to the output end of the anti-aliasing filter, and the buffer amplifier and the second switch are connected in series and connected in parallel with the first switch and the resistor as a whole.

[0010] Furthermore, when the SAR ADC front-end circuit structure is in the beginning part of sampling and tracking the input signal, the first switch is opened, the second switch is closed, and the buffer amplifier is used to stabilize the input signal; when the SAR ADC front-end circuit structure is in the second half of sampling and tracking the input signal, the first switch is closed, the second switch is opened, and the input signal is filtered using the RC filter.

[0011] Furthermore, the driving circuit is an on-chip driving circuit integrated into the SAR ADC front-end circuit structure.

[0012] Furthermore, the opening and closing time of the second switch is determined at least by system accuracy and the bandwidth of the buffer amplifier.

[0013] Furthermore, the input end of the programmable gain amplifier is used to obtain an input signal.

[0014] The embodiment of the present invention further provides a synchronous sampling multiplexing analog-to-digital converter, comprising:

[0015] A SAR ADC front-end circuit structure as described above;

[0016] a third switch, wherein an input end of the third switch is connected to an output end of the SAR ADC front-end circuit structure;

[0017] A sampling capacitor, wherein the sampling capacitor is connected in series with the third switch;

[0018] a fourth switch, one end of the fourth switch being connected to the input end of the sampling capacitor, and the other end of the fourth switch being grounded;

[0019] A fifth switch, one end of the fifth switch is connected to the output end of the sampling capacitor, and the other end of the fifth switch is grounded.

[0020] Further, after the synchronous sampling multiplexing analog-to-digital converter performs analog-to-digital conversion, the upper plate of the sampling capacitor follows the input signal from the common mode level.

[0021] Furthermore, before the synchronous sampling multiplexed analog-to-digital converter enters the signal acquisition stage, the first switch of the SARADC front-end circuit structure is opened and the second switch is closed, so that the buffer amplifier of the SAR ADC front-end circuit structure is connected to the signal path, and the filter capacitor of the SAR ADC front-end circuit structure is precharged to the input signal to buffer the voltage kickback caused by the sampling capacitor.

[0022] Furthermore, the buffer amplifier is a high bandwidth buffer amplifier to track the upper plate of the sampling capacitor to the input level.

[0023] Furthermore, before the sampling point of the synchronous sampling multiplexed analog-to-digital converter arrives, the first switch is closed and the second switch is turned on to disconnect the buffer amplifier so that the RC buffer of the SAR ADC front-end circuit structure is connected to the signal path.

[0024] Compared with the prior art, the at least one technical solution adopted in the embodiment of the present invention can achieve the following beneficial effects:

[0025] A SAR ADC front-end circuit of the present invention connects a buffer amplifier and an RC filter in parallel, uses a first switch to control whether the RC filter is connected to the front-end circuit, and uses a second switch to control whether the buffer amplifier is connected to the front-end circuit, so that when sampling and tracking the input signal starts, the buffer amplifier is used to amplify the input signal, and the buffer amplifier can be turned off at the sampling time to eliminate the noise brought by the buffer amplifier in the front-end circuit. While enhancing the signal driving capability of the SAR ADC, it can also fully attenuate the kickback effect of the switch capacitor at the ADC input end;

[0026] Furthermore, by building the RC buffer into the SAR ADC, the large capacitance in the traditional external RC filter can also be reduced to facilitate internal integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 It is an existing external drive circuit;

[0029] Figure 2 This is the circuit diagram of the existing built-in driver buffer;

[0030] Figure 3This is the circuit diagram of the existing buffer nested into the SAR loop;

[0031] Figure 4 is a circuit diagram of a SAR ADC front-end circuit according to an embodiment of the present invention;

[0032] Figure 5 It is a structural timing of a SAR ADC front-end circuit according to an embodiment of the present invention;

[0033] Figure 6 is an application circuit diagram of a synchronous sampling multiplexing analog-to-digital converter according to an embodiment of the present invention;

[0034] Figure 7 It is a structural timing of a synchronous sampling multiplexing analog-to-digital converter according to an embodiment of the present invention;

[0035] Figure 8 The present invention is a schematic diagram of a sampling channel of a synchronous sampling multiplexed analog-to-digital converter according to an embodiment of the present invention.

[0036] The accompanying drawings of the present invention are as follows:

[0037] 10. Anti-aliasing filter;

[0038] 20. driving circuit; 21. first switch; 22. resistor; 23. filter capacitor; 24. buffer amplifier; 25. second switch;

[0039] 30. third switch; 40. sampling capacitor; 50. fourth switch; 60. fifth switch; 70. capacitor array. DETAILED DESCRIPTION

[0040] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0041] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0042] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0043] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0044] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0045] High-precision SAR analog-to-digital converters have the characteristics of high precision and low power consumption, and have broad application prospects in the fields of sensor monitoring, test instruments, medical electronics, and biological front-ends. The capacitor array is one of the core modules in the SAR analog-to-digital converter. In order to meet the capacitor matching and sampling noise required for high precision, the capacitor array is usually large, and a large voltage step will occur when the capacitive DAC switches from the conversion stage to the acquisition stage. Therefore, driving the capacitor array becomes one of the technical difficulties in the design.

[0046] Figure 1 The figure shows a classic drive circuit design. This circuit structure solves the drive problem by adding a unity gain amplifier and an RC filter outside the SAR ADC (successive approximation register analog-to-digital converter). Assume that the input signal is:

[0047] V peak sin(2πf in t) (1)

[0048] After the conversion is completed, the capacitor array is charged to the sampling voltage of the previous stage. The maximum voltage step when the capacitor array switches from the conversion mode back to the acquisition mode is:

[0049]

[0050] The role of the unity-gain buffer amplifier is to help attenuate the impact of the kickback through its large bandwidth to ensure the accuracy of the next signal acquisition. The RC filter has two functions. On the one hand, it can reduce the size of the step signal by pre-storing the Vin signal to help the buffer amplifier establish the signal. At the same time, the large RC value also helps to attenuate the noise of the buffer amplifier and prevent it from deteriorating the signal-to-noise ratio of the ADC system.

[0051] However, in order to achieve the above purpose, the value of Cext needs to be large, generally in the order of nF, so it is only suitable for off-chip driving; at the same time, the circuit is more complicated in a multiplexed ADC, because there is no definite relationship between the multiplexed channels, the voltage step is larger, and the worst case is that the signals between the two channels are positive and negative full scale respectively. At this time, the design requirements for the buffer amplifier and RC are higher; furthermore, this structure has a larger kickback when the input is close to the Nyquist frequency (close to full scale), and the buffer amplifier design requirements are higher.

[0052] If the drive circuit is built-in (built-in drive circuit means that the drive function has been designed and integrated into the same chip or module), a common method is to directly connect the buffer amplifier to the capacitor array, such as Figure 2 As shown in the figure, the buffering and filtering of the RC buffer are missing, which places higher requirements on the noise and driving capability of the buffer amplifier. If the requirements on the buffer amplifier need to be reduced, additional measures are needed to reduce the kickback voltage.

[0053] A common approach is to pre-judge the size of the input signal and pre-charge the capacitor array to a value close to the signal, thereby reducing the kickback voltage and enhancing the driving capability. The limitation of this method is that the signal needs to be pre-processed, which increases the hardware overhead and complexity of the system; at the same time, it is not applicable to the structure of synchronous sampling multiplexing.

[0054] Figure 3 The figure shows a system block diagram that enhances the driving capability by changing the SAR ADC structure. This structure has a built-in buffer amplifier, which separates the DAC with a larger capacitance and the sampling capacitor, thereby reducing the driving capability requirements of the buffer amplifier, and only requires a source follower. However, due to the nonlinearity of the buffer amplifier, this structure is difficult to achieve high precision, and it cannot be used in a multiplexed structure.

[0055] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0056] Example 1

[0057] like Figures 4-5The SAR ADC front-end circuit structure provided by the embodiment of the present invention includes a programmable gain amplifier, an anti-aliasing filter 10 and a driving circuit 20, wherein the programmable gain amplifier, the anti-aliasing filter 10 and the driving circuit 20 are connected in series in sequence.

[0058] Further, the driving circuit 20 includes a first switch 21, a resistor 22, a filter capacitor 23, a buffer amplifier 24 and a second switch 25; wherein the first switch 21 and the resistor 22 are connected in series, and the overall input end of the first switch 21 and the resistor 22 connected in series is connected to the anti-aliasing filter 10, and the overall output end is respectively connected to one end of the filter capacitor 23 and the input end of the capacitor array 70, and the resistor 22 and the filter capacitor 23 together constitute an RC filter; the buffer amplifier 24 and the second switch 25 are connected in series and connected to the output end of the anti-aliasing filter 10, and the buffer amplifier 24 and the second switch 25 are connected in series and connected in parallel with the first switch 21 and the resistor 22 as a whole.

[0059] Specifically, the input end of the first switch 21 is connected to the output end of the anti-aliasing filter 10, the output end of the first switch 21 is connected to the input end of the resistor 22, the output end of the resistor 22 is respectively connected to the input end of the capacitor array 70 and one end of the filter capacitor 23, and the other end of the filter capacitor 23 is grounded; the overall input end of the circuit structure formed by the buffer amplifier 24 and the second switch 25 being connected in series is connected to the output end of the anti-aliasing filter 10, and the overall output end of the circuit structure formed by the buffer amplifier 24 and the second switch 25 being connected in series is connected to the output end of the resistor 22, that is, the circuit structure formed by the buffer amplifier 24 and the second switch 25 being connected in series is arranged in parallel with the circuit structure formed by the first switch 21 and the resistor 22 being connected in series.

[0060] The other end of the filter capacitor 23 may be grounded.

[0061] In some of the embodiments, when the SAR ADC front-end circuit structure is applied to a differential circuit, the other end of the filter capacitor 23 can be connected across two ends of the differential path.

[0062] Furthermore, when the SAR ADC front-end circuit structure is in the beginning part of sampling and tracking the input signal, the first switch 21 is opened, the second switch 25 is closed, and the buffer amplifier 24 is used to stabilize the input signal; when the SAR ADC front-end circuit structure is in the second half of sampling and tracking the input signal, the first switch 21 is closed, the second switch 25 is opened, and the input signal is filtered using an RC filter.

[0063] Specifically, in the stage of sampling and tracking the input signal, the first half (the beginning part of the sampling and tracking input signal) is established by the buffer amplifier 24, and the second half (the second half of the sampling and tracking input signal) is switched back to the RC filter by adjusting the opening and closing of the first switch 21 and the second switch 25, thereby achieving the establishment accuracy of the first half and the filtering effect of the second half, while achieving a certain establishment accuracy and ensuring that the noise of the front-end circuit structure is within a controllable range.

[0064] The switching between the buffer amplifier 24 and the RC filter is performed through the first switch 21 and the second switch 25. The first switch 21 is closed when the buffer amplifier 24 is turned on, which can prevent the output resistance of the front-end circuit structure and the resistor 22 from constituting a loading effect and affecting the normal operation of the buffer amplifier 24.

[0065] Furthermore, the driving circuit 20 is an on-chip driving circuit 20 integrated into the SAR ADC front-end circuit structure, so that the filter capacitor 23 is reduced after the driving circuit 20 is built in, so as to eliminate the impact of the noise of the buffer amplifier 24 on the overall system while ensuring the driving capability.

[0066] Furthermore, the opening and closing time of the second switch 25 is determined at least by the system accuracy and the bandwidth of the buffer amplifier 24 .

[0067] Furthermore, the input terminal of the programmable gain amplifier is used to obtain an input signal.

[0068] The present invention controls the on-off time of the buffer amplifier 24 by using the first switch 21 and the second switch 25 , thereby achieving the driving capability of the driving circuit 20 while controlling the noise.

[0069] A SAR ADC front-end circuit structure of the present invention enhances the signal driving capability of the SAR analog-to-digital converter, fully reduces the kickback effect of the switched capacitor at the input end of the analog-to-digital converter, eliminates the noise caused by the buffer amplifier 24 in the front-end circuit structure, and reduces the large capacitance in the traditional external RC filter to facilitate internal integration.

[0070] A SAR ADC front-end circuit structure of the present invention is applicable to various sampling structures, including a multiplexed analog-to-digital converter structure for synchronous sampling; and the SAR ADC front-end circuit structure of the embodiment of the present invention is simple in structure and easy to implement, and only requires the addition of a control signal and a corresponding switch.

[0071] Example 2

[0072] like Figures 6 to 8As shown, the embodiment of the present invention also provides a bottom plate sampling network, an upper plate sampling network and a synchronous sampling multiplexed analog-to-digital converter as an application scenario of the proposed front-end circuit, including the SAR ADC front-end circuit structure as described in Example 1, a third switch 30, a sampling capacitor 40, a fourth switch 50 and a fifth switch 60. Among them, the input end of the third switch 30 is connected to the output end of the SAR ADC front-end circuit structure; the sampling capacitor 40 is connected in series with the third switch 30; one end of the fourth switch 50 is connected to the input end of the sampling capacitor 40, and the other end is grounded; one end of the fifth switch 60 is connected to the output end of the sampling capacitor 40, and the other end is grounded.

[0073] Further, after the analog-to-digital converter performs the analog-to-digital conversion, the upper plate of the sampling capacitor 40 follows the input signal from the common mode level.

[0074] Furthermore, before the synchronous sampling multiplexed analog-to-digital converter enters the signal acquisition stage, the first switch 21 of the SAR ADC front-end circuit structure is disconnected and the second switch 25 is closed, so that the buffer amplifier 24 of the SAR ADC front-end circuit structure is connected to the signal path, and the filter capacitor 23 of the SAR ADC front-end circuit structure is pre-charged to the input signal to buffer the voltage kickback caused by the sampling capacitor 40.

[0075] Furthermore, the buffer amplifier 24 is a high bandwidth buffer amplifier 24 to track the upper plate of the sampling capacitor 40 to the input level.

[0076] Furthermore, before the sampling point of the synchronous sampling multiplexed analog-to-digital converter arrives, the first switch 21 is closed and the second switch 25 is turned on to disconnect the buffer amplifier 24 so that the RC buffer of the SAR ADC front-end circuit structure is connected to the signal path.

[0077] The specific implementation of the embodiment of the present invention is as follows:

[0078] After the conversion phase (tc) is over, the upper plate of the sampling capacitor 40 will gradually follow the input signal from the common mode level. Before the acquisition phase begins (Φs1 rising edge), the buffer amplifier 24 is connected to the signal path, and the filter capacitor 23 is pre-charged to the input signal, thereby buffering the voltage kickback brought by the sampling capacitor 40, and then the high-bandwidth buffer amplifier 24 tracks the upper plate of the sampling capacitor 40 to the input level. At this stage, the first switch 21 needs to be turned off to prevent the output resistance and resistor 22 of the front-end circuit structure from causing a loading effect on the buffer amplifier 24, affecting its bandwidth and linearity. Before the sampling point (Φs1 falling edge) arrives, the first switch 21 is turned on, the buffer amplifier 24 path is closed, and the RC filter is connected to the signal path. Since the buffer amplifier 24 is not on the signal transmission path at the sampling moment, the noise of the buffer amplifier 24 is eliminated, and the first-order RC also plays a filtering role.

[0079] The present invention can also be used in other sampling circuit structures, such as Figure 4 After the conversion phase is over, the upper board can be pre-charged to the sampling voltage or common mode voltage of the previous stage, and then Figure 5 Timing drives the sampling capacitor.

[0080] Therefore, the SAR ADC front-end circuit structure proposed in the present invention can be applied to a multiplexed structure. The common synchronous sampling multiplexed structure is similar to the bottom plate sampling, such as Figure 8 As shown, the charge is latched to the bottom plate, and the conversion path is selected by Φt in the conversion stage. Therefore, each time the sampling stage is returned, the top plate of CDAC is preset to Vcm. Through the structure of the driving circuit 20, the DC signal to the Nyquist frequency signal can be fully established.

[0081] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiment described later, since it corresponds to the method, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment.

[0082] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A SAR ADC front-end circuit structure, comprising a programmable gain amplifier, an anti-aliasing filter and a driving circuit, wherein the programmable gain amplifier, the anti-aliasing filter and the driving circuit are connected in series in sequence, characterized in that: The driving circuit includes a first switch, a resistor, a filter capacitor, a buffer amplifier and a second switch; The first switch and the resistor are connected in series, and the overall input end of the first switch and the resistor connected in series is connected to the anti-aliasing filter, and the overall output end is respectively connected to one end of the filter capacitor and the input end of the capacitor array, and the resistor and the filter capacitor together form an RC filter; The buffer amplifier and the second switch are connected in series, and the overall input end is connected to the output end of the anti-aliasing filter, and the overall output end is connected to the output end of the RC filter. The buffer amplifier and the second switch are connected in series, and the overall is connected in parallel with the first switch and the resistor.

2. The SAR ADC front-end circuit structure according to claim 1, characterized in that: When the SAR ADC front-end circuit structure is in the beginning part of sampling and tracking the input signal, the first switch is opened, the second switch is closed, and the buffer amplifier is used to stabilize the input signal; When the SAR ADC front-end circuit structure is in the second half of sampling and tracking the input signal, the first switch is closed, the second switch is opened, and the input signal is filtered using the RC filter.

3. The SAR ADC front-end circuit structure according to claim 1, characterized in that: The driving circuit is an on-chip driving circuit integrated into the SAR ADC front-end circuit structure.

4. The SAR ADC front-end circuit structure according to claim 1, characterized in that: The opening and closing time of the second switch is determined by at least the system accuracy and the bandwidth of the buffer amplifier.

5. The SAR ADC front-end circuit structure according to claim 1, characterized in that: The input end of the programmable gain amplifier is used to obtain an input signal.

6. A synchronous sampling multiplexing analog-to-digital converter, characterized in that: include: The SAR ADC front-end circuit structure according to any one of claims 1 to 5; a third switch, wherein an input end of the third switch is connected to an output end of the SAR ADC front-end circuit structure; A sampling capacitor, wherein the sampling capacitor is connected in series with the third switch; a fourth switch, one end of the fourth switch being connected to the input end of the sampling capacitor, and the other end of the fourth switch being grounded; A fifth switch, one end of the fifth switch is connected to the output end of the sampling capacitor, and the other end of the fifth switch is grounded.

7. The synchronous sampling multiplexing analog-to-digital converter according to claim 6, characterized in that: After the synchronous sampling multiplexing analog-to-digital converter performs analog-to-digital conversion, the upper plate of the sampling capacitor follows the input signal from the common mode level.

8. The synchronous sampling multiplexing analog-to-digital converter according to claim 7, characterized in that: Before the synchronous sampling multiplexing analog-to-digital converter enters the signal acquisition stage, the first switch of the SAR ADC front-end circuit structure is opened and the second switch is closed, so that the buffer amplifier of the SAR ADC front-end circuit structure is connected to the signal path, and the filter capacitor of the SAR ADC front-end circuit structure is precharged to the input signal to buffer the voltage kickback caused by the sampling capacitor.

9. The synchronous sampling multiplexing analog-to-digital converter according to claim 8, characterized in that: The buffer amplifier is a high bandwidth buffer amplifier to track the upper plate of the sampling capacitor to the input level.

10. The synchronous sampling multiplexing analog-to-digital converter according to claim 9, characterized in that: Before the sampling point of the synchronous sampling multiplexing analog-to-digital converter arrives, the first switch is closed and the second switch is turned on to disconnect the buffer amplifier so that the RC buffer of the SAR ADC front-end circuit structure is connected to the signal path.

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