A clock generation circuit suitable for step-down DC voltage regulator

Abstract

The present invention discloses a clock generating circuit suitable for a step-down DC voltage regulator, which belongs to the technical field of power chip, and solves the problem that the oscillator currently used for DCDC is difficult to be unaffected by the power supply, resulting in inaccurate output clock. It includes six oscillator sub-unit circuits, each of which has two input terminals and two output terminals. Each of the oscillator sub-unit circuits is coupled with the oscillator sub-unit circuits of the previous stage and the next stage. The six oscillator sub-unit circuits are cascaded to form a ring-shaped oscillator system, and the square wave #imgabs0# output by the last oscillator sub-unit circuit is shaped by a multi-stage inverter as the output #imgabs1# of the overall oscillator. The present invention has little change with power supply voltage and temperature, good stability, and can generate a stable clock to provide to the on-time generating module of the adaptive constant-on DC voltage regulator for capacitor charging and discharging, thereby generating a fixed on-cycle.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply chips, and in particular to a clock generating circuit suitable for a step-down direct current voltage regulator. Background Art

[0002] There are many types of DC-DC power management chips, which can usually be divided into two categories: linear regulated power supplies and switching power supplies. Linear regulated power supplies are also called series regulators. Linear regulated power supplies can be regarded as a transistor connected in series between its input and output terminals. When the transistor is working normally, it can be regarded as a variable resistor, which adjusts the voltage difference between the input and output to achieve a stable voltage output. Linear regulated power supplies are cheap, simple in structure, "clean" in output, and produce little or no electronic noise. The advantages of linear regulated power supplies also include fast response speed, small output ripple and low noise level, which makes them very suitable for analog circuits and sensitive electronic equipment. The disadvantage of linear regulated power supplies is that they can only be used to step down and have low efficiency, especially when the voltage difference between the input voltage and the output voltage is relatively large. The efficiency is generally only 30%~60%, and the excess energy will fall on the conduction transistor, causing heating problems and causing disturbing problems to the system.

[0003] The switching power supply outputs a stable voltage by controlling the periodic conduction of the power switch tube. It converts direct current into high-frequency pulse current, and then stores and releases energy through components such as inductors and capacitors to generate the required output voltage. The switching power supply can achieve functions such as boost, buck, and voltage reversal. Compared with linear regulated power supplies, switching power supplies have the following advantages:

[0004] 1. High conversion efficiency: Switching power supplies are known for their high efficiency. Conventional products generally achieve an energy efficiency conversion of more than 80%, while high-performance switching power supplies built with cutting-edge technology have broken through the 90% efficiency mark, significantly reducing energy consumption and promoting the development of energy-saving technologies.

[0005] 2. Strong load capacity: The reason why the switching power supply can efficiently handle high current loads is mainly due to the extremely low on-resistance of its internal power tube, which makes the power loss in the on state negligible. This design advantage enables the switching power supply to maintain low heat loss and high-efficiency energy conversion when facing high current output requirements of several amperes. It is very suitable for electronic equipment and industrial applications that require high power output, while ensuring the stability and reliability of the system.

[0006] 3. Wide voltage regulation range and flexible use; the voltage regulation mechanism of the switching power supply relies on the precise control of the conduction and cutoff of the power tube, and dynamically responds to voltage changes by adjusting the conduction duty cycle. Even when the input voltage fluctuates, the switching power supply can ensure that the output voltage remains constant by adjusting the duty cycle, thereby achieving a high-precision voltage regulation effect. This flexible control strategy not only improves the adaptability of the power supply, but also enhances the reliability and performance stability of electronic equipment.

[0007] Compared with linear regulated power supplies, switching power supplies have disadvantages such as complex structure, large output ripple, and large inductance and capacitance that cannot be integrated. However, due to the advantages of high efficiency and high output power density, switching power supplies have been widely used in consumer electronics, industry, medical and military fields. Therefore, based on the background of my country's determination to vigorously develop the integrated circuit industry, it is of great significance to study high-performance switching power management chips.

[0008] With the increasing application of switching power supplies in many fields, chips with a single voltage output can no longer meet the market's expectations for higher power density. The power management chip required by users must not only provide stable voltage, but also be able to adapt to changing power requirements, achieve multi-channel voltage output and flexible adjustment to meet the increasingly compact and efficient electronic equipment design standards. For a single chip, as the output power continues to increase, its load is getting bigger and bigger. However, simply cascading multiple single-channel chips together not only wastes space and money, but also brings more losses. Therefore, through a chip with multiple outputs, the load power is evenly distributed to each branch, thereby reducing the load on a single branch and greatly improving the system reliability.

[0009] However, there are two challenges for multi-output switching power supplies: high switching frequency and high stability.

[0010] In terms of high switching frequency, power management chips are working towards improving power density and response time. In addition, high power density is conducive to reducing chip area and reducing costs, and fast response helps to realize high-dynamic application scenarios of chips. Since power inductors often occupy the largest area, especially dual-output chips, the best choice to increase power density is usually a higher switching frequency. In addition, a higher switching frequency can also increase the bandwidth upper limit of the control loop and improve the dynamic response speed.

[0011] In general, the current development trend of power management chips is high frequency, high precision, low power consumption, low voltage, etc. Among them, high frequency is an important technical approach to improve power density and improve dynamic response, which requires a high-performance and high-precision oscillator. A high-performance oscillator can generate a clock signal that basically does not change with changes in power supply voltage and temperature.

[0012] Based on these requirements, it is necessary to provide a clock generation circuit suitable for a step-down DC regulator.

[0013] The clock generation circuit is required to have little change with power supply voltage and temperature, good stability, and can generate a stable clock to provide to the on-time generation module of the adaptive constant conduction DC regulator for capacitor charging and discharging, thereby generating a fixed on-time cycle.

[0014] Therefore, a clock generating circuit suitable for a step-down DC regulator is proposed to solve or alleviate the above problems. Summary of the invention

[0015] The purpose of the present invention is to solve the shortcomings of the prior art and to propose a clock generation circuit suitable for a step-down DC regulator. The clock generation circuit is exquisitely designed and can maintain extremely high stability under the condition of power supply voltage fluctuations and ambient temperature changes. It can generate an accurate and constant clock signal to provide the necessary synchronization signal for the adaptive constant conduction DC regulator. This stable clock signal is used in the on-time generation module, which is responsible for controlling the charging and discharging process of the capacitor to ensure that the on-time of the DC regulator remains consistent, thereby achieving a fixed on-cycle.

[0016] In order to achieve the above object, the present invention adopts the following technical solutions:

[0017] A clock generation circuit suitable for a step-down DC regulator comprises six oscillator sub-unit circuits, each of which has two input terminals and two output terminals, each of which is coupled to the oscillator sub-unit circuits of the previous stage and the next stage, and the six oscillator sub-unit circuits are cascaded to form a ring oscillator system, and the last oscillator sub-unit circuit outputs The square wave shaped by multi-stage inverters is used as the output of the overall oscillator. , is the output voltage of the oscillator subunit circuit, It is the output voltage after shaping by the multi-stage inverter.

[0018] Preferably, the oscillator sub-unit circuit comprises a plurality of capacitors and MOS switch tubes, and the oscillator sub-unit circuit controls the charging and discharging delay of the capacitors by turning off the MOS switch tubes to generate an oscillation period.

[0019] Preferably, the calculation formula of the oscillation period is:

[0020] ,

[0021] in, is the output voltage of the oscillator subunit circuit, is the capacitance value of capacitor C1, is the capacitance value of capacitor C2, is the voltage of A, is the current at capacitor C1, is the current at capacitor C2.

[0022] Preferably, the oscillator sub-unit circuit also includes an RT current generating circuit, a voltage-current conversion circuit, an oscillation circuit VCO, and a frequency divider. The reverse end of the RT current generating circuit is coupled to the voltage-current conversion circuit, the voltage-current conversion circuit is coupled to the oscillation circuit VCO, the output end of the oscillation circuit VCO is coupled to the frequency divider, the voltage-current conversion circuit is used to divide the voltage and compare with a reference voltage to output a reference current mirrored by a low-voltage current mirror, the oscillation circuit VCO is controlled by the reference current to oscillate and output an 83ns period square wave, the frequency divider divides the 83ns period square wave output by the oscillation circuit VCO by 12 and finally outputs a 996ns period square wave.

[0023] Preferably, the RT current generating circuit comprises an RT resistor and a differential operational amplifier circuit, and the differential operational amplifier circuit makes the voltage drop on the RT resistor equal to 1.2V through clamping work and obtains a current related to the RT resistance value.

[0024] Preferably, the differential operational amplifier circuit is composed of two NMOS input pairs.

[0025] The present invention has the following beneficial effects:

[0026] The clock generation circuit in the present invention can maintain excellent stability even in the fluctuation of power supply voltage and ambient temperature. It generates a constant clock signal, which provides a key synchronization signal for the adaptive constant conduction mechanism of the DC regulator. This stable clock signal further drives the on-time generation module, which regulates the charge and discharge cycle of the capacitor to ensure that the on-time of the DC regulator is accurate and consistent, and achieves periodic stable conduction. This precise clock control is crucial to maintaining the continuity and reliability of power supply output, especially in precision electronic equipment and systems that have extremely high requirements for power supply stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0028] Figure 1It is a structural block diagram of the present invention;

[0029] Figure 2 is the wiring diagram of the present invention;

[0030] Figure 3 is a wiring diagram of the oscillator subunit circuit in the present invention;

[0031] Figure 4 Wiring diagram for the RT current generating circuit. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0033] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0035] In the description of the present invention, it should be understood that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the invention is conventionally placed when in use, or are the orientations or positional relationships conventionally understood by those skilled in the art. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0036] Furthermore, the terms “first”, “second”, “third”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0037] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0038] A clock generation circuit suitable for a step-down DC regulator, such as Figure 1 and 2 As shown, it includes six oscillator sub-unit circuits, each of which has two input terminals and two output terminals. Each oscillator sub-unit circuit is coupled to the oscillator sub-unit circuits of the previous stage and the next stage. The six oscillator sub-unit circuits are cascaded to form a ring oscillator system, and the last oscillator sub-unit circuit outputs The square wave shaped by multi-stage inverters is used as the output of the overall oscillator. , and is the bias voltage of each oscillator, which is the output of the previous transconductance amplifier. is the output voltage of the oscillator subunit circuit, It is the output voltage after shaping by the multi-stage inverter.

[0039] like Figure 3 As shown, the oscillator sub-unit circuit includes a number of capacitors and MOS switch tubes. The oscillator sub-unit circuit controls the charge and discharge delay of the capacitor by turning off the MOS switch tube to generate an oscillation period. The calculation formula of the oscillation period is:

[0040] ,

[0041] in, is the output voltage of the oscillator subunit circuit, is the capacitance value of capacitor C1, is the capacitance value of capacitor C2, is the voltage of A, is the current at capacitor C1, is the current at capacitor C2.

[0042] The working principle is to generate an oscillation cycle by delaying the charge and discharge of the capacitor. Capacitor charging process: After the last oscillator sub-unit circuit of the previous cycle is discharged, the MOS switch tube in parallel with C of the current oscillator sub-unit circuit of the current cycle is turned off, and the capacitor C begins to be charged. Capacitor discharge process: Two parts jointly determine the discharge of the capacitor, one is the effect of the latter stage on the previous stage, and the other is the charging delay of the two capacitors of this stage.

[0043] To put it simply, the output signal of the next stage makes point B a high level, and after the charging delay of the two capacitors in this stage, point A becomes a low level, and thus point C becomes a low level. This charging time directly affects the oscillation period.

[0044] The specific wiring diagram of the oscillator sub-unit circuit is as follows Figure 3 As shown, the gate of field effect transistor M1 is connected to The drain of the field effect tube M1 is grounded, the source of the field effect tube M1 is connected to the drain of the field effect tube M3, and the gate of the field effect tube M3 is connected to The source of field effect tube M3 is connected to the drain of field effect tube M4, and the gate of field effect tube M4 is connected to The source of FET M4 is connected to INTVCC, the source of FET M2 is connected to the drain of FET M3, and the gate of FET M2 is connected to 0.41V. The drain of the field effect tube M2 is connected to the capacitor C1 and then grounded. The drain of the field effect tube M2 and the capacitor C1 are connected to the output The gate of the field effect tube M5 is connected to the drain of the field effect tube M2 and the capacitor C1, the drain of the field effect tube M5 is grounded, and the gate of the field effect tube M7 is connected The source of the field effect tube M7 is connected to INTVCC, the drain of the field effect tube M7 is connected to the source of the field effect tube M6, the drain of the field effect tube M6 is connected to the source of the field effect tube M5, and the drain of the field effect tube M6 is connected to the source of the field effect tube M5. , the gate of field effect transistor M6 is connected to , the source of field effect transistor M10 is connected to INTVCC, and the gate of field effect transistor M10 is connected to The drain of field effect tube M10 is connected to the source of field effect tube M9, and the gate of field effect tube M9 is connected to The drain of the field effect tube M9 is connected to the source of the field effect tube M8, the gate of the field effect tube M8 is connected to the drain of the field effect tube M6 and the source of the field effect tube M5, the drain of the field effect tube M8 is grounded, the source of the field effect tube M12 is connected to INTVCC, and the gate of the field effect tube M12 is connected to The drain of the field effect tube M12 is connected to the source of the field effect tube M11, the gate of the field effect tube M11 is connected between the drain of the field effect tube M9 and the source of the field effect tube M8, the drain of the field effect tube M11 is grounded, a capacitor C2 is connected between the gate of the field effect tube M11, the drain of the field effect tube M9 and the source of the field effect tube M8, the other end of the capacitor C2 is grounded, and a gate of the field effect tube M11, the drain of the field effect tube M9 and the source of the field effect tube M8 are connected. The source of the field effect tube, the drain of the field effect tube is grounded, and at the same time, a source of a field effect tube is connected between the capacitor C1 and the drain of the field effect tube M2, and the drain of the field effect tube is grounded. The source of the field effect tube M13 is connected to INTVCC, the source of the field effect tube M15 is connected to INTVCC, the drain of the field effect tube M15 is connected to the source of the field effect tube M14, and the drain of the field effect tube M14 is grounded. The gate of the field effect tube M13 is connected to the gate of the field effect tube M15, and the field The drain of the field effect transistor M13 and the drain of the field effect transistor M12 are commonly connected to one of the input ends of the first NAND gate circuit, the output end of the first NAND gate circuit is connected to one of the input ends of the second NAND gate circuit, the output end of the second NAND gate circuit and the other input end of the first NAND gate circuit are commonly connected to the first inverter, the output end of the first inverter is connected to the input end of a second inverter, the output end of the second inverter is connected to the gate of the field effect transistor M14, the gate of the field effect transistor M14 is connected to the gate of the field effect transistor M15, the output end of the first inverter and the input end of the second inverter are connected to the gate of the field effect transistor connected to the gate of the field effect transistor M11 and the gate of the field effect transistor connected to the gate of the field effect transistor M5, the drain of the field effect transistor M15 and the source of the field effect transistor M14 are connected to the input end of a third inverter, the output end of the third inverter is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the input end of the third NAND gate circuit. The input is connected to the input terminal of the fifth inverter, the output terminal of the fifth inverter is connected to the input terminal of the sixth inverter, the output terminal of the sixth inverter is connected to the other input terminal of the third NAND gate circuit, and the output terminal of the third NAND gate circuit is connected to the other input terminal of the second NAND gate circuit.

[0045] The oscillator sub-unit circuit also includes an RT current generating circuit, a voltage-current conversion circuit, an oscillation circuit VCO, and a frequency divider. The reverse end of the RT current generating circuit is coupled to the voltage-current conversion circuit, the voltage-current conversion circuit is coupled to the oscillation circuit VCO, the output end of the oscillation circuit VCO is coupled to the frequency divider, the voltage-current conversion circuit is used to divide the voltage and compare with a reference voltage to output a reference current mirrored by a low-voltage current mirror, the oscillation circuit VCO is controlled by the reference current to oscillate and output an 83ns period square wave, the frequency divider divides the 83ns period square wave output by the oscillation circuit VCO by 12 and finally outputs a 996ns period square wave.

[0046] like Figure 4 As shown, the RT current generating circuit generates a current information related to the external resistor RT. This current is used as the bias current of the transconductance amplifier OTA for the control of the phase-locked loop. The FREQ pin is a PAD of the chip, and a resistor R is connected to the chip. Since the FREQ pin is connected to components outside the chip, two resistors are added for ESD protection of the MOS tube. The RT current generating circuit includes an RT resistor and a differential operational amplifier circuit. The differential operational amplifier circuit makes the voltage drop on the RT resistor equal to 1.2V through the clamping function and obtains a current related to the RT resistance value. The differential operational amplifier circuit is composed of two NMOS input pairs. The clamping function of the operational amplifier makes the voltage drop on the external resistor RT equal to 1.2V, and then obtains a current related to the RT resistance value, that is, the current I=1.2 / RT. Since the current provided by the RT current generating circuit supplies V to I, and then V to I provides current to the oscillation circuit VCO, changing the value of RT can change the output frequency of the oscillation circuit VCO.

[0047] The specific wiring diagram of the RT current generating circuit is as follows Figure 4 As shown, the source of the field effect tube M7 is connected to INTVCC, the drain of the field effect tube M7 is grounded, and the gate of the field effect tube M7 is connected between the source of the field effect tube M7 and INTVCC, thereby inputting , the source of field effect tube M12 is connected to INTVCC, the drain of field effect tube M12 is connected to the source of field effect tube M10, the gate of field effect tube M10 is also connected to INTVCC, the drain of field effect tube M10 is grounded, the source of field effect tube M5 is connected to INTVCC, the drain of field effect tube M5 is connected to the source of field effect tube M3, the drain of field effect tube M3 is connected to the source of field effect tube M1, and the gate of field effect tube M1 is connected to 1.2V , the drain of field effect transistor M1 is connected to the source of field effect transistor M8, the drain of field effect transistor M8 is grounded, the gate of field effect transistor M8 is connected to INTVCC, the source of field effect transistor M6 is connected to INTVCC, the drain of field effect transistor M6 is connected to the source of field effect transistor M4, the drain of field effect transistor M5 is connected to the source of field effect transistor M2, the drain of field effect transistor M2 is connected to the source of field effect transistor M8, the gate of field effect transistor M5 and the gate of field effect transistor M6 are connected between the drain of field effect transistor M3 and the source of field effect transistor M1, the gate and field effect transistor M2 are connected to the source of field effect transistor M4, and the gate of field effect transistor M5 and field effect transistor M6 are connected to the drain of field effect transistor M3 and the source of field effect transistor M1. The gate of field effect transistor M3 and the gate of field effect transistor M4 are connected between the drain of field effect transistor M3 and the source of field effect transistor M1, the source of field effect transistor M11 is connected to INTVCC, the drain of field effect transistor M1 is connected to the source of field effect transistor M9, the drain of field effect transistor M9 is connected to the source of field effect transistor M13, the drain of field effect transistor M13 is connected to resistor R1 and resistor R2 and then connected to the gate of field effect transistor M2, the gate of field effect transistor M13 is connected between the drain of field effect transistor M4 and the source of field effect transistor M2, and the gate of field effect transistor M13 is connected to resistor R2. and capacitor Then connect the resistor R1 to the ground, connect a PAD between the resistor R1 and the resistor R2, and then connect the resistor R T The gate output of field effect tube M11 is grounded. , the gate output of field effect transistor M9 , the gate of the field effect transistor M11 is connected between the drain of the field effect transistor M9 and the source of the field effect transistor M13.

[0048] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A clock generating circuit suitable for a step-down DC regulator, characterized in that: The invention comprises six oscillator sub-unit circuits, each of which has two input terminals and two output terminals. Each of the oscillator sub-unit circuits is coupled to the oscillator sub-unit circuits of the previous stage and the next stage. The six oscillator sub-unit circuits are cascaded to form a ring oscillator system, and the last oscillator sub-unit circuit outputs The square wave shaped by multi-stage inverters is used as the output of the overall oscillator. , is the output voltage of the oscillator subunit circuit, is the output voltage after shaping by the multi-stage inverter; The oscillator sub-unit circuit controls the charging and discharging delay of the capacitor by turning off the MOS switch tube to generate an oscillation cycle; The specific wiring method of the oscillator sub-unit circuit includes The gate of field effect tube M1 is connected The drain of the field effect tube M1 is grounded, the source of the field effect tube M1 is connected to the drain of the field effect tube M3, and the gate of the field effect tube M3 is connected to The source of field effect tube M3 is connected to the drain of field effect tube M4, and the gate of field effect tube M4 is connected to The source of FET M4 is connected to INTVCC, the source of FET M2 is connected to the drain of FET M3, and the gate of FET M2 is connected to 0.41V. The drain of the field effect tube M2 is connected to the capacitor C1 and then grounded. The drain of the field effect tube M2 and the capacitor C1 are connected to the output The gate of the field effect tube M5 is connected to the drain of the field effect tube M2 and the capacitor C1, the drain of the field effect tube M5 is grounded, and the gate of the field effect tube M7 is connected The source of the field effect tube M7 is connected to INTVCC, the drain of the field effect tube M7 is connected to the source of the field effect tube M6, the drain of the field effect tube M6 is connected to the source of the field effect tube M5, and the drain of the field effect tube M6 is connected to the source of the field effect tube M5. , the gate of field effect transistor M6 is connected to , the source of field effect transistor M10 is connected to INTVCC, and the gate of field effect transistor M10 is connected to The drain of field effect tube M10 is connected to the source of field effect tube M9, and the gate of field effect tube M9 is connected to The drain of the field effect tube M9 is connected to the source of the field effect tube M8, the gate of the field effect tube M8 is connected to the drain of the field effect tube M6 and the source of the field effect tube M5, the drain of the field effect tube M8 is grounded, the source of the field effect tube M12 is connected to INTVCC, and the gate of the field effect tube M12 is connected to The drain of the field effect tube M12 is connected to the source of the field effect tube M11, the gate of the field effect tube M11 is connected between the drain of the field effect tube M9 and the source of the field effect tube M8, the drain of the field effect tube M11 is grounded, a capacitor C2 is connected between the gate of the field effect tube M11, the drain of the field effect tube M9 and the source of the field effect tube M8, the other end of the capacitor C2 is grounded, and a gate of the field effect tube M11, the drain of the field effect tube M9 and the source of the field effect tube M8 are connected. The source of the field effect tube, the drain of the field effect tube is grounded, and at the same time, a source of a field effect tube is connected between the capacitor C1 and the drain of the field effect tube M2, and the drain of the field effect tube is grounded. The source of the field effect tube M13 is connected to INTVCC, the source of the field effect tube M15 is connected to INTVCC, the drain of the field effect tube M15 is connected to the source of the field effect tube M14, and the drain of the field effect tube M14 is grounded. The gate of the field effect tube M13 is connected to the gate of the field effect tube M15, and the field The drain of the field effect transistor M13 and the drain of the field effect transistor M12 are commonly connected to one of the input ends of the first NAND gate circuit, the output end of the first NAND gate circuit is connected to one of the input ends of the second NAND gate circuit, the output end of the second NAND gate circuit and the other input end of the first NAND gate circuit are commonly connected to the first inverter, the output end of the first inverter is connected to the input end of a second inverter, the output end of the second inverter is connected to the gate of the field effect transistor M14, the gate of the field effect transistor M14 is connected to the gate of the field effect transistor M15, the output end of the first inverter and the input end of the second inverter are connected to the gate of the field effect transistor connected to the gate of the field effect transistor M11 and the gate of the field effect transistor connected to the gate of the field effect transistor M5, the drain of the field effect transistor M15 and the source of the field effect transistor M14 are connected to the input end of a third inverter, the output end of the third inverter is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the input end of the third NAND gate circuit. The input is connected to the input terminal of the fifth inverter, the output terminal of the fifth inverter is connected to the input terminal of the sixth inverter, the output terminal of the sixth inverter is connected to the other input terminal of the third NAND gate circuit, and the output terminal of the third NAND gate circuit is connected to the other input terminal of the second NAND gate circuit.

2. A clock generating circuit suitable for a step-down DC regulator according to claim 1, characterized in that: The calculation formula of the oscillation period is: ； in, is the output voltage of the oscillator subunit circuit, is the capacitance value of capacitor C1, is the capacitance value of capacitor C2, is the voltage of A, is the current at capacitor C1, is the current at capacitor C2.

3. A clock generating circuit suitable for a step-down DC regulator according to claim 2, characterized in that: The oscillator sub-unit circuit also includes an RT current generating circuit, a voltage-current conversion circuit, an oscillation circuit VCO, and a frequency divider. The reverse end of the RT current generating circuit is coupled to the voltage-current conversion circuit, the voltage-current conversion circuit is coupled to the oscillation circuit VCO, the output end of the oscillation circuit VCO is coupled to the frequency divider, the voltage-current conversion circuit is used to divide the voltage and compare with a reference voltage to output a reference current mirrored by a low-voltage current mirror, the oscillation circuit VCO is controlled by the reference current to oscillate and output an 83ns period square wave, the frequency divider divides the 83ns period square wave output by the oscillation circuit VCO by 12 and finally outputs a 996ns period square wave.

4. The clock generating circuit for a step-down DC regulator according to claim 3, characterized in that: The RT current generating circuit includes an RT resistor and a differential operational amplifier circuit, wherein the differential operational amplifier circuit makes the voltage drop on the RT resistor equal to 1.2V through clamping work and obtains a current related to the RT resistance value; The specific wiring method of the RT current generating circuit includes connecting the source of the field effect tube M7 to INTVCC, connecting the drain of the field effect tube M7 to ground, and connecting the gate of the field effect tube M7 between the source of the field effect tube M7 and INTVCC, thereby inputting , the source of field effect tube M12 is connected to INTVCC, the drain of field effect tube M12 is connected to the source of field effect tube M10, the gate of field effect tube M10 is also connected to INTVCC, the drain of field effect tube M10 is grounded, the source of field effect tube M5 is connected to INTVCC, the drain of field effect tube M5 is connected to the source of field effect tube M3, the drain of field effect tube M3 is connected to the source of field effect tube M1, and the gate of field effect tube M1 is connected to 1.2V , the drain of field effect transistor M1 is connected to the source of field effect transistor M8, the drain of field effect transistor M8 is grounded, the gate of field effect transistor M8 is connected to INTVCC, the source of field effect transistor M6 is connected to INTVCC, the drain of field effect transistor M6 is connected to the source of field effect transistor M4, the drain of field effect transistor M5 is connected to the source of field effect transistor M2, the drain of field effect transistor M2 is connected to the source of field effect transistor M8, the gate of field effect transistor M5 and the gate of field effect transistor M6 are connected between the drain of field effect transistor M3 and the source of field effect transistor M1, the gate and field effect transistor M2 are connected to the source of field effect transistor M4, and the gate of field effect transistor M5 and field effect transistor M6 are connected to the drain of field effect transistor M3 and the source of field effect transistor M1. The gate of field effect transistor M3 and the gate of field effect transistor M4 are connected between the drain of field effect transistor M3 and the source of field effect transistor M1, the source of field effect transistor M11 is connected to INTVCC, the drain of field effect transistor M1 is connected to the source of field effect transistor M9, the drain of field effect transistor M9 is connected to the source of field effect transistor M13, the drain of field effect transistor M13 is connected to resistor R1 and resistor R2 and then connected to the gate of field effect transistor M2, the gate of field effect transistor M13 is connected between the drain of field effect transistor M4 and the source of field effect transistor M2, and the gate of field effect transistor M13 is connected to resistor R2. and capacitor Then connect the resistors R1 and R2 to the ground. The gate output of field effect tube M11 is grounded. , the gate output of field effect transistor M9 , the gate of the field effect transistor M11 is connected between the drain of the field effect transistor M9 and the source of the field effect transistor M13.

5. The clock generating circuit for a step-down DC regulator according to claim 4, characterized in that: The differential operational amplifier circuit is composed of two NMOS input pairs.

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