A fully GaN integrated bandgap reference source circuit and its manufacturing process

Abstract

The present invention relates to a fully GaN-integrated bandgap reference source circuit, comprising: a plurality of enhancement-mode GaN HEMT transistors, a plurality of lateral temperature sensor diodes, a plurality of on-chip resistors, and an epitaxial wafer; the plurality of enhancement-mode GaN HEMT transistors, the plurality of lateral temperature sensor diodes, and the plurality of on-chip resistors are all integrated on the epitaxial wafer; wherein the epitaxial wafer comprises a substrate, a nucleation layer, a buffer layer, a channel layer, an insertion layer, a barrier layer, a P-GaN layer, and a passivation layer stacked sequentially from bottom to top. The present invention utilizes all-GaN devices, which reduces chip parasitic effects, lowers costs, and improves overall performance. Through the on-chip resistors and lateral temperature sensor diodes, the reference source circuit can accurately output a temperature-independent reference voltage, and the output resistance ratio can be adjusted, resulting in a stable output.

Description

Technical Field

[0001] The present invention relates to the technical field of GaN power electronics, and in particular to a fully GaN integrated bandgap reference source circuit and a manufacturing process thereof. Background Art

[0002] Gallium Nitride (GaN), as a third-generation semiconductor, has advantages such as wide bandgap, high breakdown field strength, and high electron saturation rate. Compared with SiC, GaN with a lateral device structure is easier to integrate. In the circuit application of GaN devices, the reference source circuit is a circuit that generates a reference voltage and reference current following the startup signal of the DC (direct current) startup circuit of the power supply, and can provide stable reference voltage and reference current for other modules. However, traditional reference source circuits are mainly generated by resistor voltage division, which is easily affected by temperature interference and has low accuracy; this may cause the circuit to fail to shut down and start in time during operation, reducing circuit efficiency and possibly causing system application failures. In addition, the use of silicon-based reference source circuits will bring parasitic effects, further reducing the overall performance of the system. However, due to the low mobility of holes in gallium nitride, it is difficult to form efficient gallium nitride PMOS (Positive channel Metal Oxide Semiconductor) devices. GaN-based logic devices lack P-type devices, but traditional CMOS (Complementary Metal-Oxide-Semiconductor) logic circuit designs cannot implement them. On the other hand, the process of using epitaxial wafers with P-GaN layers to make depletion-mode HEMT (High Electron Mobility Transistor) devices is complex. The etching process can easily lead to defects on the epitaxial wafer surface, which in turn affects the reliability of the device and the performance of the integrated circuits produced by the etching process. Summary of the Invention

[0003] In order to solve the above problems existing in the prior art, the present invention provides a fully GaN integrated bandgap reference source circuit and a manufacturing process.

[0004] According to a first aspect of an embodiment of the present invention, a fully GaN-integrated bandgap reference source circuit is provided, comprising: a plurality of enhancement-mode GaN HEMT transistors, a plurality of lateral temperature sensor diodes, a plurality of on-chip resistors, and an epitaxial wafer; the plurality of enhancement-mode GaN HEMT transistors, the plurality of lateral temperature sensor diodes, and the plurality of on-chip resistors are all integrated on the epitaxial wafer; wherein the epitaxial wafer comprises a substrate, a nucleation layer, a buffer layer, a channel layer, an insertion layer, a barrier layer, a P-GaN layer, and a passivation layer stacked in sequence from bottom to top.

[0005] Optionally, the P-GaN layer includes a first P-GaN layer; the structures of the multiple enhancement-mode GaN HEMT transistors are all the same; a source and a drain are respectively arranged on both sides of the first barrier region of the barrier layer, the first P-GaN layer is located between the source and the drain, and a gate is arranged on the upper surface of the first P-GaN layer, and the source, the drain and the gate are all higher than the passivation layer.

[0006] Optionally, the P-GaN layer also includes a second P-GaN layer; the structures of the multiple lateral temperature sensor diodes are the same, a cathode located on the upper surface of the insertion layer is provided on one side of the second barrier region of the barrier layer, and an anode located on the upper surface of the barrier layer is provided on the other side of the second barrier region, the second P-GaN layer is located on the upper surface of the barrier layer, one side of the second P-GaN layer is flush with the side of the passivation layer away from the cathode, and the anode is higher than the passivation layer.

[0007] Optionally, the structures of the plurality of on-chip resistors are the same, and a first ohmic contact electrode and a second ohmic contact electrode located on the upper surface of the insertion layer are respectively provided on both sides of the third barrier region of the barrier layer.

[0008] Optionally, the plurality of enhancement-mode GaN HEMT transistors include: a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, and a transistor M8; the plurality of on-chip resistors include: an on-chip resistor R1, an on-chip resistor R2, and an on-chip resistor R3; the plurality of lateral temperature sensor diodes include: a lateral temperature sensor diode D1, a lateral temperature sensor diode D2, a lateral temperature sensor diode D3, and a lateral temperature sensor diode D4; the anode of the lateral temperature sensor diode D1 is connected to a power supply DC, and the cathode of the lateral temperature sensor diode D1 is connected to the on-chip resistor R 1; the other end of the on-chip resistor R1 is connected to the drain of the transistor M1, the source of the transistor M1 is connected to the drain of the transistor M3, the gate of the transistor M1 is connected to the gate of the transistor M2, the source of the transistor M3 is grounded, and the gate of the transistor M3 is connected to the gate of the transistor M4; the anode of the lateral temperature sensor diode D2 is connected to the power supply DC, the cathode of the lateral temperature sensor diode D2 is connected to the drain of the transistor M2, the source of the transistor M2 is connected to the drain of the transistor M4, and the drain of the transistor M4 is connected. grounded; one end of the on-chip resistor R2 is connected to the power supply DC, the other end of the on-chip resistor R2 is connected to the drain of the transistor M5, the gate of the transistor M5 is connected between the cathode of the lateral temperature sensor diode D2 and the drain of the transistor M2, and the source of the transistor M5 is grounded; the anode of the lateral temperature sensor diode D3 is connected to the power supply DC, the cathode of the lateral temperature sensor diode D3 is connected to the drain of the transistor M6, the drain of the transistor M6 is connected to the gate of the transistor M2, and the gate of the transistor M6 is connected to the on-chip resistor R2 The source of the transistor M6 is connected to the drain of the transistor M7, the gate of the transistor M7 is connected between the drain of the transistor M1 and the gate of the transistor M3, and the source of the transistor M7 is grounded; the anode of the lateral temperature sensor diode D4 is connected to the power supply DC, the cathode of the lateral temperature sensor diode D4 is connected to one end of the on-chip resistor R3, the other end of the on-chip resistor R3 is connected to the drain of the transistor M8, the gate of the transistor M8 is connected to the gate of the transistor M7, and the source of the transistor M8 is grounded.

[0009] Optionally, the substrate is made of Si, the nucleation layer is made of AlN, and the buffer layer is made of Al. 0.3 Ga 0.7 N, the material of the channel layer is GaN, the material of the insertion layer is AlN, and the material of the barrier layer is AlGaN.

[0010] According to a second aspect of an embodiment of the present invention, a process for manufacturing a fully GaN integrated bandgap reference circuit is provided, comprising:

[0011] Prepare an epitaxial wafer; wherein the epitaxial wafer comprises, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a P-GaN layer;

[0012] defining a first P-GaN region corresponding to a gate of an enhancement-mode GaN HEMT transistor on a surface of the P-GaN layer, and etching downwardly an area other than the first P-GaN region in the first region, the etching depth extending to the barrier layer;

[0013] defining a mesa region on the surface of the barrier layer, and etching downwardly an area outside the mesa region in the second region, with the etching depth extending to the buffer layer;

[0014] After depositing a passivation layer on the surface of the current device, defining a source and drain recess region for the enhancement-mode GaN HEMT transistor, a cathode recess region for the lateral temperature sensor diode, and an ohmic contact electrode recess region for the on-chip resistor on the surface of the passivation layer above the remaining P-GaN layer;

[0015] Etching downwardly the source and drain recess regions of the enhancement-mode GaN HEMT transistor, the cathode recess region of the lateral temperature sensor diode, and the ohmic contact electrode recess region of the on-chip resistor, with the etching depth extending to the barrier layer, to form corresponding electrode recesses;

[0016] Depositing ohmic contact metal in the source and drain grooves of the enhancement-mode GaN HEMT transistor, the cathode groove of the lateral temperature sensor diode, and the ohmic contact electrode grooves of the on-chip resistor to fill the corresponding electrode grooves, and making the ohmic contact metal overlap the passivation layer;

[0017] Performing a rapid thermal annealing process on the ohmic contact metal to form a source and a drain of the enhancement-mode GaN HEMT transistor, a cathode of the lateral temperature sensor diode, and a first ohmic contact electrode and a second ohmic contact electrode of the on-chip resistor;

[0018] defining an enhancement-mode GaN HEMT transistor gate metal groove region on a first P-GaN region corresponding to the gate of the enhancement-mode GaN HEMT transistor, and defining a temperature sensor diode anode groove region on a side of the lateral temperature sensor diode away from the cathode of the lateral temperature sensor diode;

[0019] Etching the metal groove region of the gate of the enhancement-mode GaN HEMT transistor downwards to a depth extending to the P-GaN layer to form a groove for the gate of the enhancement-mode GaN HEMT transistor;

[0020] Etching the anode groove area of the temperature sensor diode downwards, with the etching depth extending to the barrier layer, to form the anode groove of the temperature sensor diode;

[0021] Schottky metal is deposited in the gate groove of the enhancement-mode GaN HEMT transistor and the anode groove of the temperature sensor diode to form the gate of the enhancement-mode GaN HEMT transistor and the anode of the temperature sensor diode.

[0022] The technical solution provided by the present invention can have the following beneficial effects:

[0023] The circuit design is implemented using all-GaN devices, which reduces the overall parasitic effects of the chip, improves integration, and reduces costs. It fully utilizes the high-frequency and high-power density characteristics of GaN materials to enhance overall performance. In addition, this reference source circuit uses enhancement-mode GaN HEMT transistors, which are more suitable for the most widely used applications. Through on-chip resistors and lateral temperature sensor diodes, this reference source circuit can accurately output a temperature-independent reference voltage. The output resistance ratio can be adjusted, and the output is stable.

[0024] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following detailed description, they are used to explain the present invention but do not constitute a limitation of the present invention. In the accompanying drawings:

[0026] Figure 1 The figure is a schematic diagram of the device structure of a fully GaN integrated bandgap reference source circuit according to an exemplary embodiment.

[0027] Figure 2 The figure is a schematic structural diagram of a fully GaN integrated bandgap reference source circuit according to an exemplary embodiment.

[0028] Figure 3 The present invention is a flow chart showing a process for preparing a fully GaN integrated bandgap reference circuit according to an exemplary embodiment.

[0029] Description of Reference Numerals

[0030] 1. Enhancement-mode GaN HEMT transistor; 2. Lateral temperature sensor diode; 3. On-chip resistor; 5. Substrate; 6. Nucleation layer; 7. Buffer layer; 8. Channel layer; 9. Insertion layer; 10. Barrier layer; 11. P-GaN layer; 111. First P-GaN layer; 112. Second P-GaN layer; 12. Passivation layer; 13. Source; 14. Drain; 15. Gate; 16. Cathode; 17. Anode; 18. First ohmic contact electrode; 19. Second ohmic contact electrode. DETAILED DESCRIPTION

[0031] Figure 1 FIG. 1 is a schematic diagram of a device structure of a fully GaN integrated bandgap reference source circuit according to an exemplary embodiment. Figure 1 As shown, the fully GaN integrated bandgap reference source circuit includes: multiple enhancement-mode GaN HEMT transistors 1, multiple lateral temperature sensor diodes 2, multiple on-chip resistors and an epitaxial wafer; the multiple enhancement-mode GaN HEMT transistors 1, multiple lateral temperature sensor diodes 2 and multiple on-chip resistors 3 are all integrated on the epitaxial wafer; wherein the epitaxial wafer includes a substrate 5, a nucleation layer 6, a buffer layer 7, a channel layer 8, an insertion layer 9, a barrier layer 10, a P-GaN layer 11 and a passivation layer 12 stacked in sequence from bottom to top.

[0032] It can be understood that multiple devices are integrated on the epitaxial wafer, including three types: enhancement-mode GaN HEMT transistors, lateral temperature sensor diodes and on-chip resistors. The enhancement-mode GaN HEMT transistors have higher gate reliability.

[0033] In one embodiment, the material of the substrate 5 is Si, the material of the nucleation layer 6 is AlN, and the material of the buffer layer 7 is Al. 0.3 Ga 0.7 N, the material of the channel layer 8 is GaN, the material of the insertion layer 9 is AlN, and the material of the barrier layer 10 is AlGaN.

[0034] Optionally, the P-GaN layer 11 includes a first P-GaN layer 111; the structures of the multiple enhancement-mode GaN HEMT transistors 1 are the same; a source 13 and a drain 14 are respectively arranged on both sides of the first barrier region of the barrier layer 10, the first P-GaN layer 111 is located between the source 13 and the drain 14, and a gate 15 is arranged on the upper surface of the first P-GaN layer 111, and the source 13, the drain 14 and the gate 15 are all higher than the passivation layer 12.

[0035] It can be understood that the first p-GaN layer 111 is inserted between the gate 15 and the barrier layer 10. The first p-GaN layer 111 under the gate 15 can increase the height of the barrier layer 10, thereby raising the potential energy at the channel layer 8 under the gate 15 to above the Fermi level, thereby realizing the enhancement mode of the GaN HEMT transistor.

[0036] Optionally, the P-GaN layer 11 also includes a second P-GaN layer 112; the structures of multiple lateral temperature sensor diodes 2 are the same, and a cathode 16 located on the upper surface of the insertion layer 9 is provided on one side of the second barrier region of the barrier layer 10, and an anode 17 located on the upper surface of the barrier layer is provided on the other side of the second barrier region. The second P-GaN layer 112 is located on the upper surface of the barrier layer 10, and one side of the second P-GaN layer 112 is flush with the side of the passivation layer 12 away from the cathode 16, and the anode 17 is higher than the passivation layer 12.

[0037] It can be understood that after etching the area outside the gate 15, a cathode groove and an anode groove are defined, the etching depth of the anode groove extends to the barrier layer 10, and the etching depth of the cathode groove extends to the channel layer 8. The anode 17 is deposited with Schottky contact metal, and the cathode 16 is deposited with ohmic contact metal to realize a lateral temperature sensor.

[0038] Optionally, the structures of the multiple on-chip resistors 3 are the same, and a first ohmic contact electrode 18 and a second ohmic contact electrode 19 located on the upper surface of the insertion layer 9 are respectively provided on both sides of the third barrier region of the barrier layer 10 .

[0039] It can be understood that the P-GaN layer 11 is etched and then passivated to define an ohmic contact resistor electrode groove, the groove etching depth extends to the barrier layer 10, and ohmic contact metal is deposited in the ohmic contact resistor electrode groove to obtain a first ohmic contact electrode 18 and a second ohmic contact electrode 19 to realize on-chip resistance.

[0040] Optionally, Figure 2 FIG. 1 is a schematic structural diagram of a fully GaN integrated bandgap reference source circuit according to an exemplary embodiment. Figure 2As shown, multiple enhancement-mode GaN HEMT transistors 1 include: transistor M1, transistor M2, transistor M3, transistor M4, transistor M5, transistor M6, transistor M7 and transistor M8; multiple on-chip resistors 3 include: on-chip resistor R1, on-chip resistor R2 and on-chip resistor R3; multiple lateral temperature sensor diodes 2 include: lateral temperature sensor diode D1, lateral temperature sensor diode D2, lateral temperature sensor diode D3 and lateral temperature sensor diode D4; the anode of the lateral temperature sensor diode D1 is connected to the power supply DC, and the cathode of the lateral temperature sensor diode D1 is connected to one end of the on-chip resistor R1; the other end of the on-chip resistor R1 is connected to the drain of the transistor M1, the source of the transistor M1 is connected to the drain of the transistor M3, the gate of the transistor M1 is connected to the gate of the transistor M2, the source of the transistor M3 is grounded, and the gate of the transistor M3 is connected to the gate of the transistor M4; the anode of the lateral temperature sensor diode D2 is connected to the power supply DC, the cathode of the lateral temperature sensor diode D2 is connected to the drain of the transistor M2, and the source of the transistor M2 is connected to the drain of the transistor M4. The on-chip resistor R2 is connected to the power supply DC, the other end of the on-chip resistor R2 is connected to the drain of the transistor M5, the gate of the transistor M5 is connected between the cathode of the lateral temperature sensor diode D2 and the drain of the transistor M2, and the source of the transistor M5 is grounded; the anode of the lateral temperature sensor diode D3 is connected to the power supply DC, the cathode of the lateral temperature sensor diode D3 is connected to the drain of the transistor M6, the drain of the transistor M6 is connected to the gate of the transistor M2, and the gate of the transistor M6 is connected to The on-chip resistor R2 is connected to the drain of the transistor M5, the source of the transistor M6 is connected to the drain of the transistor M7, the gate of the transistor M7 is connected between the drain of the transistor M1 and the gate of the transistor M3, and the source of the transistor M7 is grounded; the anode of the lateral temperature sensor diode D4 is connected to the power supply DC, the cathode of the lateral temperature sensor diode D4 is connected to one end of the on-chip resistor R3, the other end of the on-chip resistor R3 is connected to the drain of the transistor M8, the gate of the transistor M8 is connected to the gate of the transistor M7, and the source of the transistor M8 is grounded.

[0041] Optionally, the first-stage circuit is a startup circuit, including a lateral temperature sensor diode D1, a lateral temperature sensor diode D2, an on-chip resistor R1, a transistor M3, and a transistor M4. The first-stage circuit is used to provide a first bias voltage VD1 and a second bias voltage VD2, and generate a current by comparing the difference between VD2 and VD1 with the on-chip resistor R1. The transistor M3 and the transistor M4 form a current mirror circuit, so that the current flowing through the lateral temperature sensor diode D1 branch is the same as the current flowing through the lateral temperature sensor diode D2 branch.

[0042] The second-stage circuit is a feedback circuit, including a lateral temperature sensor diode D3, an on-chip resistor R2, transistors M1, M2, M5, M6, and M7. The second-stage circuit is used to clamp the potential at point y to keep it consistent with the potential at point x.

[0043] The third-stage circuit is a proportional resistor output circuit, including a lateral temperature sensor diode D4, an on-chip resistor R3, and a transistor M8. Transistor M8 and transistor M3 form a current mirror circuit, which makes the current flowing through the lateral temperature sensor diode D4 branch the same as the current flowing through the lateral temperature sensor diode D1 branch, and outputs a temperature-corrected reference voltage through the output terminal.

[0044] Based on the above, a current is generated by the ratio of the difference in the forward voltage of lateral temperature sensor diodes D1 and D2 to the on-chip resistor R1. Transistors M3 and M4 are connected to form a current mirror circuit, transferring the current from on-chip resistor R1 to the branch of lateral temperature sensor diode D2. Transistors M7 and M8 are connected at their gate terminals and connected between the gate terminals of transistors M3 and M4, forming a current mirror circuit that transfers the current from on-chip resistor R1 to the branches of lateral temperature sensor diodes D3 and D4. The sum of the forward voltage drop of lateral temperature sensor diode D4 and on-chip resistor R3 is subtracted from the DC voltage of the power supply to produce a temperature-corrected reference voltage at the output terminal. The current mirror circuit and the output characteristic curves of the transistors are used to clamp the potential at point y to the same level as the potential at point x. For example, when the potential at point y increases, the feedback circuit provides negative feedback, which lowers the potential at point y.

[0045] Specifically, the first-stage circuit can provide current to the second-stage circuit and the third-stage circuit through a current mirror circuit; the second-stage circuit can clamp the potential at point y of the lateral temperature sensor diode D2 branch in the first-stage circuit so that it remains the same as the potential at point x of the lateral temperature sensor diode D1 branch; the third-stage circuit can convert the current transmitted in the first-stage circuit into a voltage after passing through a resistor, and after temperature correction, output a stable reference voltage through the output terminal Vout.

[0046] Figure 3 FIG. 1 is a flow chart showing a process for preparing a fully GaN integrated bandgap reference circuit according to an exemplary embodiment. Figure 3 Shown, including:

[0047] S1. Prepare an epitaxial wafer; wherein the epitaxial wafer includes a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a P-GaN layer from bottom to top.

[0048] S2. Define a P-GaN region corresponding to the gate of the enhancement-mode GaN HEMT transistor on the surface of the P-GaN layer, and etch downward the region other than the P-GaN region in the first region, with the etching depth extending to the barrier layer.

[0049] It can be understood that the first region in S2 is the region where the enhancement mode GaN HEMT transistor to be manufactured is located. Figure 1 The first region is the source 13 and the drain 14 and the region therebetween.

[0050] S3. Define a mesa region on the surface of the barrier layer, and perform downward etching on the region outside the mesa region in the second region, with the etching depth extending to the buffer layer.

[0051] It can be understood that S3 is to separate the various devices. The mesa area can be understood as the area of each device, and the second area can be understood as the entire area of the epitaxial wafer. Etching down the gap area between each mesa area can separate the various devices. Figure 1 The etched area is the area between the source electrode 13 and the first ohmic contact electrode 18 .

[0052] S4. After depositing a passivation layer on the surface of the current device, define, on the surface of the passivation layer above the remaining P-GaN layer, source and drain recess regions of the enhancement-mode GaN HEMT transistor, a cathode recess region of the lateral temperature sensor diode, and an ohmic contact electrode recess region of the on-chip resistor.

[0053] S5. Etching downwards the source and drain groove regions of the enhancement-mode GaN HEMT transistor, the cathode groove region of the lateral temperature sensor diode, and the ohmic contact electrode groove region of the on-chip resistor, with the etching depth extending to the barrier layer to form corresponding electrode grooves.

[0054] S6. Depositing ohmic contact metal in the source and drain grooves of the enhancement-mode GaN HEMT transistor, the cathode groove of the lateral temperature sensor diode, and the ohmic contact electrode grooves of the on-chip resistor to fill the corresponding electrode grooves, and making the ohmic contact metal overlap the passivation layer.

[0055] S7. Perform a rapid thermal annealing process on the ohmic contact metal to form a source and a drain of the enhancement-mode GaN HEMT transistor, a cathode of the lateral temperature sensor diode, and a first ohmic contact electrode and a second ohmic contact electrode of the on-chip resistor.

[0056] S8. Define a gate metal groove region of the enhancement-mode GaN HEMT transistor on the P-GaN region corresponding to the gate of the enhancement-mode GaN HEMT transistor, and define a temperature sensor diode anode groove region on a side of the lateral temperature sensor diode away from the cathode of the lateral temperature sensor diode.

[0057] S9. Etching the metal groove region of the gate of the enhancement-mode GaN HEMT transistor downwards, with the etching depth extending to the P-GaN layer, to form a gate groove of the enhancement-mode GaN HEMT transistor.

[0058] S10, etching the temperature sensor diode anode groove region downwards, with the etching depth extending to the barrier layer, to form the temperature sensor diode anode groove.

[0059] S11. Depositing Schottky metal in the gate groove of the enhancement-mode GaN HEMT transistor and the anode groove of the temperature sensor diode to form the gate of the enhancement-mode GaN HEMT transistor and the anode of the temperature sensor diode.

[0060] Optionally, the fabricated device includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, an on-chip resistor R1, an on-chip resistor R2, an on-chip resistor R3, a lateral temperature sensor diode D1, a lateral temperature sensor diode D2, a lateral temperature sensor diode D3, and a lateral temperature sensor diode D4; after depositing Schottky metal in a gate groove of the enhancement-mode GaN HEMT transistor and an anode groove of the temperature sensor diode to form a gate of the enhancement-mode GaN HEMT transistor and an anode of the temperature sensor diode, the device further includes:

[0061] By depositing metal, the lateral temperature sensor diode D1, the on-chip resistor R1, the transistor M1, and the transistor M3 are connected in series as a first series branch;

[0062] Connecting the lateral temperature sensor diode D2, transistor M2, and transistor M4 in series as a second series branch;

[0063] The on-chip resistor R2 and the transistor M5 are connected in series to form a third series branch;

[0064] Connecting the lateral temperature sensor diode D3, transistor M6, and transistor M7 in series to form a fourth series branch;

[0065] Connecting the lateral temperature sensor diode D4, the on-chip resistor R3, and the transistor M8 in series as a fifth series branch;

[0066] Connecting the first series-connected branch, the second series-connected branch, the third series-connected branch, the fourth series-connected branch, and the fifth series-connected branch in parallel;

[0067] The gate of transistor M1 is short-circuited with the gate of transistor M2, the gate of transistor M3 is short-circuited with the gate of transistor M4, the gate and drain of transistor M3 are short-circuited, the gate of transistor M5 is short-circuited with the drain of transistor M2, the gate of transistor M6 is short-circuited with the drain of transistor M5, the drain of transistor M6 is short-circuited with the gate of transistor M2, the gate of transistor M7 is short-circuited with the gate of transistor M8, and the gate of transistor M7 is short-circuited with the gates of transistors M3 and M4.

[0068] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the scope of protection of the present invention.

[0069] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0070] In addition, the various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A fully GaN integrated bandgap reference source circuit, characterized in that: include: Multiple enhancement-mode GaN HEMT transistors, multiple lateral temperature sensor diodes, multiple on-chip resistors and epitaxial wafers; Multiple enhancement-mode GaN HEMT transistors, multiple lateral temperature sensor diodes, and multiple on-chip resistors are integrated on an epitaxial wafer. The epitaxial wafer includes a substrate, a nucleation layer, a buffer layer, a channel layer, an insertion layer, a barrier layer, a P-GaN layer, and a passivation layer stacked in sequence from bottom to top. Among them, multiple enhancement-mode GaN HEMT transistors include: transistors M1 to M8; multiple on-chip resistors include: on-chip resistors R1 to R3; multiple lateral temperature sensor diodes include: diodes D1 to D4; the anode of diode D1 is connected to the power supply DC, and the cathode of diode D1 is connected to one end of the on-chip resistor R1; the other end of the on-chip resistor R1 is connected to the drain of transistor M1, the source of transistor M1 is connected to the drain of transistor M3, the gate of transistor M1 is connected to the gate of transistor M2, the source of transistor M3 is grounded, and the gate of transistor M3 is connected to the gate of transistor M4; the anode of diode D2 is connected to the power supply DC, the cathode of diode D2 is connected to the drain of transistor M2, the source of transistor M2 is connected to the drain of transistor M4, and the drain of transistor M4 is grounded; one end of the on-chip resistor R2 is connected to the power supply DC, and the other end of the on-chip resistor R2 is connected to The drain of transistor M5 is connected, the gate of transistor M5 is connected between the cathode of diode D2 and the drain of transistor M2, and the source of transistor M5 is grounded; the anode of diode D3 is connected to power supply DC, the cathode of diode D3 is connected to the drain of transistor M6, the drain of transistor M6 is connected to the gate of transistor M2, the gate of transistor M6 is connected between on-chip resistor R2 and the drain of transistor M5, the source of transistor M6 is connected to the drain of transistor M7, the gate of transistor M7 is connected between the drain of transistor M1 and the gate of transistor M3, and the source of transistor M7 is grounded; the anode of diode D4 is connected to power supply DC, the cathode of diode D4 is connected to one end of on-chip resistor R3, the other end of on-chip resistor R3 is connected to the drain of transistor M8, the gate of transistor M8 is connected to the gate of transistor M7, and the source of transistor M8 is grounded.

2. The fully GaN integrated bandgap reference source circuit according to claim 1, characterized in that: The P-GaN layer includes a first P-GaN layer; the structures of the multiple enhancement-mode GaN HEMT transistors are all the same; a source and a drain are respectively arranged on both sides of the first barrier region of the barrier layer, the first P-GaN layer is located between the source and the drain, and a gate is arranged on the upper surface of the first P-GaN layer, and the source, the drain and the gate are all higher than the passivation layer.

3. The fully GaN integrated bandgap reference source circuit according to claim 1, characterized in that: The P-GaN layer also includes a second P-GaN layer; the structures of the multiple lateral temperature sensor diodes are the same, a cathode located on the upper surface of the insertion layer is provided on one side of the second barrier region of the barrier layer, and an anode located on the upper surface of the barrier layer is provided on the other side of the second barrier region. The second P-GaN layer is located on the upper surface of the barrier layer, and one side of the second P-GaN layer is flush with the side of the passivation layer away from the cathode, and the anode is higher than the passivation layer.

4. The fully GaN integrated bandgap reference source circuit according to claim 1, characterized in that: The structures of the plurality of on-chip resistors are all the same. A first ohmic contact electrode and a second ohmic contact electrode located on the upper surface of the insertion layer are respectively provided on both sides of the third barrier region of the barrier layer.

5. The fully GaN integrated bandgap reference source circuit according to claim 1, characterized in that: The material of the substrate is Si, the material of the nucleation layer is AlN, and the material of the buffer layer is Al 0.3 Ga 0.7 N, the material of the channel layer is GaN, the material of the insertion layer is AlN, and the material of the barrier layer is AlGaN.

6. A process for manufacturing a fully GaN integrated bandgap reference circuit, characterized in that: include: Prepare an epitaxial wafer; wherein the epitaxial wafer includes a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a P-GaN layer from bottom to top; defining a first P-GaN region corresponding to a gate of an enhancement-mode GaN HEMT transistor on a surface of the P-GaN layer, and etching downwardly an area other than the first P-GaN region in the first region to a depth extending to the barrier layer; defining a mesa region on the surface of the barrier layer, and etching downwardly the area outside the mesa region in the second region, with the etching depth extending to the buffer layer; After depositing a passivation layer on the surface of the current device, defining a source and drain recess region of the enhancement mode GaN HEMT transistor, a cathode recess region of the lateral temperature sensor diode, and an ohmic contact electrode recess region of the on-chip resistor on the surface of the passivation layer above the remaining P-GaN layer; Etching the source and drain recesses of the enhancement-mode GaN HEMT transistor, the cathode recesses of the lateral temperature sensor diode, and the ohmic contact electrode recesses of the on-chip resistor downwards, extending the etching depth to the barrier layer to form corresponding electrode recesses; Depositing ohmic contact metal in the source and drain grooves of the enhancement-mode GaN HEMT transistor, the cathode groove of the lateral temperature sensor diode, and the ohmic contact electrode grooves of the on-chip resistor to fill the corresponding electrode grooves, and making the ohmic contact metal overlap the passivation layer; Performing a rapid thermal annealing process on the ohmic contact metal to form the source and drain of the enhancement-mode GaN HEMT transistor, the cathode of the lateral temperature sensor diode, and the first and second ohmic contact electrodes of the on-chip resistor; defining a gate metal recess region of the enhancement-mode GaN HEMT transistor on the first P-GaN region corresponding to the gate of the enhancement-mode GaN HEMT transistor, and defining an anode recess region of the temperature sensor diode on a side of the lateral temperature sensor diode away from the cathode of the lateral temperature sensor diode; Etching the metal groove region of the gate of the enhancement-mode GaN HEMT transistor downwards, with the etching depth extending to the P-GaN layer, to form a gate groove of the enhancement-mode GaN HEMT transistor; Etching the anode groove area of the temperature sensor diode downwards, with the etching depth extending to the barrier layer, to form the anode groove of the temperature sensor diode; Depositing Schottky metal in the gate groove of the enhancement-mode GaN HEMT transistor and the anode groove of the temperature sensor diode to form the gate of the enhancement-mode GaN HEMT transistor and the anode of the temperature sensor diode; Among them, multiple enhancement-mode GaN HEMT transistors include: transistors M1 to M8; multiple on-chip resistors include: on-chip resistors R1 to R3; multiple lateral temperature sensor diodes include: diodes D1 to D4; the anode of diode D1 is connected to the power supply DC, and the cathode of diode D1 is connected to one end of the on-chip resistor R1; the other end of the on-chip resistor R1 is connected to the drain of transistor M1, the source of transistor M1 is connected to the drain of transistor M3, the gate of transistor M1 is connected to the gate of transistor M2, the source of transistor M3 is grounded, and the gate of transistor M3 is connected to the gate of transistor M4; the anode of diode D2 is connected to the power supply DC, the cathode of diode D2 is connected to the drain of transistor M2, the source of transistor M2 is connected to the drain of transistor M4, and the drain of transistor M4 is grounded; one end of the on-chip resistor R2 is connected to the power supply DC, and the other end of the on-chip resistor R2 is connected to The drain of transistor M5 is connected, the gate of transistor M5 is connected between the cathode of diode D2 and the drain of transistor M2, and the source of transistor M5 is grounded; the anode of diode D3 is connected to power supply DC, the cathode of diode D3 is connected to the drain of transistor M6, the drain of transistor M6 is connected to the gate of transistor M2, the gate of transistor M6 is connected between on-chip resistor R2 and the drain of transistor M5, the source of transistor M6 is connected to the drain of transistor M7, the gate of transistor M7 is connected between the drain of transistor M1 and the gate of transistor M3, and the source of transistor M7 is grounded; the anode of diode D4 is connected to power supply DC, the cathode of diode D4 is connected to one end of on-chip resistor R3, the other end of on-chip resistor R3 is connected to the drain of transistor M8, the gate of transistor M8 is connected to the gate of transistor M7, and the source of transistor M8 is grounded.

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