FPGA architecture implementing out-of-band bridging, out-of-band bridging system, method, server

Abstract

The present disclosure provides a field programmable gate array structure, an out-of-band bridging system, a method and a server for realizing out-of-band bridging, relates to the technical field of computers, and particularly relates to a server. The specific implementation scheme is as follows: the field programmable gate array structure comprises at least two first data interface modules, at least two second data interface modules and a cache module, each first data interface module is matched with each in-band data interface module, each second data interface module is matched with each management data interface module, the cache module is used for caching data of each first data interface module and data of each second data interface module, and each second data interface module performs data transmission with at least two first data interface modules through the cache module.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, in particular to a server, and more particularly to a field programmable gate array structure for implementing out-of-band bridging, an out-of-band bridging system, a method and a server. BACKGROUND

[0002] With the deepening of the demand for system on chip (SoC) array servers (hereinafter referred to as SoC array servers), the market requirements for the SoC array servers are becoming higher and higher, not only high density and high performance, but also adding various out-of-band management functions to ensure better operation and maintenance. As a bridge between the in-band part and the out-of-band management controller, the out-of-band bridging system plays an important role in the implementation of the out-of-band management function. SUMMARY

[0003] DISCLOSURE

[0004] The present disclosure provides a field programmable gate array structure for implementing out-of-band bridging, an out-of-band bridging system, a method and a server.

[0005] According to an aspect of the present disclosure, a field programmable gate array structure for implementing out-of-band bridging is provided, comprising:

[0006] at least two first data interface modules, each of the first data interface modules matching a respective in-band data interface module;

[0007] at least two second data interface modules, each of the second data interface modules matching a respective management data interface module;

[0008] a cache module, the cache module being configured to cache data of each of the first data interface modules and data of each of the second data interface modules; wherein each of the second data interface modules is configured to perform data transmission with at least two of the first data interface modules through the cache module.

[0009] According to another aspect of the present disclosure, an out-of-band bridging system is provided, comprising: at least two field programmable gate array structures according to any of the embodiments of the present disclosure.

[0010] According to another aspect of the present disclosure, an array server is provided, comprising: a management controller, a field programmable gate array structure according to any of the embodiments of the present disclosure, and at least two computing units;

[0011] wherein the field programmable gate array structure is configured to bridge the management controller and the at least two computing units.

[0012] According to another aspect of the present disclosure, a method for implementing out-of-band bridging in a field programmable gate array structure is provided, comprising:

[0013] data transmission is performed between the first data interface module and the in-band data interface module; wherein the number of the first data interface module is at least two;

[0014] data transmission is performed between the second data interface module and the management data interface module;

[0015] data of each first data interface module and data of the second data interface module are cached by the cache module; wherein each second data interface module performs data transmission with at least two first data interface modules through the cache module.

[0016] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present disclosure, nor to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings are used to better understand the present scheme, and do not constitute a limitation on the present disclosure. Among them:

[0018] Figure 1 A functional structure schematic diagram of an FPGA for implementing out-of-band bridging is provided for the embodiments of the present disclosure;

[0019] Figure 2 Another functional structure schematic diagram of an FPGA for implementing out-of-band bridging is provided for the embodiments of the present disclosure;

[0020] Figure 3 Another functional structure schematic diagram of an FPGA for implementing out-of-band bridging is provided for the embodiments of the present disclosure;

[0021] Figure 4 A structure schematic diagram of an array server is provided for the embodiments of the present disclosure;

[0022] Figure 5 Another structure schematic diagram of an array server is provided for the embodiments of the present disclosure;

[0023] Figure 6 A flowchart of a method for implementing out-of-band bridging in an FPGA is provided according to the embodiments of the present disclosure;

[0024] Figure 7 Another flowchart of a method for implementing out-of-band bridging in an FPGA is provided according to the embodiments of the present disclosure;

[0025] Figure 8is a flowchart of another method for implementing out-of-band bridging in an FPGA according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] Exemplary embodiments of the present disclosure are described herein with reference to the accompanying drawings, which are provided for the purpose of illustration only. It will be appreciated that various modifications and changes can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. It is to be understood that the foregoing description and figures are merely illustrative of exemplary embodiments of the present disclosure, and various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. As such, although the present disclosure has been described in detail with reference to exemplary embodiments, it is not intended to be limited to the embodiments described herein. Rather, it is to be understood that various modifications and changes can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. It is therefore intended that the present disclosure not be limited to the described embodiments, but that the present disclosure can include all modifications and alternatives within the scope and spirit of the present disclosure.

[0027] An FPGA (Field Programmable Gate Array) is a product further developed on the basis of programmable devices such as PAL (Programmable Array Logic) and GAL (Generic Array Logic). The FPGA is a semi-custom circuit in the field of ASIC (Application Specific Integrated Circuit) and solves the disadvantages of custom circuits and the limited number of gate circuits of original programmable devices. Specifically, the FPGA adopts the concept of a logic unit array (or gate array), which includes a plurality of logic units and internal connections, etc. The logic function of a module composed of the logic units and the connection mode between the modules can be determined by configuring the values of the logic units, and the function implemented by the FPGA can be ultimately determined. The main difficulty in FPGA design is to be familiar with the hardware system and internal resources and to be able to effectively coordinate between modules. Figure 1 A functional structure diagram of an FPGA for implementing out-of-band bridging is provided according to an embodiment of the present disclosure. Referring to FIG. 1, Figure 1 The FPGA 100 includes:

[0028] at least two first data interface modules 110, each first data interface module 110 being matched with each in-band data interface module (not shown in the figure) respectively; Figure 1

[0029] at least two second data interface modules 120, each second data interface module 120 being matched with each management data interface module (not shown in the figure) respectively; Figure 1

[0030] ​​The cache module 130 is configured to cache data of each first data interface module 110 and data of each second data interface module 120. Each second data interface module 120 is configured to perform data transmission with at least two first data interface modules 110 through the cache module 130.

[0031] The in-band data interface module is a data interface of an in-band part of the server. The in-band part includes a computing unit and a switch unit, for example. The in-band data interface module provided by the present disclosure is particularly suitable for a System on a Chip (SoC) array server and other array servers with the same architecture as the SoC array server. The management data interface module is a data interface of a management controller. The management controller is configured to implement management of system information, real-time serial port control, firmware update, and the like of the in-band computing unit. The management controller is a Baseboard Management Controller (BMC), for example.

[0032] In the FPGA, the first data interface module 110 is matched with the in-band data interface module, the second data interface module 120 is matched with the management data interface module, and the cache module 130 is configured to cache data of the first data interface module 110 and the second data interface module 120. In this way, the at least two first data interface modules 110 can send data to the second data interface module 120 after caching through the cache module 130, and the out-of-band bridging function can be implemented through the FPGA.

[0033] Generally, the number of computing units of the in-band part is large, and thus the number of in-band data interface modules is greater than the number of management data interface modules.

[0034] Continuing to refer to Figure 1In some embodiments, the at least two first data interface modules 110 are respectively a first data interface module 111, a first data interface module 112, a first data interface module 113, a first data interface module 114, a first data interface module 115, a first data interface module 116, a first data interface module 117, and a first data interface module 118; and the at least two second data interface modules 120 are respectively a second data interface module 121, a second data interface module 122, and a third data interface module 123. The first data interface module 111, the first data interface module 114, and the first data interface module 117 all transmit data with the second data interface module 121 through the cache module 130; the first data interface module 112, the first data interface module 115, and the first data interface module 118 all transmit data with the second data interface module 122 through the cache module 130; and the first data interface module 113 and the first data interface module 116 both transmit data with the second data interface module 123 through the cache module 130.

[0035] Exemplarily, the method for implementing out-of-band bridging in the FPGA includes: transmitting data with each first data interface module 110 (including the first data interface module 111, the first data interface module 112, the first data interface module 113, the first data interface module 114, the first data interface module 115, the first data interface module 116, the first data interface module 117, and the first data interface module 118) and each in-band data interface module; storing the received data in the cache module 130; and each second data interface module 120 (including the second data interface module 121, the second data interface module 122, and the third data interface module 123) receives the cached data sent by the cache module 130 in sequence and then transmits the data to each management data interface module. The second data interface module 121 receives the data cached by the first data interface module 111, the first data interface module 114, and the first data interface module 117; the second data interface module 122 receives the data cached by the first data interface module 112, the first data interface module 115, and the first data interface module 118; and the second data interface module 123 receives the data cached by the first data interface module 113 and the first data interface module 116.

[0036] It should be noted that, in the above embodiments, the number of the first data interface modules 110 is exemplarily shown as 8, and the number of the second data interface modules 120 is exemplarily shown as 3, which is not a limitation of the present disclosure. In other embodiments, the number of the first data interface modules 110 and the number of the second data interface modules 120 can be set as needed.

[0037] It should be further noted that in the above embodiments, one second data interface module 120 corresponds to two first data interface modules 110 is exemplarily shown, for example, the second data interface module 123; one second data interface module 120 corresponds to three first data interface modules 110 is also shown, for example, the second data interface module 121 and the second data interface module 122; not limited to the disclosure, in other embodiments, the number of first data interface modules 110 corresponding to the second data interface module 120 can also be set to four, five or more as needed.

[0038] The number of the first data interface module 110 and the second data interface module 120 of the FPGA in the embodiments of the disclosure is set flexibly, when the number of pins of a piece of FPGA is large, dozens or even hundreds of first data interface modules can be set, therefore, under the allowed conditions, a large number of first data interface modules 110 and second data interface modules 120 can be set.

[0039] In related embodiments for implementing out-of-band bridging, the out-of-band bridging function is implemented by stacking interface chips and microprocessor chips, wherein one interface chip can only implement the connection of a few interfaces, which makes the number of peripheral devices of the out-of-band bridging very large, and the number of peripheral devices increases exponentially with the number of in-band computing units, resulting in high cost. As can be seen, the FPGA in the embodiments of the disclosure can reduce the number of peripheral devices to reduce the cost when implementing out-of-band bridging, and the more the number of first data interface modules 110 in the FPGA, the more the cost is reduced.

[0040] In addition, in related embodiments for implementing out-of-band bridging, part of the data transmission function is limited by the cache and the link quality, thereby simplifying part of the function. For example, for the Universal Asynchronous Receiver / Transmitter (UART) interface type, UART data is concurrent, that is, data is sent at the same time, therefore, a chip with cache function needs to be additionally set in the out-of-band bridging, when the density of the computing unit exceeds a certain number, the requirement for cache is also increased, which makes the out-of-band bridging of UART impossible; for example, for the Universal Serial Bus (USB) interface type, the USB data needs to set a complex link, and the interface chip is stacked, resulting in a link quality problem, when the density of the computing unit exceeds a certain number, the out-of-band bridging function of USB cannot be implemented due to too many stacked layers. The FPGA in the embodiments of the disclosure can use the internal cache module 130 to implement out-of-band bridging, without using the device stacking method, thereby being able to implement the data transmission of UART and USB.

[0041] Further, the implementation of the out-of-band bridging function has low requirements on the device performance of the FPGA, and can be applied to more types of models, thereby further reducing the cost.

[0042] Figure 2 Another function structure diagram of the FPGA for implementing the out-of-band bridging is provided by the embodiments of the present disclosure. Referring to Figure 2 In an embodiment, optionally, each first data interface module 110 is divided into at least two groups of data interface modules; each group of data interface modules includes at least two first data interface modules 110 of different types, and each group of data interface modules is used to match the in-band data interface module of one computing unit in the array server. For example, the first data interface module 111, the first data interface module 112, and the first data interface module 113 form one group of data interface modules, which are used to match one computing unit and implement the out-of-band bridging of the computing unit; the first data interface module 114, the first data interface module 115, and the first data interface module 116 form another group of data interface modules, which are used to match another computing unit and implement the out-of-band bridging of the computing unit.

[0043] The embodiments of the present disclosure match each computing unit by grouping each first data interface module 110, so that the logic in the FPGA is clear, and the program design difficulty is simplified.

[0044] In an embodiment, optionally, the computing unit of the array server includes a SoC computing unit. The SoC computing unit can be used in combination or separately according to application requirements, and is flexible to use. The FPGA for implementing the out-of-band bridging provided by the present disclosure also has the effect of flexible application, and is suitable for the SoC computing unit.

[0045] Continuously referring to Figure 2In an embodiment, optionally, the number of the second data interface modules 120 is the same as the number of the types of the first data interface modules 110; one second data interface module 120 corresponds to one type of the first data interface modules 110. For example, the types of the first data interface module 111, the first data interface module 112 and the first data interface module 113 in one data interface group are different, and the types of the first data interface module 114, the first data interface module 115 and the first data interface module 116 in another data interface group are different. The type of the first data interface module 111 is the same as the type of the first data interface module 114, the type of the first data interface module 112 is the same as the type of the first data interface module 115, and the type of the first data interface module 113 is the same as the type of the first data interface module 116. That is, there are three types of the first data interface modules 110 in the FPGA, and accordingly, there are three second data interface modules 120, which are the second data interface module 121, the second data interface module 122 and the second data interface module 123. The second data interface module 121 corresponds to the first data interface module 111 and the first data interface module 114 of the same type, the second data interface module 122 corresponds to the first data interface module 112 and the first data interface module 115 of the same type, and the second data interface module 123 corresponds to the first data interface module 113 and the first data interface module 116 of the same type.

[0046] The embodiment of the present disclosure is advantageous for packing and buffering the data of the same type by setting one second data interface module 120 corresponding to one type of the first data interface modules 110, thereby simplifying the design difficulty of the FPGA.

[0047] In the above embodiments, there are various types of the first data interface modules 110, such as IIC (Inter-Integrated Circuit), UART, USB and SPI (Serial Peripheral Interface), and there are various types of the second data interface modules 120, such as IIC, UART, USB and SPI. The following is a detailed description, but is not a limitation of the present disclosure.

[0048] In an embodiment, optionally, the types of the first data interface modules 110 include at least one of the following:

[0049] IIC slave, the IIC slave is used to match the IIC master;

[0050] An out-of-band UART (Universal Asynchronous Receiver Transmitter, hereinafter referred to as an out-of-band UART) is used to match an in-band UART (Universal Asynchronous Receiver Transmitter, hereinafter referred to as an in-band UART);

[0051] A first USB (Universal Serial Bus) physical layer (hereinafter referred to as a first USB physical layer) is used to match an in-band USB (Universal Serial Bus) device (hereinafter referred to as an in-band USB device); the FPGA further comprises an out-of-band USB (Universal Serial Bus) host (hereinafter referred to as an out-of-band USB host) for managing data of at least two first USB physical layers.

[0052] The IIC is a serial communication bus using a master-slave architecture, and through the IIC, system information or basic information of the computing unit can be obtained. In some embodiments, an IIC host is arranged in the computing unit, and an IIC slave is arranged in the FPGA to match the master and the slave. Specifically, the plurality of IIC slaves corresponding to the plurality of computing units cache the system information or basic information of the plurality of computing units received in the cache module 130, so that the second data interface module 120 obtains the data in a polling or interrupt manner. The embodiment of the present disclosure uses the FPGA to realize the out-of-band bridging function of the IIC host in the computing unit, without using interface chips and cache chips for stacking, thereby reducing the number of out-of-band devices and reducing the cost; and the more the number of computing units corresponding to the FPGA, the more significant the effect.

[0053] The UART is a universal serial data bus used for asynchronous communication, and the bus is bidirectional communication, which can realize full-duplex transmission and reception. Through the UART, the printing and log information of the computing unit can be transmitted, so that the computing unit is controlled in real time through the serial port. Specifically, the plurality of out-of-band UARTs corresponding to the plurality of computing units cache the printing and log information of the plurality of computing units received in the cache module 130, so that the second data interface module 120 obtains the data in a polling or interrupt manner. The embodiment of the present disclosure uses the FPGA to realize the out-of-band bridging function of the UART in the computing unit, without using interface chips and cache chips for stacking, thereby reducing the number of out-of-band devices and reducing the cost; and the more the number of computing units corresponding to the FPGA, the more significant the effect.

[0054] The USB is a kind of serial bus standard, and is also a kind of input / output interface technical specification, and firmware updating and flashing can be carried out on the computing unit through the USB. The USB has two interfaces of host and device, the USB host can play a control role, and the USB device is controlled. The USB physical layer (phy) is arranged between the USB host and the USB device to provide a bridge for the digital and modular component interface. In some embodiments, the USB device is arranged in the computing unit, and the first USB physical layer is arranged in the FPGA for matching. Specifically, the out-of-band USB host can be switched to different first USB physical layers to sequentially send firmware update information to a plurality of in-band USB devices corresponding to a plurality of computing units. The out-of-band bridging function of the USB in the computing unit is realized by the FPGA in the embodiment of the present disclosure, without using an interface chip for superposition, so that the link length is shortened, thereby facilitating to avoid the design difficulty caused by the link problem, so as to simplify the link design of the out-of-band bridging, reduce the number of out-of-band devices, and reduce the cost. The more the number of computing units corresponding to the FPGA is, the more significant the effect is. Through the switching function of the out-of-band USB host, data transmission can be carried out on each first USB physical layer in turn, which is beneficial to saving the logic resource of the FPGA.

[0055] In an embodiment, optionally, the type of the second data interface module 120 includes:

[0056] The SPI slave is used for matching the SPI master; wherein one SPI slave is used for data transmission with each IIC slave; and / or one SPI slave is used for data transmission with each out-of-band UART.

[0057] The second USB physical layer is used for matching the USB host; the FPGA further includes an out-of-band USB device, and the out-of-band USB device and the second USB physical layer are transmission media between the out-of-band USB host and the USB host.

[0058] The SPI is a high-speed, full-duplex, synchronous communication bus, allowing the controller to communicate with various peripheral devices in a serial manner, and exchange data. In some embodiments, an SPI host is arranged in the management controller, and an SPI slave is arranged in the FPGA to match the master and slave. Specifically, the SPI slave obtains the IIC data or UART data buffered in the cache module 130 in a polling or interrupt manner. The embodiment of the present disclosure uses the FPGA to implement the out-of-band bridging function of the SPI host in the management controller, without using interface chips and cache chips for stacking, thereby reducing the number of out-of-band devices and lowering the cost.

[0059] Corresponding to the setting mode of the first USB physical layer and the out-of-band USB host, the function of the second USB physical layer and the out-of-band USB device is that the second USB physical layer matches the management USB host in the management controller, and the second USB physical layer serves as an interface bridge between the management USB host and the out-of-band USB device. The embodiment of the present disclosure uses the FPGA to implement the out-of-band bridging function of the USB in the management controller, without using interface chips for stacking, thereby shortening the link length, which is conducive to avoiding the design difficulty caused by the link problem, thereby simplifying the link design of the out-of-band bridging, reducing the number of out-of-band devices, and lowering the cost.

[0060] Figure 3 Another functional structure diagram of the FPGA for implementing the out-of-band bridging provided by the embodiment of the present disclosure is provided. Referring to FIG. 6, Figure 3 In an implementation, the FPGA corresponds to 24 computing units, wherein the first data interface module 110 corresponding to the first computing unit is respectively an IIC slave 01, an out-of-band UART 01, and a first USB physical layer 01; ……; the first data interface module 110 corresponding to the 24th computing unit is respectively an IIC slave 24, an out-of-band UART 24, and a first USB physical layer 24. The second data interface module 120 corresponding to the management controller is respectively a first SPI slave 01, a second SPI slave 01, and a second USB physical layer 01. The FPGA further includes an out-of-band USB host 01 and an out-of-band USB device 01.

[0061] Exemplarily, the 24 IIC slaves (including IIC slave 01 to IIC slave 24) corresponding to the first computing unit to the 24th computing unit cache the system information or basic information of the 24 computing units received in the cache module 130, so as to be taken by the first SPI slave in a polling or interrupt manner, and then transmitted to the management controller. The 24 out-of-band UARTs (including out-of-band UART 01 to out-of-band UART 24) corresponding to the first computing unit to the 24th computing unit cache the printing and log information of the 24 computing units received in the cache module 130, so as to be taken by the second SPI slave in a polling or interrupt manner, and then transmitted to the management controller.

[0062] The management controller transmits data to the out-of-band USB device 01 through the second USB physical layer 01, and caches the data in the cache module 130. The out-of-band USB host takes the data in the cache module 130, and can be switched to different first USB physical layers (including first USB physical layer 01 to first USB physical layer 24) to sequentially send firmware update information to the first computing unit to the 24th computing unit.

[0063] The embodiment of the present disclosure realizes out-of-band bridging through FPGA. In a first aspect, the data transmission of multiple IIC, multiple UART and multiple USB can be realized in a single FPGA, without using the scheme of stacking interface chips, thereby reducing the number and cost of out-of-band devices. In a second aspect, the FPGA has sufficient cache, and the single FPGA shortens the length of the link, which is conducive to realizing the functions of IIC, UART, USB and the like at the same time. In a third aspect, by using the FPGA with a USB host and a USB physical layer, the USB host can be connected to multiple first USB physical layers in turn through the internal switching function of the FPGA, thereby greatly saving the logic resources of the FPGA.

[0064] On the basis of the above-mentioned embodiments, optionally, the cache module 130 is further configured to transparently transmit the data of each first data interface module 110 and the data of the second data interface module 120. The transparent transmission refers to a process of transmitting data without analysis and processing by an intermediate device, so as to maintain the originality of the data and facilitate the rapid transmission of the data. The embodiment of the present disclosure realizes out-of-band bridging through FPGA, and can realize the data transmission of multiple computing units in one FPGA, thereby facilitating the realization of data transparent transmission. Therefore, the embodiment of the present disclosure further improves the data transmission quality of out-of-band bridging.

[0065] The embodiment of the present disclosure also provides an out-of-band bridging system including at least two FPGAs provided by any embodiment of the present disclosure, and has the corresponding beneficial effects.

[0066] Specifically, in some embodiments, the number of computing units in the array server (especially suitable for SoC array server and other array servers with the same architecture as SoC array server) is large, and one FPGA is insufficient to meet the out-of-band bridging requirement, and more number of FPGAs can meet the out-of-band bridging requirement.

[0067] The embodiments of the present disclosure also provide an array server, which can be an SoC array server or other array servers with the same architecture as the SoC array server. Figure 4 A structural schematic diagram of an array server provided by the embodiments of the present disclosure is shown in FIG. 1. Figure 4 The array server includes a management controller 300, an FPGA 100 provided by any of the embodiments of the present disclosure, and at least two computing units 200; wherein the FPGA 100 is used for bridging the management controller 300 and the at least two computing units 200. Since the array server includes the FPGA 100 provided by any of the embodiments of the present disclosure, the technical principles and effects are similar.

[0068] Optionally, the management controller 300 can be a baseboard management controller (BMC).

[0069] In some embodiments, optionally, the array server further includes a switch, wherein the switch and the computing units 200 constitute an in-band part of the array server, the FPGA 100 is an out-of-band bridging part, and the management controller 300 is an out-of-band management part.

[0070] Figure 5 A structural schematic diagram of another array server provided by the embodiments of the present disclosure is shown in FIG. 2. Figure 5 In some embodiments, optionally, the at least two computing units 200 constitute an array of n rows and m columns; the number of FPGAs 100 is at least two, one FPGA 100 is connected with one row or one column of computing units 200, and each FPGA 100 is connected with the management controller 300. For example, one FPGA 100 is connected with one row of computing units 200, and n FPGAs are arranged in the array server; wherein the number m of columns of one row of computing units 200 can be set as needed, such as Figure 5 As shown in FIG. 3, the number m of columns of one row of computing units 200 is 24, that is, one FPGA corresponds to 24 computing units 200.

[0071] In some embodiments, optionally, the first data interface module in each FPGA is divided into at least two groups of data interfaces, and one computing unit 200 corresponds to one group of data interfaces. For example,Figure 5 As shown, taking the FPGA 01 as an example, each first data interface module is IIC slave 01, out-of-band UART 01, first USB physical layer 01, …, IIC slave 24, out-of-band UART 24, and first USB physical layer 24, IIC slave 01, out-of-band UART 01, and first USB physical layer 01 constitute a first data interface group, and the data interface group corresponds to the calculation unit 200 located in the first row and the first column; …; IIC slave 24, out-of-band UART 24, and first USB physical layer 24 constitute a 24th data interface group, and the data interface group corresponds to the calculation unit 200 located in the first row and the 24th column. Similarly, taking the FPGA n as an example, each first data interface module is IIC slave n, out-of-band UART n, first USB physical layer n, …, IIC slave n+24, out-of-band UART n+24, and first USB physical layer n+24, IIC slave n, out-of-band UART n, and first USB physical layer n constitute a first data interface group, and the data interface group corresponds to the calculation unit 200 located in the n-th row and the first column; …; IIC slave n+24, out-of-band UART n+24, and first USB physical layer n+24 constitute a 24th data interface group, and the data interface group corresponds to the calculation unit 200 located in the n-th row and the 24th column. The embodiments of the present disclosure group the first data interface modules to match the calculation units, so that the logic in the FPGA is clear, which is beneficial to simplify the program design difficulty.

[0072] In an embodiment, optionally, the calculation unit 200 includes a SoC calculation unit. The SoC calculation unit can be used in combination or separately according to application requirements, and the use is flexible.

[0073] In an embodiment of the present disclosure, optionally, the types of the in-band data interface modules of one calculation unit 200 are at least two, and the types of the first data interface modules are at least two; the number of the second data interface modules is the same as the number of the types of the first data interface modules; one second data interface module corresponds to one type of first data interface module. The embodiments of the present disclosure correspond one second data interface module to one type of first data interface module, which is beneficial to pack and cache data of the same type, thereby simplifying the design difficulty of the FPGA.

[0074] In an embodiment of the present disclosure, optionally, the in-band data interface modules of the calculation unit 200 include at least one of an IIC master, an in-band UART, and an in-band USB device; and / or the management data interface modules of the management controller 300 include a first management SPI master, a second management SPI master, and at least two management USB masters.

[0075] In an embodiment of the present disclosure, optionally, the first data interface module 110 of the FPGA 100 comprises an IIC slave, the IIC slave is connected to an IIC master in one-to-one correspondence; and / or, the first data interface module 110 of the FPGA 100 comprises an out-of-band UART, the out-of-band UART is connected to an in-band UART in one-to-one correspondence; and / or, the first data interface module 110 of the FPGA 100 comprises a first USB physical layer, the FPGA 100 further comprises an out-of-band USB host, the first USB physical layer is connected to an in-band USB device in one-to-one correspondence; each first USB physical layer is connected to the out-of-band USB host, and the out-of-band USB host is configured to switch data transmission to different first USB physical layers.

[0076] In an embodiment of the present disclosure, optionally, the second data interface module 120 of the FPGA 100 comprises a first SPI slave, each first SPI slave of the FPGA 100 is connected to a first management SPI host; and / or, the second data interface module 120 of the FPGA 100 comprises a second SPI slave, each second SPI slave of the FPGA 100 is connected to a second management SPI host; and / or, the second data interface module 120 of the FPGA 100 comprises a second USB physical layer, the FPGA 100 further comprises an out-of-band USB device, the second USB physical layer is connected to a management USB host in one-to-one correspondence, and the second USB physical layer is a transmission medium between the out-of-band USB device and the management USB host.

[0077] In an embodiment of the present disclosure, optionally, the first data interface module 110 of the FPGA 100 comprises an IIC slave, an out-of-band UART and a first USB physical layer; the second data interface module 120 of the FPGA 100 comprises a first SPI slave, a second SPI slave and a second USB physical layer; the FPGA 100 further comprises an out-of-band USB host and an out-of-band USB device; inside each FPGA 100, each IIC slave is connected to the first SPI slave through a cache module 130; each out-of-band UART is connected to the second SPI slave through the cache module 130; each first USB physical layer is connected to the out-of-band USB host, the out-of-band USB host is connected to the out-of-band USB device through the cache module 130, and the out-of-band USB device is connected to the second USB physical layer.

[0078] As Figure 5As shown, the exemplary computing units 200 include three types of IIC, UART and USB, and the management controller 300 includes two types of SPI and USB. Specifically, the computing unit SoC01 includes an in-band IIC host 01, an in-band UART 01 and an in-band USB device 01, …, the computing unit SoC 24 includes an in-band IIC host 24, an in-band UART 24 and an in-band USB device 24, …, the computing unit SoC n includes an in-band IIC host n, an in-band UART n and an in-band USB device n, …, the computing unit SoC n+24 includes an in-band IIC host n+24, an in-band UART n+24 and an in-band USB device n+24. The management controller 300 includes a first SPI host, a second SPI host, a management USB host 01, …, a management USB host n.

[0079] Correspondingly, the first data interface module in the FPGA 01 is the IIC slave 01, the out-of-band UART 01 and the first USB physical layer 01 respectively; …; the first data interface module corresponding to the 24th computing unit is the IIC slave 24, the out-of-band UART 24 and the first USB physical layer 24 respectively; the second data interface module is the first SPI slave 01, the second SPI slave 01 and the second USB physical layer 01 respectively. The FPGA 01 further includes an out-of-band USB host 01 and an out-of-band USB device 01. The FPGA 01 corresponds to the 24 SoCs in the first row.

[0080] By analogy, the first data interface module in the FPGA n is the IIC slave n, the out-of-band UART n and the first USB physical layer n respectively; …; the first data interface module corresponding to the 24th computing unit is the IIC slave n+24, the out-of-band UART n+24 and the first USB physical layer n+24 respectively; the second data interface module is the first SPI slave n, the second SPI slave n and the second USB physical layer n respectively. The FPGA n further includes an out-of-band USB host n and an out-of-band USB device n. The FPGA n corresponds to the 24 SoCs in the nth row.

[0081] The first SPI slave 01 in the FPGA 01, …, the first SPI slave n in the FPGA n are all connected to the first SPI host in the management controller 300; the second SPI slave 01 in the FPGA 01, …, the second SPI slave n in the FPGA n are all connected to the second SPI host in the management controller 300.

[0082] The second USB physical layer 01 in the FPGA 01 is connected to the management USB host 01 in the management controller 300, …, the second USB physical layer n in the FPGA n is connected to the management USB host n in the management controller 300.

[0083] Exemplarily, the 24 IIC slaves (including IIC slave 01 to IIC slave 24) corresponding to the 24 computing units of the first row buffer the received system information or basic information of the 24 computing units of the first row into the buffer module 01, …, the 24 IIC slaves (including IIC slave n to IIC slave n+24) corresponding to the 24 computing units of the nth row buffer the received system information or basic information of the 24 computing units of the first row into the buffer module n; the first SPI master in the management controller 300 controls the first SPI slave 01 to the first SPI slave n to obtain the data in a polling or interrupt manner, and then transmits the data to the management controller 300.

[0084] The 24 out-of-band UARTs (including out-of-band UART 01 to out-of-band UART 24) corresponding to the 24 computing units of the first row buffer the received printing and log information of the 24 computing units of the first row into the buffer module 01, …, the 24 out-of-band UARTs (including out-of-band UART n to out-of-band UART n+24) corresponding to the 24 computing units of the nth row buffer the received printing and log information of the 24 computing units of the first row into the buffer module n; the second SPI master in the management controller 300 controls the second SPI slave 01 to the second SPI slave n to obtain the data in a polling or interrupt manner, and then transmits the data to the management controller 300.

[0085] The management controller 300 transmits data to the FPGA 01 through the management USB host 01, in the FPGA 01, the second USB physical layer 01 transmits the data to the out-of-band USB device 01 and buffers the data to the buffer module 01, the out-of-band USB host 01 obtains the data in the buffer module 01 and can be switched to different first USB physical layers (including first USB physical layer 01 to first USB physical layer 24) to sequentially send firmware update information to the 24 computing units 200 of the first row; …; the management controller 300 transmits data to the FPGA n through the management USB host n, in the FPGA n, the second USB physical layer n transmits the data to the out-of-band USB device n and buffers the data to the buffer module n, the out-of-band USB host n obtains the data in the buffer module n and can be switched to different first USB physical layers (including first USB physical layer n to first USB physical layer n+24) to sequentially send firmware update information to the 24 computing units 200 of the nth row.

[0086] The out-of-band bridging is implemented by the FPGA, in the first aspect, the data transmission of the multi-channel IIC, the multi-channel UART and the multi-channel USB can be implemented in the single-chip FPGA, without adopting the scheme of stacking interface chips, so that the number and cost of out-of-band devices are reduced, in the second aspect, the FPGA has sufficient cache, and the single-chip FPGA shortens the length of the link, which is beneficial to simultaneously implementing the functions of IIC, UART, USB and the like, and in the third aspect, the FPGA with the USB host and the USB physical layer is adopted, so that the USB physical layer chip does not need to be externally hung, and through the internal switching function of the FPGA, the USB host can be used to alternately control multiple first USB physical layers, so that the logic resources of the FPGA are greatly saved.

[0087] In the above embodiments, the array server can be a cloud server, also known as a cloud computing server or a cloud host, which is a host product in a cloud computing service system, and solves the defects of great management difficulty and weak business scalability in traditional physical hosts and VPS services. The server can also be a server of a distributed system, or a server combined with a blockchain.

[0088] The embodiment of the present disclosure also provides a method for implementing out-of-band bridging in an FPGA, which can be executed by the FPGA provided by any embodiment of the present disclosure and achieves the corresponding beneficial effects. Specifically, Figure 6 is a flowchart of a method for implementing out-of-band bridging in an FPGA according to an embodiment of the present disclosure. Referring to Figure 6 , the method specifically includes the following:

[0089] S110, data transmission is performed between the first data interface module and the in-band data interface module; wherein the number of the first data interface modules is at least two;

[0090] S120, data transmission is performed between the second data interface module and the management data interface module;

[0091] S130, the data of each first data interface module and the data of the second data interface module are cached by the cache module; wherein each second data interface module performs data transmission with at least two first data interface modules through the cache module.

[0092] In the FPGA, the embodiment of the present disclosure sets the first data interface module 110 to perform data transmission with the in-band data interface module, sets the second data interface module 120 to perform data transmission with the management data interface module, and sets the cache module 130 to cache the data of the first data interface module 110 and the second data interface module 120, so that at least two first data interface modules 110 can send data to the second data interface module 120 after being cached by the cache module 130, and the out-of-band bridging function can be implemented by the FPGA.

[0093] The embodiments of the present disclosure can realize bidirectional transmission of data, for example, can realize transmission of data from the computing unit to the management controller, can realize transmission of data from the management controller to the computing unit, and can also realize bidirectional transmission of data between the computing unit and the management controller. In actual application, the transmission direction can be set as required.

[0094] Figure 7 is a flowchart of another method for implementing out-of-band bridging in an FPGA according to an embodiment of the present disclosure. Referring to Figure 7 In an embodiment, optionally, the data transmission direction is: transmitting data from the in-band data interface module to the management data interface module; the method comprises:

[0095] S210, receiving data sent by at least two in-band data interface modules through at least two first data interface modules of the same type;

[0096] S220, buffering data of each first data interface module through the buffer module, and sequentially sending to the corresponding second data interface module;

[0097] Optionally, buffering data of each first data interface module through the buffer module comprises: simultaneously or time-divisionally receiving data of each first data interface module through the buffer module, and buffering the received data. In this way, concurrent buffering of data can be realized.

[0098] S230, sending the received data to the management data interface module through the second data interface module.

[0099] The method can be applied to the case of obtaining system information, basic information, printing and log information, etc. of the computing unit. For example, the method can be applied to transmission of IIC data and UART data.

[0100] Figure 8 is a flowchart of another method for implementing out-of-band bridging in an FPGA according to an embodiment of the present disclosure. Referring to Figure 8 In an embodiment, optionally, the data transmission direction is: transmitting data from the in-band data interface module to the management data interface module; the method comprises:

[0101] S310, receiving data sent by the management data interface module through the second data interface module;

[0102] S320, buffering data of the second data interface module through the buffer module, and sending to at least two first data interface modules of the same type;

[0103] S330, transmitting the received data to each in-band data interface module through each first data interface module.

[0104] The method can be applied to firmware update of a computing unit, etc. For example, it can be applied to transmission of USB data.

[0105] In the technical solution of the embodiments of the present disclosure, the receiving, transmission, sending and caching of data involved all comply with the relevant laws and regulations and do not violate public order and good customs.

[0106] It should be understood that the various forms of flow shown above can be used to reorder, add or delete steps. For example, each step described in the present disclosure can be executed in parallel, sequentially or in a different order, as long as the desired results of the technical solution provided by the present disclosure can be achieved, which is not limited herein.

[0107] The above specific embodiments do not constitute a limitation on the protection scope of the present disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A field programmable gate array structure for implementing out-of-band bridging, comprising: at least two first data interface modules, each of the first data interface modules matching a respective in-band data interface module; wherein the in-band data interface module is a data interface of an in-band portion of a server, the server comprising at least a SoC array server, the in-band portion comprising at least a SoC compute unit; at least two second data interface modules, each of the second data interface modules matching a respective management data interface module; wherein the management data interface module is a data interface of a management controller; a cache module for caching data of each of the first data interface modules and data of each of the second data interface modules; wherein each of the second data interface modules is in data transmission with at least two of the first data interface modules via the cache module.

2. The field programmable gate array architecture implementing out-of-band bridging as recited in claim 1, wherein, each of the first data interface modules is divided into at least two groups of data interface groups; each of the groups of data interface groups comprises at least two different types of the first data interface modules, each of the groups of data interface groups matching the in-band data interface module of a respective compute unit of the array server.

3. The field programmable gate array architecture implementing out-of-band bridging of any of claims 1-2, wherein, a number of the second data interface modules is the same as a number of types of the first data interface modules; one of the second data interface modules corresponds to one type of the first data interface modules.

4. The field programmable gate array architecture implementing out-of-band bridging as claimed in any of claims 1-2, wherein, the types of the first data interface modules comprise at least one of: an inter-integrated circuit bus slave for matching an in-band inter-integrated circuit bus master; an out-of-band universal asynchronous receiver transmitter for matching an in-band universal asynchronous receiver transmitter.

5. The field programmable gate array architecture implementing out-of-band bridging of claim 4, wherein, the types of the second data interface modules comprise a serial peripheral interface slave for matching a management serial peripheral interface master; one of the serial peripheral interface slaves is in data transmission with each of the inter-integrated circuit bus slaves; and / or, one of the serial peripheral interface slaves is in data transmission with each of the out-of-band universal asynchronous receiver transmitters.

6. The field programmable gate array architecture implementing out-of-band bridging as claimed in any of claims 1-2, wherein, the types of the first data interface modules comprise a first universal serial bus physical layer for matching an in-band universal serial bus device; the field programmable gate array structure further comprises an out-of-band universal serial bus master for managing data of at least two of the first universal serial bus physical layers.

7. The field programmable gate array architecture implementing out-of-band bridging of claim 6, wherein, the types of the second data interface modules comprise a second universal serial bus physical layer for matching a management universal serial bus master; the field programmable gate array structure further comprises an out-of-band universal serial bus device, the out-of-band universal serial bus device and the second universal serial bus physical layer being a transmission medium between the out-of-band universal serial bus master and the management universal serial bus master.

8. The field programmable gate array architecture implementing out-of-band bridging as claimed in any of claims 1-2, wherein, the types of the second data interface modules comprise at least one of: a serial peripheral interface slave for matching a management serial peripheral interface master; a second USB PHY for matching the management USB host; the FPGA structure further comprises an out-of-band USB device, and the second USB PHY is a transmission medium between the out-of-band USB device and the management USB host.

9. The field programmable gate array architecture implementing out-of-band bridging as claimed in any of claims 1-2, wherein, The cache module is further configured to transparently transmit data of each first data interface module and data of the second data interface module.

10. An out-of-band bridging system, comprising: At least two FPGA structures according to any one of claims 1-9.

11. An array server comprising: a management controller, an FPGA structure according to any one of claims 1-9, and at least two computing units; The FPGA structure is configured to bridge the management controller and the at least two computing units.

12. The array server of claim 11, wherein, The at least two computing units form an n-row-m-column array. The number of FPGA structures is at least two, one FPGA structure is connected to one row or one column of the computing units, and each FPGA structure is connected to the management controller.

13. The array server of claim 12, wherein, Each first data interface module is divided into at least two groups of data interfaces, and one computing unit corresponds to one group of data interfaces.

14. The array server of any of claims 11-13, wherein, The types of the in-band data interface modules of one computing unit are at least two, and the types of the first data interface modules are at least two. The number of second data interface modules is the same as the number of types of first data interface modules, and one second data interface module corresponds to one type of first data interface module.

15. The array server of any of claims 11-13, wherein, The in-band data interface modules of the computing units include at least one of an IC bus master, an in-band UART, and an in-band USB device. And / or, the management data interface modules of the management controller include a first management SPI master, a second management SPI master, and at least two management USB hosts.

16. The array server of claim 15, wherein, The first data interface modules of the FPGA structure include IC bus slaves that are connected to the IC bus masters one-to-one; And / or, the first data interface modules of the FPGA structure include out-of-band UARTs that are connected to the in-band UARTs one-to-one; And / or, the first data interface modules of the FPGA structure include first USB PHYs, the FPGA structure further comprises an out-of-band USB master, and the first USB PHYs are connected to the in-band USB devices one-to-one; Each first USB PHY is connected to the out-of-band USB master, and the out-of-band USB master is configured to switch data transmission to different first USB PHYs.

17. The array server of claim 15, wherein, The second data interface module of the field programmable gate array structure includes a first serial peripheral interface slave, and each first serial peripheral interface slave of the field programmable gate array structure is connected to the first management serial peripheral interface master; And / or, the second data interface module of the field programmable gate array structure includes a second serial peripheral interface slave, and each second serial peripheral interface slave of the field programmable gate array structure is connected to the second management serial peripheral interface master; And / or, the second data interface module of the field programmable gate array structure includes a second universal serial bus physical layer, and the field programmable gate array structure further includes an out-of-band universal serial bus device, the second universal serial bus physical layer is connected to the management universal serial bus master one by one, and the second universal serial bus physical layer is a transmission medium between the out-of-band universal serial bus device and the management universal serial bus master.

18. The array server of claim 15, wherein, The first data interface module of the field programmable gate array structure includes an inter-integrated circuit bus slave, an out-of-band universal asynchronous receiver transmitter, and a first universal serial bus physical layer; The second data interface module of the field programmable gate array structure includes a first serial peripheral interface slave, a second serial peripheral interface slave, and a second universal serial bus physical layer; The field programmable gate array structure further includes an out-of-band universal serial bus master and an out-of-band universal serial bus device; In each field programmable gate array structure, each inter-integrated circuit bus slave is connected to the first serial peripheral interface slave through the cache module; Each out-of-band universal asynchronous receiver transmitter is connected to the second serial peripheral interface slave through the cache module; Each first universal serial bus physical layer is connected to the out-of-band universal serial bus master, the out-of-band universal serial bus master is connected to the out-of-band universal serial bus device through the cache module, and the out-of-band universal serial bus device is connected to the second universal serial bus physical layer.

19. A method for implementing out-of-band bridging in a field programmable gate array structure, comprising: transmitting data through a first data interface module and an in-band data interface module; wherein the number of the first data interface module is at least two; wherein the in-band data interface module is a data interface of an in-band part of a server, and the server at least includes an SoC array server, and the in-band part at least includes an SoC computing unit; transmitting data through a second data interface module and a management data interface module; wherein the management data interface module is a data interface of a management controller; caching data of each first data interface module and data of each second data interface module through a cache module; wherein each second data interface module transmits data with at least two first data interface modules through the cache module.

20. The method of implementing out-of-band bridging in a field programmable gate array structure of claim 19, wherein, The data transmission direction is from the in-band data interface module to the management data interface module; the method comprises: Receiving data sent by at least two of the in-band data interface modules through at least two of the first data interface modules of the same type; Caching data of each of the first data interface modules by the cache module and sending the data to the corresponding second data interface module in sequence; Sending the received data to the management data interface module by the second data interface module.

21. The method of implementing out-of-band bridging in a field programmable gate array structure of claim 20, wherein, The caching of data of each of the first data interface modules by the cache module comprises: Receiving data of each of the first data interface modules by the cache module simultaneously and caching the received data.

22. The method of implementing out-of-band bridging in a field programmable gate array structure of claim 21, wherein, The method is suitable for transmission of bus data between integrated circuits and universal asynchronous receiver-transmitter data.

23. The method of implementing out-of-band bridging in a field programmable gate array structure according to any of claims 19-22, wherein, The data transmission direction is from the management data interface module to the in-band data interface module. Receiving data sent by the management data interface module through the second data interface module; Caching data of the second data interface module by the cache module and sending the data to at least two of the first data interface modules of the same type; Sending the received data to each of the in-band data interface modules by each of the first data interface modules.

24. The method of implementing out-of-band bridging in a field programmable gate array structure of claim 23, wherein, The method is suitable for transmission of universal serial bus data.

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