A broadband low-loss radio frequency delay circuit, radio frequency chip and electronic device

Abstract

The present invention proposes a broadband low-loss radio frequency delay circuit, a radio frequency chip and an electronic device, which belong to the field of RFIC digital delay devices. The broadband low-loss radio frequency delay circuit includes a high-delay part and a low-delay part, wherein the high-delay part includes a switch circuit, and a constant resistance delay unit and a reference state amplitude equalization circuit connected to the switch circuit, and the low-delay part includes two embedded switches, two series inductors and a parallel capacitor. The present invention realizes the switching of radio frequency signals between the reference state circuit and the delay state circuit through switches to realize different signal delays, and realizes the small area and low insertion loss of the low-delay position through the switch embedded structure.

Description

Technical Field

[0001] The invention relates to the field of RFIC digitally controlled delay devices, and in particular to a broadband low-loss radio frequency delay device circuit, a radio frequency chip and an electronic device. Background Art

[0002] In modern radar systems, active phased array technology is widely used, and phase shifters and delay devices are used to achieve phase control of radiating units. In systems with a large number of antennas or broadband radars, the use of delay devices is more advantageous due to the existence of beam tilt effects. The principle of a delay device is similar to that of a phase shifter, both of which achieve signal delay by controlling the switching between two channels with different delays. The most important indicator of a delay device is the group delay characteristic, which is defined as , that is, the rate of change of phase with frequency. Unlike the constant phase difference within the operating frequency band of the phase shifter, the delay device has a constant group delay value throughout the entire operating frequency band.

[0003] The main indicators of the delay device include working bandwidth, delay amount, insertion loss and return loss. In order to achieve high-resolution delay characteristics, multiple delay circuits with different delay amounts are usually cascaded. The cascaded delay units of the low-delay circuit are relatively few, while the high-delay circuit requires the cascade of several or even dozens of delay units. On the one hand, the size of the circuit is large, and on the other hand, the insertion loss of the delay state is large, which is 2~3dB lower than the reference state insertion loss, making the overall insertion loss of the delay device fluctuate greatly and introducing additional amplitude modulation. At the same time, since multiple delay networks are connected in series, the parasitic resistances of each delay network are added together, resulting in a large input resistance in the delay state, which worsens the return loss of the input and output ports.

[0004] Each bit of the delay device usually contains two channels, namely the reference state and the delayed state. There is a time difference when the signal passes through the two channels of the reference state and the delayed state. Each channel contains a switch for switching and improving isolation. The existence of the switch introduces additional loss. If each delay bit adopts this structure, the overall loss of the delay device will be large. Summary of the invention

[0005] In view of the problems existing in the delay device design process mentioned above, the present invention proposes a broadband low-loss RF delay device circuit, RF chip and electronic device, which fully utilizes the multi-layer metal process of RF integrated circuits and adopts an improved switch embedded structure for the low-delay position, effectively reducing the overall insertion loss of the delay device while reducing the size of the low-delay position.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] In a first aspect, the present invention provides a broadband low-loss radio frequency delay circuit, comprising: a high-delay part and a low-delay part;

[0008] The high delay part includes: a switch circuit, and a constant resistance delay unit and a reference state amplitude equalization circuit connected to the switch circuit;

[0009] The switch circuit includes four series switches and four parallel switches, and the series switches and the parallel switches work together to realize the switching of the delay device between the reference state and the delay state at the high delay position;

[0010] The reference state amplitude equalization circuit is used to achieve the balance of insertion loss between the reference state and the delay state in the constant resistance delay unit;

[0011] The low-delay part includes two embedded switches, two series inductors and a parallel capacitor, and the delay device is placed in a reference state or a delay state based on the switching of the two embedded switches.

[0012] Further, the four series switches include S1, S2, S3 and S4, and the four parallel switches include S5, S6, S7 and S8;

[0013] The RF signal enters S1 and S3 simultaneously after being input from the input port;

[0014] The RF signal outputs two signals after passing through S1, one of which is grounded after passing through switch S5, and the other is grounded after passing through the reference state circuit in the constant resistance delay unit, and then outputs one signal through switch S6 and grounded, and outputs the other signal through switch S2 as the first output signal;

[0015] The RF signal outputs two signals after passing through S3, one of which passes through switch S7 and is grounded, and the other passes through the delay state circuit in the constant resistance delay unit, outputs one signal through switch S8 and is grounded, and outputs the other signal through switch S4 as the second output signal;

[0016] The first signal and the second signal serve as a common output signal of the RF output port.

[0017] Furthermore, the constant resistance delay unit includes a delay state circuit and a reference state circuit, wherein

[0018] The delay state circuit includes two cascaded coupled inductors L2 and L3, and a capacitor C1 whose common end is connected in parallel to the ground;

[0019] The reference state circuit includes two series inductors L1.

[0020] Furthermore, the reference state amplitude equalization circuit is composed of a pi-type fixed attenuation network, including resistors R1, R2 and R3, wherein one end of R1 and R3 is connected to the two ends of R2 respectively, and the other ends of R1 and R3 are grounded respectively.

[0021] Furthermore, the process of realizing the delay device in the reference state or the delay state based on the switching of the two embedded switches is specifically that when the first embedded switch is closed and the second embedded switch is opened, the delay device is in the reference state; when the first embedded switch is opened and the second embedded switch is closed, the delay device is in the delay state.

[0022] Furthermore, the switch circuit includes four series switches and four parallel switches, and the switching of the delay device between the reference state and the delay state at the high delay position is realized by the joint action of the series switches and the parallel switches, including:

[0023] When switches S1, S2, S7, and S8 are in a closed state and switches S3, S4, S5, and S6 are in an open state, the timer is in a reference state; when switches S1, S2, S7, and S8 are in an open state and switches S3, S4, S5, and S6 are in a closed state, the timer is in a delay state.

[0024] Furthermore, the coupled inductors L2 and L3 are octagonal coupled inductors.

[0025] Furthermore, the coupled inductors L2 and L3 are formed by metal wiring.

[0026] In a second aspect, the present invention further proposes a radio frequency chip, which includes the broadband low-loss radio frequency delay circuit as described in the first aspect.

[0027] In a third aspect, the present invention further proposes an electronic device, comprising the broadband low-loss radio frequency delay circuit as described in the first aspect or the radio frequency chip as described in the second aspect.

[0028] The beneficial effects of the present invention are:

[0029] (1) The optimized delay unit structure is adopted to reduce the insertion loss of the low-delay bit while reducing the area of ​​the low-delay bit.

[0030] (2) By introducing the reference state attenuation network, the insertion loss amplitude of the high delay position is balanced. At the same time, by connecting the upper and lower metal layers, the insertion loss of the delay state is reduced and the return loss is improved. The structure of the delay unit is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present invention and do not constitute a limitation on the technical solution of the present invention.

[0032] Figure 1 This is the overall framework diagram of the broadband low-loss radio frequency delay circuit proposed by the present invention;

[0033] Figure 2 This is a schematic diagram of the high delay circuit in the broadband low-loss radio frequency delay circuit proposed by the present invention;

[0034] Figure 3 A schematic diagram of a low delay circuit in a broadband low-loss radio frequency delay circuit proposed by the present invention;

[0035] Figure 4 The layout of the constant resistance delay unit in the broadband low loss radio frequency delay circuit proposed by the present invention;

[0036] Figure 5 It is an equivalent circuit diagram of a switch embedded delay circuit of a low-delay part reference state in a broadband low-loss radio frequency delay circuit proposed by the present invention;

[0037] Figure 6 This is an equivalent circuit diagram of a switch embedded delay circuit in a low-delay part delay state in a broadband low-loss radio frequency delay circuit proposed by the present invention. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0039] like Figure 1 As shown, this embodiment provides a broadband low-loss radio frequency delay circuit, which includes a high-delay bit part and a low-delay bit part.

[0040] like Figure 2 As shown, the high-delay part includes: a switching circuit, and a constant-resistance delay unit and a reference state amplitude balancing circuit connected to the switching circuit; the switching circuit includes four series switches and four parallel switches, and the switching of the high-delay position delay device between the reference state and the delay state is realized through the joint action of the series switches and the parallel switches; the reference state amplitude balancing circuit is used to achieve the balance of insertion loss between the reference state and the delay state in the constant-resistance delay unit.

[0041] In this embodiment, the switching circuit includes four series switches S1, S2, S3 and S4 for switching, and four parallel switches S5, S6, S7 and S8. The four parallel switches S5, S6, S7 and S8 increase the isolation between the channels where the switches S1, S2, S3 and S4 are located.

[0042] The RF signal outputs two signals after passing through S1, one of which is grounded after passing through switch S5, and the other is grounded after passing through the reference state circuit in the constant resistance delay unit, and then outputs one signal through switch S6 and grounded, and outputs the other signal through switch S2 as the first output signal;

[0043] The RF signal outputs two signals after passing through S3, one of which passes through switch S7 and is grounded, and the other passes through the delay state circuit in the constant resistance delay unit, outputs one signal through switch S8 and is grounded, and outputs the other signal through switch S4 as the second output signal;

[0044] The first signal output by the switch S2 and the second signal output by the switch S4 serve as a common output signal of the RF output port.

[0045] In this embodiment, the constant resistance delay unit includes a delay state circuit and a reference state circuit, and is used to achieve broadband constant signal delay. Specifically, the delay state circuit includes two cascaded coupled inductors L2 and L3, and a capacitor C1 connected in parallel to the ground at the common end, and the reference state circuit includes two series inductors L1. Both the delay state and the reference state include the above-mentioned switching circuit to achieve the switching of the signal between the reference state and the delay state, and to ensure the isolation requirements between the channels. The high delay position is achieved by cascading multiple constant resistance delay networks.

[0046] It should be noted that since the high-delay delay state circuit requires the cascade of a large number of delay units, the insertion loss of the delay state is large, and the difference with the reference state is large. A pi-type fixed attenuation network of the reference state is introduced to achieve amplitude balance between the two channels. By interconnecting the upper and lower metal layers, the parasitic resistance of the constant-resistance delay unit is reduced, and the insertion loss of the delay state circuit is reduced. When multiple delay units are cascaded, the input return loss characteristics are improved. At the same time, this embodiment uses a constant-resistance delay unit in the form of an octagonal coupled inductor, which can improve the Q value and reduce the loss of the delay state circuit on the one hand; on the other hand, compared with the two unequal inductance values ​​caused by the asymmetric structure of the quadrilateral, the symmetrical structure of the octagon can achieve equal values ​​of the two coupled inductors.

[0047] In this embodiment, the reference state amplitude equalization circuit is mainly used to reduce the difference in insertion loss between the reference state and the delayed state of high delay, and avoid introducing additional amplitude modulation. It is mainly composed of a pi-type fixed attenuation network, including resistors R1, R2 and R3, wherein one end of R1 and R3 is respectively connected to the two ends of R2, and the other ends of R1 and R3 are respectively grounded. On the one hand, the balance of insertion loss between the reference state and the delayed state is achieved, and on the other hand, the tuning freedom can be increased by adjusting the specific resistance value to achieve matching of the input and output ports.

[0048] In this embodiment, the low delay part includes two embedded switches, two series inductors and a parallel capacitor, and the delay device is in a reference state or a delay state based on the switching of the two embedded switches. Figure 3 As shown, the low-delay part can be configured as a small-size, low-loss, low-delay position switch embedded in a full-pass network. Its circuit prototype is a series inductor full-pass network, including embedded switches S9 and S10. By switching the switch state, the small resistance in the on state and the small capacitance in the off state are realized. Inductors L5 and L6 are connected in series, and capacitor C2 is connected in parallel.

[0049] It should be noted that for the low-delay position, the circuit adopts a switch-embedded structure. When switch S9 is closed and S10 is disconnected, the delay device is in the reference state; when switch S9 is disconnected and S10 is closed, the delay device is in the delay state. In the reference state, the circuit is equivalent to a series LC circuit connected in parallel to the ground; in the delay state, the circuit is equivalent to a full-pass network with series inductors. In addition, the use of a switch-embedded low-delay state circuit slightly sacrifices the delay characteristics, reduces the circuit area, reduces the insertion loss, and reduces the number of switches.

[0050] The present invention provides a broadband low-loss radio frequency delay device, the working principle of which is:

[0051] For the high delay position, when switches S1, S2, S7, S8 are in the closed state and switches S3, S4, S5, S6 are in the open state, the delay device is in the reference state; when switches S1, S2, S7, S8 are in the open state and switches S3, S4, S5, S6 are in the closed state, the delay device is in the delay state. The series switch is used to control the switching of the channel, and the parallel switch is used to improve the isolation between the channels. The reference state circuit structure is a section of transmission line or Figure 2 The two inductors L1 shown in the figure and a pi-type fixed attenuation network for balancing the amplitude difference between the two channels, the basic structural unit of the delay state circuit is a constant resistance delay network, including a pair of magnetically coupled inductors L2 and L3, and a capacitor C1 connected to the ground in parallel at the common end. When the signal passes through the reference state and delay state circuits alone, there will be different delays. The delay amount of the constant resistance delay network is reasonably designed to achieve better return loss and insertion loss. More delay amounts require the cascade of multiple delay networks to achieve.

[0052] In this embodiment, if Figure 2 As shown, Figure 2 This is the circuit schematic diagram of a single delay position of the delay device. The switch tubes S1, S2, S3, and S4 control the switching of the channels, and the parallel switch tubes S5, S6, S7, and S8 increase the isolation between the channels. When turned on, the switch is equivalent to a small resistor, which is approximately a short circuit; when turned off, the switch is equivalent to a small capacitor with a high reactance part, which is approximately an open circuit. The upper part is the reference state circuit, which is usually a small inductor or a short section of transmission line. For high-delay circuits, the delay state circuit contains a large number of delay units with large losses. In order to balance the loss difference between channels, a pi-type fixed attenuation network is introduced, which includes two parallel resistors R1 and R3, and a series resistor R2. And the fine-tuning attenuation network can also be used to improve the return loss characteristics of the reference state. The lower part is the delay state circuit, which includes a pair of mutually coupled inductors L2 and L3, and a capacitor C1 connected in parallel to the ground. By adjusting the circuit parameters, a stable group delay characteristic in a wide frequency range can be achieved.

[0053] like Figure 3 As shown in the figure, it is a circuit diagram of the low-delay part, including embedded switch tubes S9 and S10, inductors L5 and L6 connected in series, and capacitor C2 connected in parallel to ground. As part of the circuit, the switch tube is closed and S10 is open in the reference state. The circuit is equivalent to Figure 5 In the delay state, S9 is open and S10 is closed, and the circuit is equivalent to Figure 6 The form shown. The structure in which the switch tube is embedded is relatively small, fewer switch tubes are used, and the circuit loss is lower.

[0054] like Figure 4 As shown, the constant resistance delay unit provided in this embodiment. P1 and P2 are the input and output ports, and the two mutually coupled inductors are in the form of two layers of metal routing to increase the thickness of the cross section. The capacitor in the middle is connected to the ground in parallel. First, for the high-delay position circuit part, since the delay amount is very large, there are usually several to dozens of constant resistance delay networks cascaded to superimpose the delay amount. The parasitic resistance introduced by the series inductance of the constant resistance delay network is also superimposed, resulting in a large input resistance of the delay state circuit, making it difficult to match the broadband input impedance. Secondly, the octagonal coupled inductor form is adopted. On the one hand, the structure is simple. On the other hand, compared with the quadrilateral form, the octagon has a higher Q value and lower loss, and solves the problem of asymmetry of the two inductance values ​​caused by the asymmetric structure of the quadrilateral.

[0055] This embodiment provides a radio frequency chip, which includes the broadband low-loss radio frequency delay circuit of the above embodiment. Through the structure of embedded switch tube, the simplification and reduction of the low-delay position circuit structure are achieved, and the insertion loss is reduced. For the high-delay position circuit, the amplitude balance of the reference state and the delay state, as well as the improvement of the input and output return loss are achieved through the introduction of the attenuation network of the reference state and the optimization of the delay unit structure of the delay state.

[0056] This embodiment also provides an electronic device, having a controller, which is connected to the RF chip through a configuration bus and is used to send a control signal to control a register, so as to reduce the parasitic resistance of the circuit and improve the return loss and insertion loss characteristics, thereby solving the technical problem in the prior art that large parasitic resistance leads to large insertion loss and a large difference in insertion loss with a reference state. This embodiment makes full use of the multi-layer metal process of the RF integrated circuit and adopts an improved switch embedding structure for the low-delay bit, thereby effectively reducing the overall insertion loss of the delay device while reducing the size of the low-delay bit.

[0057] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted for facilitating the understanding of the present invention, and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, and these all belong to the protection scope of the present invention. Therefore, the patent protection scope of the present invention shall still be subject to the scope defined by the attached claims.

Claims

1. A broadband low-loss radio frequency delay circuit, characterized in that: include: High latency part and low latency part; The high delay part includes: a switch circuit, and a constant resistance delay unit and a reference state amplitude equalization circuit connected to the switch circuit; The switch circuit includes four series switches and four parallel switches, and the switching between the reference state and the delay state of the delay device at the high delay position is realized by the joint action of the series switches and the parallel switches; the four series switches include S1, S2, S3 and S4, and the four parallel switches include S5, S6, S7 and S8; The constant resistance delay unit includes a reference state circuit and a delay state circuit, the reference state circuit includes a first series inductor and a second series inductor; the delay state circuit includes two cascaded coupled inductors L2 and L3; The reference state amplitude equalization circuit is used to achieve the balance of insertion loss between the reference state and the delay state in the constant resistance delay unit, and is composed of a pi-type fixed attenuation network, including resistors R1, R2 and R3, wherein one end of R1 and R3 is connected to the two ends of R2 respectively, and the other ends of R1 and R3 are grounded respectively; The first ends of S1 and S3 are connected to the input end of the radio frequency signal, the second end of S1 is connected to the first end of S5 and the first end of the first series inductor, the second end of the first series inductor is connected to the first end of the resistor R1 and the first end of the resistor R2, the second end of the resistor R2 is connected to the first end of the resistor R3 and the first end of the second series inductor, and the second end of the second series inductor is connected to the first end of S6 and the first end of S2; The second end of S3 is connected to the first end of S7 and the first end of the coupling inductor L2, the second end of the coupling inductor L2 is connected to the first end of the coupling inductor L3 and then grounded via the capacitor C1, the second end of the coupling inductor L3 is connected to the first end of S8 and the first end of S4, and the second end of S2 and the second end of S4 are connected to the output end of the RF signal; The second ends of S5, S6, S7 and S8 are all grounded; The RF signal enters S1 and S3 simultaneously after being input from the input port; The RF signal outputs two signals after passing through S1, one of which is grounded after passing through switch S5, and the other is grounded after passing through the reference state circuit in the constant resistance delay unit, and then outputs one signal through switch S6 and grounded, and outputs the other signal through switch S2 as the first output signal; The RF signal outputs two signals after passing through S3, one of which passes through switch S7 and is grounded, and the other passes through the delay state circuit in the constant resistance delay unit, outputs one signal through switch S8 and is grounded, and outputs the other signal through switch S4 as the second output signal; The first signal and the second signal are used as a common output signal of the RF output port; The low delay part includes a switch tube S9, a switch tube S10, a series inductor L5, a series inductor L6 and a parallel capacitor C2. The delay device is in a reference state or a delay state based on the switching of two embedded switches, wherein the first end and the second end of the switch tube S9 are respectively connected to the first end of the series inductor L5 and the first end of the series inductor L6, the second end of the series inductor L5 and the second end of the series inductor L6 are connected to the first end of the switch tube S10, and the second end of the switch tube S10 is connected to the parallel capacitor C2 and then grounded.

2. The broadband low-loss radio frequency delay circuit according to claim 1, characterized in that: The process of realizing the delay device in the reference state or the delay state based on the switching of the two embedded switches is specifically as follows: when the switch tube S9 is closed and the switch tube S10 is opened, the delay device is in the reference state; when the switch tube S9 is opened and the switch tube S10 is closed, the delay device is in the delay state.

3. The broadband low-loss radio frequency delay circuit according to claim 1, characterized in that: The switch circuit includes four series switches and four parallel switches, and the switching of the delay device between the reference state and the delay state at the high delay position is realized by the joint action of the series switches and the parallel switches, including: When switches S1, S2, S7, and S8 are in a closed state and switches S3, S4, S5, and S6 are in an open state, the timer is in a reference state; when switches S1, S2, S7, and S8 are in an open state and switches S3, S4, S5, and S6 are in a closed state, the timer is in a delay state.

4. The broadband low-loss radio frequency delay circuit according to claim 1, characterized in that: The coupled inductors L2 and L3 are octagonal coupled inductors.

5. The broadband low-loss radio frequency delay circuit according to claim 1, characterized in that: The coupled inductors L2 and L3 are formed by metal wiring.

6. A radio frequency chip, characterized in that: The radio frequency chip includes the broadband low-loss radio frequency delay circuit as described in any one of claims 1-5.

7. An electronic device, characterized in that: It comprises the broadband low-loss radio frequency delay circuit as described in any one of claims 1 to 5 or the radio frequency chip as described in claim 6.

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