A method and system for predicting junction temperature of a power semiconductor device

Abstract

The present invention discloses a method and system for predicting the junction temperature of a power semiconductor device. The method comprises: loading the current normal load of the power semiconductor device as the input of a power semiconductor device junction temperature prediction model, and outputting the junction temperature value corresponding to the power semiconductor device under the current working condition. The method and system for predicting the junction temperature of a power semiconductor device disclosed by the present invention can improve the accuracy of the junction temperature prediction result.

Description

Technical Field

[0001] The present invention relates to the technical field of thyristor junction temperature prediction, and in particular to a method and system for predicting the junction temperature of a power semiconductor device. Background Art

[0002] Ultra-high voltage direct current transmission technology is a key means to achieve long-distance, large-capacity power transmission. Thyristors are key core components for realizing AC-DC conversion functions in ultra-high voltage direct current projects, and their reliability is directly related to the safe and stable operation of the entire direct current transmission system. Existing studies have shown that the reliability of power semiconductor devices will decrease by 50% for every 10°C increase in junction temperature. Therefore, accurate modeling of thyristors to accurately predict their junction temperature is of great significance for reliability analysis of thyristor devices.

[0003] In order to meet the high-power demand of DC transmission, existing UHV DC transmission thyristors generally adopt a crimping type packaging form, that is, the layers of materials are stacked together by external mechanical means, so that the device is subjected to a normal load force, thereby forming good electrical and thermal contact between each contact surface.

[0004] The accurate setting of thyristor thermal resistance is a key factor affecting the junction temperature prediction results. The thermal resistance of thyristor consists of two parts: the bulk thermal resistance of each layer of material and the contact thermal resistance between layers. The bulk thermal resistance of thyristor is mainly related to the physical properties of the material itself, and the calculation is relatively simple, but the contact thermal resistance is a quantity related to material properties, surface morphology, and external loads. Existing studies have shown that the contact thermal resistance of press-fit devices accounts for about 50% of the thermal resistance of the entire device. Existing modeling methods often do not consider the contact thermal resistance or directly set the contact thermal resistance to a constant value. This modeling method is too idealistic, and the accuracy of the junction temperature prediction results obtained from it needs to be improved urgently.

[0005] In the prior art, an invention patent with a patent publication number of CN117970062A discloses a method, system and related components for obtaining the junction temperature of a power device, in which the thermal resistance in the thermal network model is set to a fixed value. Summary of the invention

[0006] The technical problem to be solved by the present invention is to solve the problem of low accuracy in the prediction of junction temperature of existing thyristor devices.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0008] A method for predicting junction temperature of a power semiconductor device, comprising:

[0009] The current normal load of the power semiconductor device is loaded as the input of the power semiconductor device junction temperature prediction model, and the junction temperature value corresponding to the power semiconductor device under the current working condition is output; wherein the modeling steps of the power semiconductor device junction temperature prediction model include:

[0010] Obtaining contour roughness curves of various surfaces of power semiconductor devices;

[0011] The roughness curves of the contours of the adjacent surfaces are converted into a smooth surface and a rough surface, and an equivalent fractal dimension parameter and an equivalent fractal scale parameter are obtained;

[0012] According to the equivalent fractal dimension parameter and the equivalent fractal scale parameter, a three-dimensional equivalent fractal contact rough surface is constructed, and the elastic-plastic critical contact area of ​​the three-dimensional equivalent fractal contact rough surface is obtained;

[0013] By using the constructed three-dimensional equivalent fractal contact rough surface and elastic-plastic critical contact area, and changing the equivalent contact spacing of the three-dimensional equivalent fractal contact rough surface, the corresponding real contact area, normal load, and contact thermal resistance value are iteratively calculated to obtain the contact thermal resistances of the power semiconductor device under the target normal load.

[0014] According to the contact thermal resistances of the power semiconductor device under the target normal load, combined with the shell temperature and heat generation power of the current power semiconductor device, and the body thermal resistance of each layer of material of the power semiconductor device, a power semiconductor device junction temperature prediction model is established.

[0015] Advantages: The present invention adopts fractal contact theory to integrate contact thermal resistance into the junction temperature prediction model, and can obtain the junction temperature value of the thyristor under different normal load forces and different heat losses, and the accuracy and flexibility of the junction temperature prediction are higher.

[0016] In one embodiment of the present invention, obtaining the equivalent fractal dimension parameter and the equivalent fractal scale parameter comprises the following steps:

[0017] Obtaining one-dimensional power density of the roughness curve of the profile of two adjacent surfaces of the power semiconductor device;

[0018] Calculate the equivalent power density function of two one-dimensional power densities, and fit the equivalent power density function after taking the logarithm to obtain the equivalent power density linear function;

[0019] According to the equivalent power density linear function, the equivalent fractal dimension parameter and the equivalent fractal scale parameter are obtained.

[0020] In one embodiment of the present invention, the equivalent fractal dimension parameter and the equivalent fractal scale parameter are obtained by the following formula:

[0021] ;

[0022] In the formula, Expressed as the equivalent fractal dimension parameter, Expressed as the equivalent fractal scale parameter, Expressed as the slope of the linear function of equivalent power density, Expressed as the intercept of the linear function of equivalent power density, is a constant, log represents logarithm, and In represents natural logarithm.

[0023] In one embodiment of the present invention, obtaining the elastic-plastic critical contact area includes the following steps:

[0024] Calculate the equivalent Young's modulus and hardness of three-dimensional equivalent fractal contact rough surface;

[0025] The elastic-plastic critical contact area of ​​the contact surface is calculated using the equivalent Young's modulus and hardness.

[0026] In one embodiment of the present invention, the three-dimensional equivalent fractal contact rough surface is obtained by the following formula:

[0027] ;

[0028] In the formula, Represented as a three-dimensional equivalent fractal contact rough surface, Expressed as the equivalent fractal scale parameter, Expressed as the sample length of the rough surface profile, Expressed as a three-dimensional equivalent fractal dimension parameter, is a constant, Expressed as the number of superimposed layers, for A subset of is expressed as the minimum contour frequency, Represented as a random phase, Expressed as pi, It is expressed as spatial position coordinates, cos is expressed as cosine function, and tan is expressed as tangent function.

[0029] In one embodiment of the present invention, the elastic-plastic critical contact area is obtained by the following formula:

[0030] ;

[0031] In the formula, Expressed as the elastic-plastic critical contact area, Expressed as the equivalent Young's modulus, Expressed as hardness.

[0032] In one embodiment of the present invention, determining each contact thermal resistance of a power semiconductor device under a target normal load comprises the following steps:

[0033] S41, calculate the maximum value corresponding to the equivalent contact spacing of the three-dimensional equivalent fractal contact rough surface and the minimum value ;

[0034] S42, set the maximum number of iterations and target normal load ;

[0035] S43, initialize the current label value and equivalent contact spacing ;in, Represents the current iteration value;

[0036] S44, calculate the total cross-sectional area of ​​the three-dimensional equivalent fractal contact rough surface ;

[0037] S45, obtaining the maximum cross-sectional area of ​​the three-dimensional equivalent fractal contact rough surface according to the total cross-sectional area of ​​the three-dimensional equivalent fractal contact rough surface ;

[0038] S46, based on the comparison results of the maximum cross-sectional area and the elastic-plastic critical contact area, the real contact area of ​​the three-dimensional equivalent fractal contact rough surface is obtained ;

[0039] S47, combined with the maximum cross-sectional area, obtains the normal contact load of the three-dimensional equivalent fractal contact rough surface ;

[0040] S48, based on the real contact area and the equivalent thermal conductivity of the joint surface, obtain the equivalent contact thermal resistance of the three-dimensional equivalent fractal contact rough surface ;

[0041] S48, Iteration ; Transfer to the calculation of contact thermal resistance value under equivalent contact spacing of the next iteration; Among them, Represents the number of next iterations;

[0042] S49, determine the normal contact load under the current iteration number Is it consistent with the target normal load? If not, the equivalent contact spacing of the current iteration number is , and proceed to step S44; if so, the contact thermal resistance of each power semiconductor device ;in, Expressed as the equivalent contact spacing of the previous iteration number.

[0043] In one embodiment of the present invention, the equivalent contact thermal resistance , obtained by the following formula:

[0044] ;

[0045] ;

[0046] In the formula, Expressed as the equivalent thermal conductivity of the joint surface, Expressed as the nominal contact area of ​​the bonding surface, , They are respectively expressed as the thermal conductivity of the materials in contact with each other on the bonding surface.

[0047] In one embodiment of the present invention, the power semiconductor device junction temperature prediction model is obtained by the following formula:

[0048] ;

[0049] ;

[0050] In the formula, Expressed as the junction temperature of the power semiconductor device, It is expressed as the case temperature of the current power semiconductor device. It is expressed as the heat generation power of the current power semiconductor device. It is expressed as the bulk thermal resistance of each layer of materials in the power semiconductor device. It is expressed as the contact thermal resistance of each power semiconductor device under the target normal load, Expressed as the thickness of each layer of material in the power semiconductor device, Expressed as the thermal conductivity of each layer of material in the power semiconductor device, Expressed as the cross-sectional area of ​​each layer of material in the power semiconductor device in the direction perpendicular to the heat flow.

[0051] The present invention also provides a power semiconductor device junction temperature prediction system, which uses the power semiconductor device junction temperature prediction method described above, and comprises:

[0052] A prediction module is used to load the current normal load of the power semiconductor device as an input of the power semiconductor device junction temperature prediction model, and output the junction temperature value corresponding to the power semiconductor device under the current working condition;

[0053] A modeling module is used to obtain the contour roughness curves of each surface of the power semiconductor device; convert the contour roughness curves of adjacent surfaces into a smooth surface and a rough surface, and obtain equivalent fractal dimension parameters and equivalent fractal scale parameters; construct a three-dimensional equivalent fractal contact rough surface according to the equivalent fractal dimension parameters and equivalent fractal scale parameters, and obtain the elastic-plastic critical contact area of ​​the three-dimensional equivalent fractal contact rough surface; use the constructed three-dimensional equivalent fractal contact rough surface and elastic-plastic critical contact area, by changing the equivalent contact spacing of the three-dimensional equivalent fractal contact rough surface, iteratively calculate the corresponding real contact area, normal load, and contact thermal resistance value, and obtain the various contact thermal resistances of the power semiconductor device under the target normal load; according to the various contact thermal resistances of the power semiconductor device under the target normal load, combined with the shell temperature and heating power of the current power semiconductor device, and the body thermal resistance of each layer of the power semiconductor device, a power semiconductor device junction temperature prediction model is established.

[0054] Compared with the prior art, the invention has the following beneficial effects: the fractal theory is used to incorporate the contact thermal resistance into the junction temperature calculation model, and the obtained power semiconductor device junction temperature prediction model is more in line with the actual situation, and the result of junction temperature prediction is more accurate.

[0055] The influence of thyristor pressing force, that is, normal load on contact thermal resistance, is taken into account, so that the junction temperature prediction model of power semiconductor devices can be applied to junction temperature prediction under different normal loads and heat losses, with higher flexibility.

[0056] The three-dimensional equivalent fractal contact rough surface of thyristor is established through fractal theory, and the relationship between contact thermal resistance and contact load is calculated, that is, the contact thermal resistances of power semiconductor devices under target normal load. This relationship is taken into account in the junction temperature prediction model of power semiconductor devices, thereby realizing the calculation of thyristor junction temperature under different working conditions considering contact thermal resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 The present invention is a flowchart of the modeling steps of the power semiconductor device junction temperature prediction model according to an embodiment of the present invention.

[0058] Figure 2 Schematic diagram of a roughness curve of a profile according to an embodiment of the present invention.

[0059] Figure 3 Schematic diagram of the conversion of profile roughness curves of adjacent surfaces according to an embodiment of the present invention.

[0060] Figure 4 The present invention is a block diagram of a power semiconductor device junction temperature prediction system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0061] In order to facilitate those skilled in the art to understand the technical solution of the present invention, the technical solution of the present invention is further described in conjunction with the accompanying drawings of the specification.

[0062] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0063] See also Figure 1 As shown, the present invention provides a method for predicting the junction temperature of a power semiconductor device, including: loading the current normal load of the power semiconductor device as the input of a junction temperature prediction model of the power semiconductor device, and outputting the junction temperature value corresponding to the power semiconductor device under the current working condition.

[0064] The modeling steps of the power semiconductor device junction temperature prediction model include:

[0065] S10, obtaining a profile roughness curve of each surface of the power semiconductor device.

[0066] In one embodiment of the present invention, the power semiconductor device is a thyristor. Figure 2 As shown, the roughness scanner is used to scan different bonding surfaces of the thyristor to obtain the profile roughness curves of each surface of the thyristor.

[0067] S20, converting the roughness curves of the contours of the adjacent surfaces into a smooth surface and a rough surface, and obtaining an equivalent fractal dimension parameter and an equivalent fractal scale parameter.

[0068] like Figure 3 As shown, in one embodiment of the present invention, obtaining the equivalent fractal dimension parameter and the equivalent fractal scale parameter includes the following steps:

[0069] S21, obtaining a one-dimensional power density of a roughness curve of two adjacent surfaces of a power semiconductor device.

[0070] Among them, the one-dimensional power density is obtained by the following formula:

[0071] ;

[0072] In the formula, Represents a power semiconductor device The one-dimensional power spectral density of the surface, Expressed as the total length of the sampled signal, Represents a power semiconductor device The rough curve of the surface contour, is expressed as a natural constant, Expressed as an imaginary unit, Expressed as the angular frequency of the one-dimensional power spectrum.

[0073] S22, calculating the equivalent power density function of the two one-dimensional power densities, and fitting the equivalent power density function after taking the logarithm to obtain the equivalent power density linear function.

[0074] In this embodiment, the equivalent power density function is the sum of the one-dimensional power densities of the roughness curves of the two adjacent surfaces. And the equivalent power density linear function is obtained by the following formula:

[0075] ;

[0076] In the formula, It is expressed as an equivalent power density linear function, log is expressed as a logarithm, Expressed as the slope of the linear function of equivalent power density, Expressed as the intercept of the linear function of equivalent power density.

[0077] S23, obtaining an equivalent fractal dimension parameter and an equivalent fractal scale parameter according to the equivalent power density linear function.

[0078] In this embodiment, the equivalent fractal dimension parameter and the equivalent fractal scale parameter are obtained by the following formula:

[0079] ;

[0080] In the formula, Expressed as the equivalent fractal dimension parameter, Expressed as the equivalent fractal scale parameter, Expressed as the slope of the linear function of equivalent power density, Expressed as the intercept of the linear function of equivalent power density, is a constant, log represents logarithm, and In represents natural logarithm.

[0081] S30, constructing a three-dimensional equivalent fractal contact rough surface according to the equivalent fractal dimension parameter and the equivalent fractal scale parameter, and obtaining the elastic-plastic critical contact area of ​​the three-dimensional equivalent fractal contact rough surface.

[0082] In this embodiment, the three-dimensional equivalent fractal contact rough surface is obtained by the following formula:

[0083] ;

[0084] In the formula, Represented as a three-dimensional equivalent fractal contact rough surface, Expressed as the equivalent fractal scale parameter, Expressed as the sample length of the rough surface profile, Expressed as a three-dimensional equivalent fractal dimension parameter, is a constant usually taken as 1.5. Expressed as the number of superimposed layers, for A subset of is expressed as the minimum contour frequency, Represented as a random phase, Expressed as pi, It is expressed as spatial position coordinates, cos is expressed as cosine function, and tan is expressed as tangent function. .

[0085] Obtaining the elastic-plastic critical contact area includes the following steps:

[0086] S31, calculate the equivalent Young's modulus and hardness of the three-dimensional equivalent fractal contact rough surface.

[0087] In this embodiment, the equivalent Young's modulus and hardness are obtained by the following formula:

[0088] ;

[0089] ;

[0090] In the formula, Expressed as the equivalent Young's modulus, , They are respectively represented as the Young's modulus of the two contacting materials, Expressed as hardness, , They are respectively expressed as the hardness of the two contacting materials, , They are respectively expressed as the Poisson's ratio of the two contacting materials.

[0091] S32, using the equivalent Young's modulus and hardness, calculate the elastic-plastic critical contact area of ​​the contact surface.

[0092] In this embodiment, the elastic-plastic critical contact area is obtained by the following formula:

[0093] ;

[0094] In the formula, Expressed as the elastic-plastic critical contact area.

[0095] S40, using the constructed three-dimensional equivalent fractal contact rough surface and elastic-plastic critical contact area, by changing the equivalent contact spacing of the three-dimensional equivalent fractal contact rough surface, iteratively calculate the corresponding real contact area, normal load, and contact thermal resistance value, and obtain the contact thermal resistances of the power semiconductor device under the target normal load.

[0096] In one embodiment of the present invention, determining each contact thermal resistance of a power semiconductor device under a target normal load comprises the following steps:

[0097] S41, calculate the maximum value corresponding to the equivalent contact spacing of the three-dimensional equivalent fractal contact rough surface and the minimum value .

[0098] S42, set the maximum number of iterations and target normal load ;

[0099] S43, initialize the current label value and equivalent contact spacing ;in, Represents the current iteration value.

[0100] S44, calculate the total cross-sectional area of ​​the three-dimensional equivalent fractal contact rough surface .

[0101] In this embodiment, the total cross-sectional area , obtained by the following formula:

[0102] ;

[0103] In the formula, Expressed as the total length of the sampled signal, Expressed as the sample length of the rough surface profile, represents the three-dimensional equivalent fractal contact rough surface, Expressed as equivalent contact spacing.

[0104] S45, obtaining the maximum cross-sectional area of ​​the three-dimensional equivalent fractal contact rough surface according to the total cross-sectional area of ​​the three-dimensional equivalent fractal contact rough surface .

[0105] In this embodiment, the maximum cross-sectional area , obtained by the following formula:

[0106] ;

[0107] S46, based on the comparison results of the maximum cross-sectional area and the elastic-plastic critical contact area, the real contact area of ​​the three-dimensional equivalent fractal contact rough surface is obtained ;

[0108] like ;but:

[0109] ;

[0110] ;

[0111] like ;but:

[0112] ;

[0113] ;

[0114] ;

[0115] In the formula, is represented by the plastic contact area, Expressed as the elastic contact area.

[0116] S47, combined with the maximum cross-sectional area, obtains the normal contact load of the three-dimensional equivalent fractal contact rough surface .

[0117] In this embodiment, the normal contact load , where Expressed as elastic deformation load, is expressed as plastic deformation load. Among them, and are obtained by the following formulas:

[0118] ;

[0119] ;

[0120] S48, based on the real contact area and the equivalent thermal conductivity of the joint surface, obtain the equivalent contact thermal resistance of the three-dimensional equivalent fractal contact rough surface .

[0121] In one embodiment of the present invention, the equivalent contact thermal resistance , obtained by the following formula:

[0122] ;

[0123] ;

[0124] In the formula, Expressed as the equivalent thermal conductivity of the joint surface, Expressed as the nominal contact area of ​​the bonding surface, , They are respectively expressed as the thermal conductivity of the materials in contact with each other on the bonding surface.

[0125] S48, Iteration ; Transfer to the calculation of contact thermal resistance value under equivalent contact spacing of the next iteration; Among them, Represents the number of next iterations;

[0126] S49, determine the normal contact load under the current iteration number Is it consistent with the target normal load? If not, the equivalent contact spacing of the current iteration number is , and proceed to step S44; if so, the contact thermal resistance of each power semiconductor device ;in, Expressed as the equivalent contact spacing of the previous iteration number.

[0127] S50, establishing a power semiconductor device junction temperature prediction model according to each contact thermal resistance of the power semiconductor device under the target normal load, combined with the current shell temperature and heat generation power of the power semiconductor device, and the body thermal resistance of each layer material of the power semiconductor device.

[0128] In one embodiment of the present invention, the power semiconductor device junction temperature prediction model is obtained by the following formula:

[0129] ;

[0130] ;

[0131] In the formula, Expressed as the junction temperature of the power semiconductor device, It is expressed as the case temperature of the current power semiconductor device. It is expressed as the heat generation power of the current power semiconductor device. It is expressed as the bulk thermal resistance of each layer of materials in the power semiconductor device. It is expressed as the contact thermal resistance of each power semiconductor device under the target normal load, Expressed as the thickness of each layer of material in the power semiconductor device, Expressed as the thermal conductivity of each layer of material in the power semiconductor device, Expressed as the cross-sectional area of ​​each layer of material in the power semiconductor device in the direction perpendicular to the heat flow.

[0132] See also Figures 1 to 4 As shown, the present invention also provides a power semiconductor device junction temperature prediction system, which applies the power semiconductor device junction temperature prediction method described above, and comprises:

[0133] The measuring module 10 is used to load the current normal load of the power semiconductor device as the input of the power semiconductor device junction temperature prediction model, and output the junction temperature value corresponding to the power semiconductor device under the current working condition;

[0134] The modeling module 20 is used to obtain the contour roughness curve of each surface of the power semiconductor device; convert the contour roughness curve of the adjacent surfaces into a smooth surface and a rough surface, and obtain the equivalent fractal dimension parameter and the equivalent fractal scale parameter; construct a three-dimensional equivalent fractal contact rough surface according to the equivalent fractal dimension parameter and the equivalent fractal scale parameter, and obtain the elastic-plastic critical contact area of ​​the three-dimensional equivalent fractal contact rough surface; use the constructed three-dimensional equivalent fractal contact rough surface and the elastic-plastic critical contact area, by changing the equivalent contact spacing of the three-dimensional equivalent fractal contact rough surface, iteratively calculate the corresponding real contact area, normal load, and contact thermal resistance value, and obtain the various contact thermal resistances of the power semiconductor device under the target normal load; according to the various contact thermal resistances of the power semiconductor device under the target normal load, combined with the shell temperature and heating power of the current power semiconductor device, and the body thermal resistance of each layer of the power semiconductor device, a power semiconductor device junction temperature prediction model is established.

[0135] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be regarded as exemplary and non-limiting from any point of view, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims are included in the present invention, and any reference numerals in the claims should not be regarded as limiting the claims involved.

[0136] The above-described embodiments merely represent implementation methods of the invention. The protection scope of the present invention is not limited to the above-described embodiments. For those skilled in the art, several modifications and improvements may be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A method for predicting junction temperature of a power semiconductor device, characterized in that: include: The current normal load of the power semiconductor device is loaded as the input of the power semiconductor device junction temperature prediction model, and the junction temperature value corresponding to the power semiconductor device under the current working condition is output; wherein the modeling steps of the power semiconductor device junction temperature prediction model include: Obtaining contour roughness curves of various surfaces of power semiconductor devices; The roughness curves of the contours of the adjacent surfaces are converted into a smooth surface and a rough surface, and an equivalent fractal dimension parameter and an equivalent fractal scale parameter are obtained; According to the equivalent fractal dimension parameter and the equivalent fractal scale parameter, a three-dimensional equivalent fractal contact rough surface is constructed, and the elastic-plastic critical contact area of ​​the three-dimensional equivalent fractal contact rough surface is obtained; By using the constructed three-dimensional equivalent fractal contact rough surface and elastic-plastic critical contact area, and changing the equivalent contact spacing of the three-dimensional equivalent fractal contact rough surface, the corresponding real contact area, normal load, and contact thermal resistance value are iteratively calculated to obtain the contact thermal resistances of the power semiconductor device under the target normal load. According to the contact thermal resistances of the power semiconductor device under the target normal load, combined with the shell temperature and heat generation power of the current power semiconductor device, and the body thermal resistance of each layer of material of the power semiconductor device, a power semiconductor device junction temperature prediction model is established.

2. The method for predicting junction temperature of a power semiconductor device according to claim 1, characterized in that: Obtaining the equivalent fractal dimension parameter and the equivalent fractal scale parameter includes the following steps: Obtaining one-dimensional power density of the roughness curve of the profile of two adjacent surfaces of the power semiconductor device; Calculate the equivalent power density function of two one-dimensional power densities, and fit the equivalent power density function after taking the logarithm to obtain the equivalent power density linear function; According to the equivalent power density linear function, the equivalent fractal dimension parameter and the equivalent fractal scale parameter are obtained.

3. The method for predicting junction temperature of a power semiconductor device according to claim 2, characterized in that: The equivalent fractal dimension parameter and equivalent fractal scale parameter are obtained by the following formula: ； In the formula, Expressed as the equivalent fractal dimension parameter, Expressed as the equivalent fractal scale parameter, Expressed as the slope of the linear function of equivalent power density, Expressed as the intercept of the linear function of equivalent power density, is a constant, log represents logarithm, and In represents natural logarithm.

4. The method for predicting junction temperature of a power semiconductor device according to claim 1, characterized in that: Obtaining the elastic-plastic critical contact area includes the following steps: Calculate the equivalent Young's modulus and hardness of three-dimensional equivalent fractal contact rough surface; The elastic-plastic critical contact area of ​​the contact surface is calculated using the equivalent Young's modulus and hardness.

5. The method for predicting junction temperature of a power semiconductor device according to claim 4, characterized in that: The three-dimensional equivalent fractal contact rough surface is obtained by the following formula: ； In the formula, Represented as a three-dimensional equivalent fractal contact rough surface, Expressed as the equivalent fractal scale parameter, Expressed as the sample length of the rough surface profile, Expressed as a three-dimensional equivalent fractal dimension parameter, is a constant, Expressed as the number of superimposed layers, for A subset of is expressed as the minimum contour frequency, Represented as a random phase, Expressed as pi, It is expressed as spatial position coordinates, cos is expressed as cosine function, and tan is expressed as tangent function.

6. The method for predicting junction temperature of a power semiconductor device according to claim 5, characterized in that: The elastic-plastic critical contact area is obtained by the following formula: ； In the formula, Expressed as the elastic-plastic critical contact area, Expressed as the equivalent Young's modulus, Expressed as hardness.

7. The method for predicting junction temperature of a power semiconductor device according to claim 1, characterized in that: Determining the various contact thermal resistances of the power semiconductor device under the target normal load includes the following steps: S41, calculate the maximum value corresponding to the equivalent contact spacing of the three-dimensional equivalent fractal contact rough surface and the minimum value ; S42, set the maximum number of iterations and target normal load ; S43, initialize the current label value and equivalent contact spacing ;in, Represents the current iteration value; S44, calculate the total cross-sectional area of ​​the three-dimensional equivalent fractal contact rough surface ; S45, obtaining the maximum cross-sectional area of ​​the three-dimensional equivalent fractal contact rough surface according to the total cross-sectional area of ​​the three-dimensional equivalent fractal contact rough surface ; S46, based on the comparison results of the maximum cross-sectional area and the elastic-plastic critical contact area, the real contact area of ​​the three-dimensional equivalent fractal contact rough surface is obtained ; S47, combined with the maximum cross-sectional area, obtains the normal contact load of the three-dimensional equivalent fractal contact rough surface ; S48, based on the real contact area and the equivalent thermal conductivity of the joint surface, obtain the equivalent contact thermal resistance of the three-dimensional equivalent fractal contact rough surface ; S48, Iteration ; Transfer to the calculation of contact thermal resistance value under equivalent contact spacing of the next iteration; Among them, Represents the number of next iterations; S49, determine the normal contact load under the current iteration number Is it consistent with the target normal load? If not, the equivalent contact spacing of the current iteration number is , and proceed to step S44; if so, the contact thermal resistance of each power semiconductor device ;in, Expressed as the equivalent contact spacing of the previous iteration number.

8. The method for predicting junction temperature of a power semiconductor device according to claim 7, characterized in that: Equivalent contact thermal resistance , obtained by the following formula: ； ； In the formula, Expressed as the equivalent thermal conductivity of the joint surface, Expressed as the nominal contact area of ​​the bonding surface, , They are respectively expressed as the thermal conductivity of the materials in contact with each other on the bonding surface.

9. The method for predicting junction temperature of a power semiconductor device according to claim 1, characterized in that: The power semiconductor device junction temperature prediction model is obtained by the following formula: ； ； In the formula, Expressed as the junction temperature of the power semiconductor device, It is expressed as the case temperature of the current power semiconductor device. It is expressed as the heat generation power of the current power semiconductor device. It is expressed as the bulk thermal resistance of each layer of materials in the power semiconductor device. It is expressed as the contact thermal resistance of each power semiconductor device under the target normal load, Expressed as the thickness of each layer of material in the power semiconductor device, Expressed as the thermal conductivity of each layer of material in the power semiconductor device, Expressed as the cross-sectional area of ​​each layer of material in the power semiconductor device in the direction perpendicular to the heat flow.

10. A power semiconductor device junction temperature prediction system, characterized in that: The method for predicting junction temperature of a power semiconductor device according to any one of claims 1 to 9 comprises: A prediction module is used to load the current normal load of the power semiconductor device as an input of the power semiconductor device junction temperature prediction model, and output the junction temperature value corresponding to the power semiconductor device under the current working condition; A modeling module is used to obtain the contour roughness curves of each surface of the power semiconductor device; convert the contour roughness curves of adjacent surfaces into a smooth surface and a rough surface, and obtain equivalent fractal dimension parameters and equivalent fractal scale parameters; construct a three-dimensional equivalent fractal contact rough surface according to the equivalent fractal dimension parameters and equivalent fractal scale parameters, and obtain the elastic-plastic critical contact area of ​​the three-dimensional equivalent fractal contact rough surface; use the constructed three-dimensional equivalent fractal contact rough surface and elastic-plastic critical contact area, by changing the equivalent contact spacing of the three-dimensional equivalent fractal contact rough surface, iteratively calculate the corresponding real contact area, normal load, and contact thermal resistance value, and obtain the various contact thermal resistances of the power semiconductor device under the target normal load; according to the various contact thermal resistances of the power semiconductor device under the target normal load, combined with the shell temperature and heating power of the current power semiconductor device, and the body thermal resistance of each layer of the power semiconductor device, a power semiconductor device junction temperature prediction model is established.

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