Circuit controllability analysis method, device, electronic device, storage medium and program product

Abstract

The present application provides a method, device, electronic device, storage medium and program product for analyzing the controllability of a circuit, and relates to the field of integrated circuit technology. The method for analyzing the controllability of a circuit includes: determining the analysis starting point of the controllability of a target integrated circuit; creating a working set, and adding the analysis starting point as a driving object to the working set; taking out a driving object from the working set as a target driving object, and determining the controllability result of the target driving object; performing a preset process for each target receiving object connected to the target driving object, wherein, after the preset process is performed for all target receiving objects, returning to perform the process of taking out a driving object from the working set as a target driving object, and determining the controllability result of the target driving object. According to the present application, static analysis of circuit controllability can be performed efficiently and accurately.

Description

Technical Field

[0001] The present application generally relates to the field of integrated circuit technology, and more specifically, to a method, device, electronic device, storage medium and program product for analyzing circuit controllability. Background Art

[0002] With the advancement of manufacturing technology and design technology, the design methods of electronic systems have undergone profound changes, from computer-aided design (CAD), computer-aided engineering (CAE) to electronic design automation (EDA), the degree of design automation is getting higher and higher, and the complexity of design is getting stronger and stronger.

[0003] Integrated circuit EDA refers to the design method that uses computer-aided design software to complete the functional design, synthesis, verification, physical design (including layout, wiring, layout, design rule checking, etc.) of ultra-large-scale integrated circuit chips. At present, EDA technology has become a powerful tool for modern electronic design. Without the support of EDA technology, it is unimaginable to complete the design and manufacture of ultra-large-scale integrated circuits. Integrated circuit designers need to use EDA tools to design complex integrated circuits with hundreds of thousands to tens of billions of transistors to reduce design deviations, improve the success rate of tape-out and save tape-out costs.

[0004] As the chip manufacturing process becomes smaller and smaller (for example, 5nm) and the chip scale becomes larger and larger, the testing of chips becomes more and more difficult. Testing is an especially important part of chip development and cannot be ignored. Design for Test (DFT) is a concept that emerged with testing. Currently, DFT is indispensable in chip design. DFT refers to the insertion of various hardware logics used to improve the testability of the chip (including controllability and observability) during the original design stage of the chip. Through this part of the logic, test vectors are generated to achieve the purpose of testing large-scale chips. Integrated circuit designers often use EDA tools to quickly insert DFT circuits into the design or quickly perform DFT rule checks on the entire circuit to reliably achieve agile development.

[0005] In EDA's DFT-related tools, analyzing the controllability of circuits is critical for fault model analysis and circuit design rule checking. The faster the controllability analysis, the faster the fault coverage estimation calculation. However, existing circuit controllability analysis methods are time-consuming and the analysis efficiency needs to be further improved. Summary of the invention

[0006] An exemplary embodiment of the present application is to provide a method, device, electronic device, storage medium and program product for analyzing circuit controllability, which can efficiently and accurately perform static analysis on circuit controllability.

[0007] According to a first aspect of an embodiment of the present application, a method for analyzing circuit controllability is provided, comprising: determining an analysis starting point of controllability of a target integrated circuit; creating a working set, and adding the analysis starting point as a driving object to the working set; taking out a driving object from the working set as a target driving object, and determining a controllability result of the target driving object; performing a preset process for each target receiving object connected to the target driving object, wherein, after the preset process is performed for all target receiving objects, returning to perform the process of taking out a driving object from the working set as a target driving object, and determining a controllability result of the target driving object; wherein the preset process comprises: obtaining a controllability result of the target receiving object according to the controllability result of the target driving object, and judging whether the controllability results of the preset type input pins of the target logic unit where the target receiving object is located have all been obtained; if all have been obtained, adding the output pins of the target logic unit as driving objects to the working set; wherein the controllability result of an object indicates: whether the object can be controlled to be at a logic value of 0, and whether the object can be controlled to be at a logic value of 1.

[0008] According to a second aspect of an embodiment of the present application, a circuit controllability analysis device is provided, comprising: a starting point determination unit, configured to determine an analysis starting point of the controllability of a target integrated circuit; a set creation unit, configured to create a working set, and add the analysis starting point as a driving object to the working set; a result determination unit, configured to take a driving object from the working set as a target driving object, and determine the controllability result of the target driving object; a processing execution unit, configured to execute a preset processing for each target receiving object connected to the target driving object, wherein after the preset processing is executed for all target receiving objects, Afterwards, return to execute the process of taking out a driving object from the working set as the target driving object, and determining the controllability result of the target driving object; wherein the preset processing includes: obtaining the controllability result of the target receiving object according to the controllability result of the target driving object, and judging whether the controllability results of the preset type input pins of the target logic unit where the target receiving object is located have all been obtained; if all have been obtained, adding the output pins of the target logic unit as the driving object to the working set; wherein the controllability result of the object indicates: whether the object can be controlled to be at a logic value of 0, and whether the object can be controlled to be at a logic value of 1.

[0009] According to a third aspect of an embodiment of the present application, a computer-readable storage medium storing instructions is provided. When the instructions are executed by a processor of an electronic device, the electronic device is enabled to perform the circuit controllability analysis method as described above.

[0010] According to a fourth aspect of an embodiment of the present application, an electronic device is provided, comprising: at least one processor; and at least one memory storing computer executable instructions, wherein the computer executable instructions, when executed by the at least one processor, prompt the at least one processor to execute the circuit controllability analysis method as described above.

[0011] According to a fifth aspect of an embodiment of the present application, a computer program product is provided, comprising computer executable instructions, which, when executed by at least one processor, implement the circuit controllability analysis method as described above.

[0012] According to the circuit controllability analysis method, device, electronic device, storage medium and program product of the exemplary embodiments of the present application, the efficiency of circuit controllability analysis can be greatly improved and the analysis time can be shortened.

[0013] Other aspects and / or advantages of the general inventive concept of the present application will be set forth in part in the following description, and some will be clear from the description or may be learned through practice of the general inventive concept of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other objects and features of the exemplary embodiments of the present application will become more apparent through the following description in conjunction with the accompanying drawings which exemplarily illustrate the embodiments, wherein:

[0015] Figure 1 Static analysis examples showing existing circuit controllability;

[0016] Figure 2 A flow chart showing a method for analyzing circuit controllability according to an exemplary embodiment of the present application;

[0017] Figure 3 A flowchart showing a method for determining a controllability result of a target driven object according to a category of a logical unit where the target driven object is located according to an exemplary embodiment of the present application;

[0018] Figure 4 A flow chart showing a method for obtaining a controllability result of a target driven object through logic analysis according to an exemplary embodiment of the present application;

[0019] Figure 5 An example of determining an initial remaining number of accesses according to an exemplary embodiment of the present application is shown;

[0020] Figure 6 Another example of determining the initial remaining number of accesses according to an exemplary embodiment of the present application is shown;

[0021] Figure 7 An example of determining a controllability result of a driven object according to an exemplary embodiment of the present application is shown;

[0022] Figure 8 An example of an analysis method of circuit controllability according to an exemplary embodiment of the present application is shown;

[0023] Fig. 9 A block diagram showing a circuit controllability analysis device according to an exemplary embodiment of the present application;

[0024] Fig.10 A structural block diagram of an electronic device according to an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0025] Reference will now be made in detail to embodiments of the present application, examples of which are shown in the accompanying drawings, wherein like reference numerals refer to like parts throughout. The embodiments will be described below with reference to the accompanying drawings in order to explain the present application.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims.

[0027] It should be noted that the phrase "at least one of the items" in this application includes three types of parallel situations: "any one of the items", "a combination of any number of the items", and "all of the items". For example, "including at least one of A and B" includes the following three parallel situations: (1) including A; (2) including B; (3) including A and B. Another example is "executing at least one of step 1 and step 2" which means the following three parallel situations: (1) executing step 1; (2) executing step 2; (3) executing step 1 and step 2.

[0028] In integrated circuit chip design, the functions and behaviors of electronic circuits are described by hardware description languages ​​(HDL). The hardware description languages ​​are used to describe the structure and behavior of digital logic system hardware in text form. They can represent logic circuit diagrams, logic expressions, and logic functions performed by digital logic systems, so that multiple abstract design levels such as algorithm level, register transfer level, gate level, and switch level can be modeled. Integrated circuit designers usually use hardware description languages ​​such as Verilog HDL (Verilog for short), VHDL (Very High Speed ​​Integrated Circuit HDL), and System Verilog HDL for design.

[0029] As the requirements change at different design stages, EDA tools divide the analysis of designs into static analysis and dynamic analysis. Dynamic analysis simulates the actual operation of the designed circuit based on the stimulus signal, and actually considers the delays, input and output values ​​of each unit in the circuit. Given the current situation where the circuit structure is generally large, a dynamic analysis usually takes up to several months. In contrast, static analysis usually does not consider delays, values, etc. when checking the circuit structure corresponding to the design file, so static analysis usually takes several hours.

[0030] The current common static analysis method for circuit controllability is to directly simulate the input pins or ports of the circuit with logical values ​​0 and 1 to obtain an accurate result. However, the time required for the simulation method is huge, and the amount of calculation required is also huge. Therefore, this method covers up the speed advantage of static analysis, especially for DFT rule checking tools that are not related to ATPG (Automatic Test Pattern Generation), this simulation method is even more undesirable, because the time consumed by the simulation is often the sum of all other rule checking operations, or even more.

[0031] Figure 1 An example of static analysis of existing circuit controllability is shown. Figure 1 As shown, taking the analysis of a simple 4-bit input circuit as an example, if the pseudo-simulation method is used, a total of 2 to the power of 4 (i.e., 16) logic value combinations are required for analysis. In other words, a simple circuit requires 16 analyses, and each combination of logic gates requires at least 16 calculations to complete the controllability analysis of the entire circuit.

[0032] Considering the above problems existing in the common static analysis methods of circuit controllability, this application proposes to use BFS (Breadth First Search) to perform circuit controllability analysis. During the analysis process, the efficiency will no longer be greatly affected by the number of circuit inputs, and multiple analyses are not required, only one analysis is required. At the same time, logical values ​​0 and 1 are no longer directly used for analysis, but the concept of controllability results is used for analysis.

[0033] The controllability result of an object (a pin or port in an integrated circuit) indicates whether the object can be controlled to be at a logic value of 0 (i.e., whether the object may or can be at a logic value of 0), or whether the object can be controlled to be at a logic value of 1 (i.e., whether the object may or can be at a logic value of 1).

[0034] As an exemplary embodiment, the specific forms of the controllability results of the object may include the following four types:

[0035] YY: indicates that the object can be controlled to be at a logical value of 0 or at a logical value of 1 (that is, both logical values ​​0 and 1 can be controlled);

[0036] YN: Indicates that the object can be controlled to be at a logic value of 0, but cannot be controlled to be at a logic value of 1 (that is, logic value 0 is controllable, and logic value 1 is uncontrollable);

[0037] NY: Indicates that the object can be controlled to be at a logical value of 1, but cannot be controlled to be at a logical value of 0 (that is, logical value 1 is controllable, and logical value 0 is uncontrollable);

[0038] NN: Indicates that the object cannot be controlled to be at a logical value of 0, nor can it be controlled to be at a logical value of 1 (that is, both logical values ​​0 and 1 are uncontrollable, or the logical values ​​cannot be predicted). For example, Figure 6 The controllability result for the pins shown as not connected (NC) is: NN.

[0039] As an example, the controllable values ​​of the primary input port on the top module can be assumed to be 0 and 1, that is, the primary input port can be controlled to be at a logical value of 0 or at a logical value of 1). Therefore, the controllability result of the primary input port can be expressed as: YY, where the first Y represents the controllability of the logical value 0, and the second Y represents the controllability of the logical value 1. As another example, if the logical value of an object is a constant 1'b0, it means that the object can only be controlled to be at a logical value of 0, that is, only a logical value of 0 is controllable. Therefore, the controllability result of the object can be expressed as: YN.

[0040] The following will be combined Figures 2 to 10Exemplary embodiments of the present application are described in detail.

[0041] Figure 2 A flow chart showing a method for analyzing circuit controllability according to an exemplary embodiment of the present application is shown. The analysis method can be implemented by a computer program, and as an example, the method can be executed by application software (eg, EDA tool) installed in an electronic device.

[0042] Reference Figure 2 , in step S100 , a starting point for analyzing the controllability of the target integrated circuit is determined.

[0043] As an exemplary embodiment, step S100 may include: reading a design file of a target integrated circuit, and determining an analysis starting point of controllability of the target integrated circuit according to the design file.

[0044] The number of analysis starting points may be one or more. As an exemplary embodiment, the analysis starting point may include, but is not limited to: a controllable point of the target integrated circuit, a pin and a port whose logic value is a constant value (i.e., a constant logic value of 0 or a constant logic value of 1). A controllable point may be understood as a pin and a port for controlling the target integrated circuit. As an example, a controllable point may include, but is not limited to: a total input port of the target integrated circuit, an output pin of a preset type unit. For example, a preset type unit may include, but is not limited to: Scannable Flip-Flop (FF, trigger), BlackBox with ScanWrap, Memory with ScanWrap.

[0045] As an exemplary embodiment, the circuit controllability analysis method according to the exemplary embodiment of the present application may further include: determining the analysis endpoint of the controllability of the target integrated circuit. As an example, the primary output port of the target integrated circuit may be determined as the analysis endpoint, and when encountered during the analysis process, the forward analysis is stopped.

[0046] In step S200, a working set is created, and an analysis starting point is added to the working set as a driving object, that is, the working set initially includes one or more analysis starting points.

[0047] As an exemplary embodiment, the data structure of the working set can be set to a non-linear structure, in which the data (i.e., the driving objects) can be taken out in any order or randomly, so that it can be used with the multi-threading mentioned later. The traditional BFS method is to set the storage data structure to a linear structure (such as a stack or a queue).

[0048] In step S300, a driving object is taken out from the working set as a target driving object, and a controllability result of the target driving object is determined.

[0049] As an exemplary embodiment, a drive object taken out of the working set will no longer remain in the working set.

[0050] As an exemplary embodiment, when the target driving object is a controllable point, the controllability result of determining the target driving object is: YY.

[0051] As an exemplary embodiment, when the target driving object is a pin or a port that is constantly at a logic value of 0, the result of determining the controllability of the target driving object is: YN.

[0052] As an exemplary embodiment, when the target driving object is a pin or a port that is constantly at a logic value of 1, the result of determining the controllability of the target driving object is: NY.

[0053] As an exemplary embodiment, when the target driven object is not the analysis starting point, the controllability result of the target driven object is determined according to the category of the logic unit where the target driven object is located. The logic unit where the target driven object is located, that is, the instance where the target driven object is located, can be a basic logic unit (for example, an AND gate, an OR gate, a NOT gate), or a sequential logic unit composed of basic logic units (for example, a flip-flop FF, a latch Latch).

[0054] The following will be combined Figure 3 An exemplary embodiment of determining the controllability result of a target driven object according to the category of the logical unit where the target driven object is located is described, which will not be expanded here.

[0055] In step S400, a preset process is performed for each target receiving object connected to the target driving object, wherein after the preset process is performed for all target receiving objects connected to the target driving object, the process returns to step S300.

[0056] The target receiving object connected to the target driving object is the port and pin to which the target driving object is directly connected through a net. The number of the target receiving objects can be one or more.

[0057] The preset processing includes: obtaining the controllability result of the target receiving object according to the controllability result of the target driving object, and judging whether the controllability results of the preset type input pins of the target logic unit where the target receiving object is located have all been obtained; if all have been obtained, adding the output pins of the target logic unit as driving objects to the working set.

[0058] As an exemplary embodiment, the step of obtaining the controllability result of the target receiving object according to the controllability result of the target driving object includes: using the controllability result of the target driving object as the controllability result of the target receiving object.

[0059] As an exemplary embodiment, the preset type input pin may include a data input pin connected to a general input port of a target integrated circuit or an output pin of a logic unit.

[0060] As an exemplary embodiment, the step of determining whether all controllability results of the preset type input pins of the target logic unit where the target receiving object is located have been obtained includes: after obtaining the controllability result of the target receiving object, reducing the remaining access count of the target logic unit by 1 to update the remaining access count; if the updated remaining access count is less than 1, determining that all controllability results of the preset type input pins of the target logic unit have been obtained; if the updated remaining access count is greater than or equal to 1, determining that not all controllability results of the preset type input pins of the target logic unit have been obtained.

[0061] The initial remaining access count of the target logic unit is: the number of preset type input pins of the target logic unit.

[0062] As an exemplary embodiment, the circuit controllability analysis method according to the exemplary embodiment of the present application may also include: calculating the number of accesses required for all logic units where the analysis starting point is not located (that is, the initial remaining number of accesses), and only considering data pins when calculating the number, and pins with drivers (that is, pins connected to the main input port or output pins of other logic units), that is, taking the number of data pins with drivers as the initial remaining number of accesses of the corresponding logic unit.

[0063] For example, Figure 5 As shown in , the instance has 2 data pins of the driver, so its initial remaining access count is 2. Figure 6 As shown, the instance has 1 data pin of the driver, so its initial remaining access count is 1.

[0064] Furthermore, as an exemplary embodiment, step S300 and step S400 may be independently performed by each of a plurality of parallel threads.

[0065] The single-threaded processing method is to process the driver objects in the current working set one by one.

[0066] The multi-threaded processing method is to put a driver object in the current working set into a thread for processing (that is, one thread executes step S300 and step S400 for one driver object), so that according to the number of threads, multiple driver objects are put into multiple threads for parallel processing. For example, eight threads can process eight objects at the same time, and different threads are independent of each other and do not interfere with each other, and the driver objects processed are different.

[0067] Figure 3 A flow chart showing a method for determining a controllability result of a target driven object according to a category of a logical unit where the target driven object is located according to an exemplary embodiment of the present application.

[0068] Reference Figure 3 In step S301, it is determined whether the logical unit where the target driving object is located belongs to a specific category.

[0069] As an example, a specific category may include, but is not limited to: a flip-flop FF, and a latch Latch.

[0070] In step S302, if the logic unit belongs to a specific category, it is determined whether the logic unit is in a reset active state or a set active state.

[0071] As an exemplary embodiment, step S302 may include: determining whether the logic unit is in a reset activation state; if the logic unit is in the reset activation state, determining the controllability result of the target driven object as follows: the target driven object can be controlled to be at a logic value of 0, and the target driven object cannot be controlled to be at a logic value of 1 (for example, can be expressed as YN); if the logic unit is not in the reset activation state, determining whether the logic unit is in a set activation state; if the logic unit is in the set activation state, determining the controllability result of the target driven object as follows: the target driven object cannot be controlled to be at a logic value of 0, and the target driven object can be controlled to be at a logic value of 1 (for example, can be expressed as NY); if the logic unit is not in the set activation state, determining that the logic unit is neither in the reset activation state nor in the set activation state (that is, the logic unit is not in the reset activation state or the set activation state).

[0072] It should be understood that the logic unit not being in the reset activation state may include two situations: the logic unit does not have a reset pin, or has a reset pin but the reset pin is not in the activation state; the logic unit being in the reset activation state may include: having a reset pin and the reset pin is in the activation state; the logic unit not being in the set activation state may include two situations: the logic unit does not have a set pin, or has a set pin but the set pin is not in the activation state; the logic unit being in the set activation state may include: having a set pin and the set pin is in the activation state.

[0073] In step S303, if the logic unit does not belong to a specific category or the logic unit is not in a reset activation state or a set activation state, a controllability result of a target driving object is determined based on a controllability result of a data input pin of the logic unit.

[0074] As an exemplary embodiment, step S303 may include: if the logic unit is not in a reset activation state or a set activation state, determining whether the type of the logic unit meets a preset condition; if the type of the logic unit meets the preset condition, taking the controllability result of the data input pin of the logic unit as the controllability result of the target driving object; if the logic unit does not belong to a specific category, or the type of the logic unit does not meet the preset condition, obtaining the controllability result of the target driving object through logical calculation based on the controllability result of the data input pin of the logic unit.

[0075] As an example, the step of determining whether the type of the logic unit meets the preset condition may include: determining whether the type of the logic unit is a Retiming type, and if it is a Retiming type, determining that the preset condition is met; if it is not a Retiming type, determining whether the type of the logic unit is a Transparent type, and if it is a Transparent type, determining that the preset condition is met; if it is not a Transparent type, determining that the preset condition is not met. In addition, for example, if the logic unit is FF, if it is determined that it is not a Retiming type, it can be directly determined that it does not meet the preset condition.

[0076] According to the exemplary embodiments of the present application, the accuracy of analysis can be ensured and the efficiency of analysis can be improved.

[0077] Figure 4 A flow chart showing a method for obtaining a controllability result of a target driven object through logic analysis according to an exemplary embodiment of the present application.

[0078] Reference Figure 4In step S401, based on the controllability results of the data input pins of the logic unit where the target driving object is located, the possible logic values ​​of the data input pins are determined.

[0079] As an example, if the controllability result of a data input pin is YY, its possible logic values ​​are 0 and 1; if the controllability result is YN, its possible logic value is 0; if the controllability result is NY, its possible logic value is 1.

[0080] In step S402, based on the possible logic values ​​of the data input pins, possible input state combinations of the logic unit are determined.

[0081] Each input state combination includes: a possible logic value of each data input pin.

[0082] In step S403, for each possible input state combination of the logic unit, possible logic values ​​of the output pin of the logic unit (ie, the target driving object) are determined.

[0083] As an exemplary embodiment, step S403 may include: determining a logic expression for representing the function of the logic unit; and calculating the possible logic values ​​of the output pin of the logic unit according to the logic expression for each possible input state combination of the logic unit.

[0084] As an example, the library file may be traversed, and according to the output pin of the logic unit, a logic expression for representing the function of the logic unit may be determined in the library file. For example, the logic expression corresponding to the output pin may be found in the library file as the logic expression for representing the function of the logic unit.

[0085] In step S404, the controllability result of the target driving object is determined based on the possible logic values ​​of the output pins of the logic unit.

[0086] like Figure 7As shown, the logical expression of the function of the logic unit where the target drive object A is located is D&E. Due to BFS, when determining the controllability result of the target drive object A, the controllability results of all data input pins D and E of the logic unit where the target drive object A is located have been obtained. The controllability result of the data input pin D is YY, that is, the possible logical values ​​of the data input pin D are 0 and 1; the controllability result of the data input pin E is YN, that is, the possible logical value of the data input pin E is 0, so the possible input state combinations (DE) of the logic unit are: 0-0 and 1-0. Next, the input state combination 0-0 is substituted into the logical expression D&E for logical calculation, and the possible logical value of the output pin A of the logic unit (that is, the target drive object A) is obtained: 0; and the input state combination 1-0 is substituted into the logical expression D&E for logical calculation, and the possible logical value of the output pin A is obtained: 0. Therefore, the possible logical value of the output pin A is only 0, and accordingly, the controllability result of the output pin A is YN.

[0087] For another example, the input pin of the logic unit where the target driving object F is located is NC (i.e., no-drive state), and the logic value of the input pin cannot be controlled, so its controllability result is NN, but the controllability result of the target driving object F is not NN, because considering that the controllability result of the data input pin B is YN, it means that its logic value 0 is controllable. Since the logic unit where the target driving object F is located is an AND gate, when any data input pin is a logic value 0, the logic value of its output pin is also 0, so it can be concluded that the controllability result of the target driving object F is YN.

[0088] In addition, if the controllability result of a certain driven object cannot be obtained through the above methods, it can be determined that the controllability result of the driven object is NN.

[0089] Figure 8 An example of an analysis method of circuit controllability according to an exemplary embodiment of the present application is shown.

[0090] Reference Figure 8 , take out an object from the current working set, determine the controllability result of the currently taken out object, and connect at least one pin or port of the currently taken out object to form at least one combination with the currently taken out object for processing, each combination consists of a driver and a receiver, specifically, the currently taken out object is a driver (i.e., the target driver object), and at least one pin or port of the currently taken out object is a receiver (i.e., the target receiving object). For example, Figure 7 There are two receivers (B and C) connected to output pin A, so two combinations AB and AC will be obtained for A.

[0091] For each combination of the currently retrieved objects, the driver's controllability result is passed to the receiver, the remaining access count of the instance where the receiver is located is -1, and it is determined whether it is possible to move forward for the instance (remaining access count < 1 means it is possible to move forward). If it is possible to move forward, all output pins of the instance are put into the current working set. When the remaining access count of the instance is < 1, it means that all input pins of the instance have been processed and the subsequent traversal can continue.

[0092] When the above processing is completed for all combinations of the currently retrieved objects, the next object is retrieved from the current working set and the above processing is performed.

[0093] As an example, a single thread processes one object at a time, while a multithreaded thread processes multiple objects at the same time. Due to the special nature of BFS, there is no problem of path intersection, and the number of remaining instance accesses is limited, so the same object will not be processed by multiple threads.

[0094] During the parallel processing process, each thread will continuously update the working set. As objects are continuously put in or taken out of the current working set, the objects in the working set may decrease or increase. Finally, when the working set is empty and all threads are idle, the entire target integrated circuit is processed and the controllability results of all related pins or ports are obtained.

[0095] When EDA tools perform fault analysis, such as the common stuck-at fault analysis, when analyzing the stuck-at-0 fault of a certain pin, its logic value 1 must be controllable before the fault can be activated and passed for inspection. At this time, the controllability result can be used for judgment. When performing observability analysis of the circuit, it is also necessary to consider the impact of the controllability result to perform logical calculations to determine whether the pin can be observed.

[0096] The method proposed in this application can analyze the controllability of the circuit efficiently and quickly, and improve the efficiency of EDA tools in checking circuit fault-related rules. On the premise of using BFS to avoid multiple analyses, the concept of controllability results is used to avoid complex calculation combinations, which greatly improves the efficiency and speed of the controllability analysis of the entire circuit.

[0097] Fig. 9 A structural block diagram showing a device for analyzing circuit controllability according to an exemplary embodiment of the present application.

[0098] The circuit controllability analysis device according to the exemplary embodiment of the present application includes: a start point determination unit 100 , a set creation unit 200 , a result determination unit 300 , and a process execution unit 400 .

[0099] Specifically, the starting point determination unit 100 is configured to determine an analysis starting point of the controllability of the target integrated circuit.

[0100] The set creation unit 200 is configured to create a working set and add the analysis starting point as a driving object to the working set.

[0101] The result determination unit 300 is configured to take out a driving object from the working set as a target driving object, and determine a controllability result of the target driving object.

[0102] The processing execution unit 400 is configured to perform preset processing for each target receiving object connected to the target driving object, wherein, after the preset processing is performed on all target receiving objects, the result determination unit 300 takes out a driving object from the working set as the target driving object and determines the controllability result of the target driving object.

[0103] The preset processing includes: obtaining the controllability result of the target receiving object according to the controllability result of the target driving object, and judging whether the controllability results of the preset type input pins of the target logic unit where the target receiving object is located have all been obtained; if all have been obtained, adding the output pins of the target logic unit as driving objects to the working set.

[0104] The controllability result of the object indicates whether the object can be controlled to be at a logical value of 0 or whether the object can be controlled to be at a logical value of 1.

[0105] As an exemplary embodiment, the result determination unit 300 and the processing execution unit 400 independently execute through each thread of multiple parallel threads: taking out a driving object from the working set as the target driving object, and determining the controllability result of the target driving object; performing preset processing on each target receiving object connected to the target driving object, wherein, after the preset processing is performed on all target receiving objects, returning to execute the taking out a driving object from the working set as the target driving object, and determining the controllability result of the target driving object.

[0106] As an exemplary embodiment, the removed drive object is no longer retained in the working set.

[0107] As an exemplary embodiment, the result determination unit 300 may be configured to: when the target driven object is not the analysis starting point, determine the controllability result of the target driven object according to the category of the logic unit where the target driven object is located.

[0108] As an exemplary embodiment, the result determination unit 300 may be configured to: determine whether the logic unit where the target driving object is located belongs to a specific category; if the logic unit belongs to the specific category, determine whether the logic unit is in a reset activation state or a set activation state; if the logic unit does not belong to the specific category, or the logic unit is not in a reset activation state or a set activation state, determine the controllability result of the target driving object based on the controllability result of the data input pin of the logic unit.

[0109] As an exemplary embodiment, the result determination unit 300 may be configured as follows: if the logic unit is not in a reset activation state or a set activation state, determining whether the type of the logic unit satisfies a preset condition; if the type of the logic unit satisfies the preset condition, taking the controllability result of the data input pin of the logic unit as the controllability result of the target driving object; if the logic unit does not belong to the specific category, or the type of the logic unit does not satisfy the preset condition, obtaining the controllability result of the target driving object through logical analysis based on the controllability result of the data input pin of the logic unit.

[0110] As an exemplary embodiment, the result determination unit 300 may be configured to: determine whether the logic unit is in a reset activation state; if the logic unit is in a reset activation state, determine the controllability result of the target driven object as follows: the target driven object can be controlled to be at a logic value of 0, and the target driven object cannot be controlled to be at a logic value of 1; if the logic unit is not in a reset activation state, determine whether the logic unit is in a set activation state; if the logic unit is in a set activation state, determine the controllability result of the target driven object as follows: the target driven object cannot be controlled to be at a logic value of 0, and the target driven object can be controlled to be at a logic value of 1.

[0111] As an exemplary embodiment, the result determination unit 300 can be configured to: determine the possible logical values ​​of each data input pin based on the controllability results of the data input pins of the logic unit where the target driving object is located; determine the possible input state combinations of the logic unit based on the possible logical values ​​of each data input pin, wherein each input state combination includes: a possible logical value of each data input pin; determine the possible logical value of the output pin of the logic unit for each input state combination that the logic unit may be in; determine the controllability result of the target driving object based on the possible logical value of the output pin of the logic unit.

[0112] As an exemplary embodiment, the result determination unit 300 may be configured to: determine a logic expression for representing the function of the logic unit; and calculate the possible logic values ​​of the output pin of the logic unit according to the logic expression for each possible input state combination of the logic unit.

[0113] As an exemplary embodiment, the result determination unit 300 may be configured to: traverse a library file, and determine a logic expression for representing a function of the logic unit in the library file according to an output pin of the logic unit.

[0114] As an exemplary embodiment, the processing execution unit 400 may be configured to: after obtaining the controllability result of the target receiving object, subtract 1 from the remaining access count of the target logic unit to update the remaining access count; if the updated remaining access count is less than 1, it is determined that all controllability results of the preset type input pins of the target logic unit have been obtained; if the updated remaining access count is greater than or equal to 1, it is determined that all controllability results of the preset type input pins of the target logic unit have not been obtained.

[0115] The initial remaining access count of the target logic unit is: the number of preset type input pins of the target logic unit.

[0116] As an exemplary embodiment, the analysis starting point may include, but is not limited to: a total input port of the target integrated circuit, an output pin of a preset type unit, and a pin and a port whose logic value is a constant value.

[0117] As an exemplary embodiment, the preset type input pin may include, but is not limited to: a data input pin connected to a general input port of the target integrated circuit or an output pin of a logic unit.

[0118] It should be understood that the specific processing performed by the circuit controllability analysis device according to the exemplary embodiment of the present application has been referred to. Figures 2 to 8The details have been described in detail and will not be repeated here.

[0119] It should be understood that each unit in the circuit controllability analysis device according to the exemplary embodiment of the present application may be implemented as a hardware component and / or a software component.

[0120] Fig.10 A structural block diagram of an electronic device according to an exemplary embodiment of the present application is shown.

[0121] Reference Fig.10 The electronic device includes: at least one memory 600 and at least one processor 700, wherein the at least one memory 600 stores a set of computer executable instructions, and when the set of computer executable instructions is executed by the at least one processor 700, the circuit controllability analysis method as described in the above exemplary embodiment is executed.

[0122] As an example, the electronic device may be a PC, a tablet device, a personal digital assistant, a smart phone, or other device capable of executing the above instruction set. Here, the electronic device is not necessarily a single electronic device, but may also be any device or circuit collection capable of executing the above instructions (or instruction sets) individually or in combination. The electronic device may also be part of an integrated control system or system manager, or may be configured as a portable electronic device interconnected with a local or remote (e.g., via wireless transmission) interface.

[0123] In an electronic device, the processor 700 may include a central processing unit (CPU), a graphics processing unit (GPU), a programmable logic device, a dedicated processor system, a microcontroller, or a microprocessor. As an example and not limitation, the processor 700 may also include an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc.

[0124] The processor 700 may execute instructions or codes stored in the memory 600, wherein the memory 600 may also store data. Instructions and data may also be sent and received over a network via a network interface device, wherein the network interface device may employ any known transmission protocol.

[0125] The memory 600 may be integrated with the processor 700, for example, by placing RAM or flash memory within an integrated circuit microprocessor or the like. In addition, the memory 600 may include a separate device, such as an external disk drive, a storage array, or any other storage device that can be used by a database system. The memory 600 and the processor 700 may be operatively coupled, or may communicate with each other, such as through an I / O port, a network connection, etc., so that the processor 700 can read files stored in the memory.

[0126] In addition, the electronic device may also include a video display (such as a liquid crystal display) and a user interaction interface (such as a keyboard, a mouse, a touch input device, etc.) All components of the electronic device may be connected to each other via a bus and / or a network.

[0127] According to an exemplary embodiment of the present application, a computer-readable storage medium storing instructions may also be provided, wherein when the instructions are executed by at least one processor, the at least one processor is prompted to perform the circuit controllability analysis method as described in the above exemplary embodiment. Examples of computer-readable storage media here include: read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disk storage, hard disk drive (HDD), solid state drive (SSD), card storage (such as, multimedia card, secure digital (SD) card or extreme digital (XD) card), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid state disk and any other device, any other device is configured to store computer programs and any associated data, data files and data structures in a non-transitory manner and provide the computer programs and any associated data, data files and data structures to a processor or computer so that the processor or computer can execute the computer program. The computer program in the above-mentioned computer-readable storage medium can be run in an environment deployed in a computer device such as a client, a host, an agent device, a server, etc. In addition, in one example, the computer program and any associated data, data files and data structures are distributed on a networked computer system, so that the computer program and any associated data, data files and data structures are stored, accessed and executed in a distributed manner by one or more processors or computers.

[0128] According to an exemplary embodiment of the present application, a computer program product may also be provided. Instructions in the computer program product may be executed by at least one processor to implement the circuit controllability analysis method as described in the above exemplary embodiment.

[0129] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the claims.

[0130] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for analyzing circuit controllability, characterized in that: include: Determine the starting point of the analysis for the controllability of the target integrated circuit; Creating a working set, and adding the analysis starting point as a driving object to the working set; Taking a driving object from the working set as a target driving object, and determining a controllability result of the target driving object; Performing a preset process on each target receiving object connected to the target driving object, wherein after the preset process is performed on all target receiving objects, returning to perform the process of taking a driving object from the working set as a target driving object and determining a controllability result of the target driving object; The preset processing includes: According to the controllability result of the target driving object, the controllability result of the target receiving object is obtained, and it is determined whether the controllability results of the preset type input pins of the target logic unit where the target receiving object is located have all been obtained; If all are obtained, adding the output pin of the target logic unit as a driving object to the working set; The controllability result of the object indicates whether the object can be controlled to be at a logic value of 0 or whether the object can be controlled to be at a logic value of 1. Among them, the specific forms of the controllability results of the object include the following four types: The object can be controlled to be at a logical value of 0 or at a logical value of 1; The object can be controlled to be at a logical value of 0, but cannot be controlled to be at a logical value of 1; The object can be controlled to be at a logical value of 1, but cannot be controlled to be at a logical value of 0; The object cannot be controlled to be at a logical value of 0, nor can the object be controlled to be at a logical value of 1.

2. The analysis method according to claim 1, characterized in that Executed independently by each of multiple parallel threads: The step of taking a driving object from the working set as a target driving object and determining a controllability result of the target driving object; The step of performing a preset process on each target receiving object connected to the target driving object, wherein after the preset process is performed on all target receiving objects, returning to perform the step of taking a driving object from the working set as a target driving object and determining a controllability result of the target driving object; The removed drive object is no longer retained in the working set.

3. The analysis method according to claim 1, characterized in that When the target driven object is not the analysis starting point, the determining of the controllability result of the target driven object includes: A controllability result of the target driven object is determined according to the category of the logic unit where the target driven object is located.

4. The analysis method according to claim 3, characterized in that The step of determining the controllability of the target driven object according to the type of the logic unit where the target driven object is located comprises: Determining whether the logic unit where the target drive object is located belongs to a specific category; If the logic unit belongs to the specific category, determining whether the logic unit is in a reset active state or a set active state; If the logic unit does not belong to the specific category, or the logic unit is not in a reset active state or a set active state, the controllability result of the target driving object is determined based on the controllability result of the data input pin of the logic unit.

5. The analysis method according to claim 4, characterized in that If the logic unit does not belong to the specific category, or the logic unit is not in a reset activation state or a set activation state, determining the controllability result of the target driving object based on the controllability result of the data input pin of the logic unit includes: If the logic unit is not in a reset activation state or a set activation state, determining whether the type of the logic unit meets a preset condition; If the type of the logic unit meets the preset condition, the controllability result of the data input pin of the logic unit is used as the controllability result of the target driving object; If the logic unit does not belong to the specific category, or the type of the logic unit does not meet the preset condition, the controllability result of the target drive object is obtained through logic analysis based on the controllability result of the data input pin of the logic unit.

6. The analysis method according to claim 4, characterized in that The determining whether the logic unit is in a reset active state or a set active state comprises: determining whether the logic unit is in a reset active state; If the logic unit is in a reset activation state, the controllability of the target drive object is determined as follows: the target drive object can be controlled to be at a logic value of 0, and the target drive object cannot be controlled to be at a logic value of 1; If the logic unit is not in a reset active state, determining whether the logic unit is in a set active state; If the logic unit is in a set activation state, the controllability of the target drive object is determined as follows: the target drive object cannot be controlled to be at a logic value of 0, and the target drive object can be controlled to be at a logic value of 1.

7. The analysis method according to claim 5, characterized in that The controllability result of the target driving object obtained by logic analysis based on the controllability result of the data input pin of the logic unit includes: Based on the controllability results of the respective data input pins of the logic unit, determining the possible logic values ​​of the respective data input pins; Based on the possible logic values ​​of the respective data input pins, determining the possible input state combinations of the logic unit, wherein each input state combination includes: a possible logic value of the respective data input pins; For each possible input state combination of the logic unit, determining possible logic values ​​of the output pin of the logic unit; Based on the possible logic values ​​of the output pins of the logic unit, a controllability result of the target drive object is determined.

8. The analysis method according to claim 7, characterized in that The determining, for each possible input state combination of the logic unit, possible logic values ​​of the output pin of the logic unit comprises: determining a logic expression for representing the function of the logic unit; For each possible input state combination of the logic unit, the possible logic value of the output pin of the logic unit is calculated according to the logic expression.

9. The analysis method according to claim 8, characterized in that The determining of a logical expression for representing the function of the logic unit comprises: The library file is traversed, and a logic expression for representing the function of the logic unit is determined in the library file according to the output pin of the logic unit.

10. The analysis method according to claim 1, characterized in that The step of judging whether all controllability results of the preset type input pins of the target logic unit where the target receiving object is located have been obtained includes: After obtaining the controllability result of the target receiving object, subtract 1 from the remaining access count of the target logical unit to update the remaining access count; If the updated remaining access count is less than 1, it is determined that all controllability results of the preset type input pins of the target logic unit have been obtained; If the updated remaining access count is greater than or equal to 1, it is determined that the controllability results of the preset type input pins of the target logic unit are not all obtained; The initial remaining access times of the target logic unit is: the number of preset type input pins of the target logic unit.

11. The analysis method according to claim 1, characterized in that The analysis starting point includes: the total input port of the target integrated circuit, the output pin of the preset type unit, and the pin and port whose logic value is a constant value; and / or, The preset type input pins include: data input pins connected to a general input port of the target integrated circuit or an output pin of a logic unit.

12. A circuit controllability analysis device, characterized in that: include: a starting point determination unit configured to determine an analysis starting point of controllability of a target integrated circuit; A set creation unit is configured to create a working set and add the analysis starting point as a driving object to the working set; a result determination unit configured to take a driving object from the working set as a target driving object and determine a controllability result of the target driving object; a processing execution unit, configured to execute a preset processing for each target receiving object connected to the target driving object, wherein after the preset processing is executed for all target receiving objects, the processing returns to execute the process of taking a driving object from the working set as a target driving object and determining a controllability result of the target driving object; The preset processing includes: According to the controllability result of the target driving object, the controllability result of the target receiving object is obtained, and it is determined whether the controllability results of the preset type input pins of the target logic unit where the target receiving object is located have all been obtained; If all are obtained, adding the output pin of the target logic unit as a driving object to the working set; The controllability result of the object indicates whether the object can be controlled to be at a logic value of 0 or whether the object can be controlled to be at a logic value of 1. Among them, the specific forms of the controllability results of the object include the following four types: The object can be controlled to be at a logical value of 0 or at a logical value of 1; The object can be controlled to be at a logical value of 0, but cannot be controlled to be at a logical value of 1; The object can be controlled to be at a logical value of 1, but cannot be controlled to be at a logical value of 0; The object cannot be controlled to be at a logical value of 0, nor can the object be controlled to be at a logical value of 1.

13. A computer-readable storage medium storing instructions, characterized in that: When the instructions are executed by a processor of an electronic device, the electronic device is enabled to execute the circuit controllability analysis method according to any one of claims 1 to 11.

14. An electronic device, characterized in that: The electronic device comprises: at least one processor; at least one memory storing computer executable instructions, When the computer executable instructions are executed by the at least one processor, the at least one processor is prompted to execute the circuit controllability analysis method according to any one of claims 1 to 11.

15. A computer program product comprising computer executable instructions, characterized in that: When the computer executable instructions are executed by at least one processor, the circuit controllability analysis method according to any one of claims 1 to 11 is implemented.

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