VCSEL chip etching process quality control method and device

Abstract

The present application provides a VCSEL chip etching process quality control method and device, which relates to the field of semiconductor manufacturing technology, including: receiving chip etching tasks according to the chip production end; aligning and associating chip etching process factors according to the etching target layer information corresponding to the chip etching target layer, and establishing a chip etching control alignment space; making etching decisions on the chip etching control alignment space according to the chip etching quality constraints, and generating a chip etching decision space that meets the predetermined etching decision capacity; performing optimization analysis on the chip etching decision space according to the chip etching quality fitness function, and obtaining a chip etching optimization process; etching the chip to be etched according to the chip etching optimization process. The present application solves the technical problem that the existing process uses fixed process parameter settings, which makes it difficult to flexibly adjust the etching process according to the differences between different chips and etching layers, resulting in poor consistency of etching effects, and improves the accuracy and consistency of chip etching.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method and device for controlling the quality of a VCSEL chip etching process. Background Art

[0002] In the field of semiconductor optoelectronics, VCSEL (vertical cavity surface emitting laser) chips have become a hot topic of research due to their excellent performance and broad application prospects. Etching technology, as a key step in VCSEL chip manufacturing, directly affects the performance and yield of the chip. Existing VCSEL chip etching process control methods mostly rely on preset parameters and operator experience, and control the etching process by setting parameters such as etching time, power, and gas flow. However, the static setting of parameters is difficult to cope with the differences between different chips and etching layers, resulting in poor consistency in etching effects; on the other hand, the complex coupling relationship between parameters makes process optimization difficult, and it is difficult to achieve precise control of the etching process, resulting in large fluctuations in etching quality, affecting the yield and performance of VCSEL chips. Summary of the invention

[0003] The present application provides a method and device for VCSEL chip etching process quality control, which solves the technical problem that the existing etching process control adopts fixed process parameter settings, which makes it difficult to flexibly adjust the etching process according to the differences between different chips and etching layers, resulting in poor consistency of etching effects, and achieves the technical effect of improving the accuracy of VCSEL chip etching and product consistency.

[0004] In view of the above problems, on the one hand, the present application provides a VCSEL chip etching process quality control method, the method comprising: receiving a VCSEL chip etching task according to a chip production end, wherein the VCSEL chip etching task includes a VCSEL chip to be etched, and a chip etching target layer and a chip etching quality constraint corresponding to the VCSEL chip to be etched; performing registration association on VCSEL chip etching process factors according to etching target layer information corresponding to the chip etching target layer, and establishing a VCSEL chip etching control registration space; performing etching decisions on the VCSEL chip etching control registration space according to the chip etching quality constraint based on the etching target layer information, and generating a VCSEL chip etching decision space that meets a predetermined etching decision capacity; performing optimization analysis on the VCSEL chip etching decision space according to a chip etching quality fitness function, and obtaining a VCSEL chip etching optimization process; and etching the VCSEL chip to be etched according to the VCSEL chip etching optimization process.

[0005] On the other hand, the present application also provides a VCSEL chip etching process quality control device, the device comprising: a task receiving unit, the task receiving unit is used to receive a VCSEL chip etching task according to a chip production end, wherein the VCSEL chip etching task includes a VCSEL chip to be etched, and a chip etching target layer and a chip etching quality constraint corresponding to the VCSEL chip to be etched; a registration association unit, the registration association unit is used to perform registration association on the VCSEL chip etching process factors according to the etching target layer information corresponding to the chip etching target layer, and establish a VCSEL chip etching control registration space; An etching decision unit, wherein the etching decision unit is used to make an etching decision on the VCSEL chip etching control registration space based on the etching target layer information and according to the chip etching quality constraint, and generate a VCSEL chip etching decision space that meets a predetermined etching decision capacity; a process optimization unit, wherein the process optimization unit is used to perform an optimization analysis on the VCSEL chip etching decision space according to a chip etching quality fitness function, and obtain a VCSEL chip etching optimization process; and an optimization process execution unit, wherein the optimization process execution unit is used to etch the VCSEL chip to be etched according to the VCSEL chip etching optimization process.

[0006] One or more technical solutions provided in this application have at least the following technical effects or advantages:

[0007] According to the chip production end, a VCSEL chip etching task is received, wherein the VCSEL chip etching task includes a VCSEL chip to be etched, and a chip etching target layer and a chip etching quality constraint corresponding to the VCSEL chip to be etched. This step provides specific goals and standards for the subsequent process parameter setting and clarifies the process control orientation. According to the etching target layer information corresponding to the chip etching target layer, the VCSEL chip etching process factors are aligned and associated, and a VCSEL chip etching control alignment space is established. This step improves the pertinence and applicability of the process parameters and provides a structured parameter space for subsequent optimization decisions. Based on the etching target layer information, an etching decision is made on the VCSEL chip etching control alignment space according to the chip etching quality constraint, and a VCSEL chip etching decision space that meets the predetermined etching decision capacity is generated. This step realizes the optimal combination of process parameters to ensure that the etching process meets both the quality constraints and the best efficiency. According to the chip etching quality fitness function, the VCSEL chip etching decision space is optimized and analyzed to obtain a VCSEL chip etching optimization process. This step determines the optimal VCSEL chip etching process from the decision space to ensure that the etching quality reaches the highest standard. The VCSEL chip to be etched is etched according to the VCSEL chip etching optimization process.

[0008] In summary, this application achieves precise control of the VCSEL chip etching process through gradually refined control strategies and optimization algorithms, ensures that the etching process parameters match the requirements of specific chips, and significantly improves the accuracy of VCSEL chip etching and product consistency.

[0009] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram of a process flow of a VCSEL chip etching process quality control method provided in an embodiment of the present application;

[0011] Figure 2 A schematic diagram of a flow chart of generating a VCSEL chip etching decision space that meets a predetermined etching decision capacity in a VCSEL chip etching process quality control method provided in an embodiment of the present application;

[0012] Figure 3 A schematic diagram of the structure of a VCSEL chip etching process quality control device provided in an embodiment of the present application.

[0013] Explanation of the reference numerals: task receiving unit 10 , registration association unit 20 , etching decision unit 30 , process optimization unit 40 , and optimization process execution unit 50 . DETAILED DESCRIPTION

[0014] The embodiments of the present application provide a method and device for controlling the quality of VCSEL chip etching process, thereby solving the technical problem that the existing etching process control uses fixed process parameter settings, which makes it difficult to flexibly adjust the etching process according to the differences between different chips and etching layers, resulting in poor consistency of etching effects, and achieves the technical effect of improving the accuracy of VCSEL chip etching and product consistency.

[0015] Embodiment 1, as Figure 1 As shown, the embodiment of the present application provides a method for controlling the quality of a VCSEL chip etching process, the method comprising:

[0016] Step S1: receiving a VCSEL chip etching task from a chip production end, wherein the VCSEL chip etching task includes a VCSEL chip to be etched, and a chip etching target layer and a chip etching quality constraint corresponding to the VCSEL chip to be etched.

[0017] Specifically, the chip production end, that is, the chip manufacturing production line, includes the entire production process from raw material input to finished product output. After receiving the production demand, the chip production end issues a task instruction, namely the VCSEL chip etching task. The instruction contains the VCSEL chip to be etched, the etching target layer, and the etching quality constraints. The VCSEL chip to be etched includes the basic information of the chip to be etched, such as materials and structures. The chip etching target layer refers to a specific layer in the chip stacking structure, such as an oxide layer, a metal layer, etc. The goal of etching is to remove or modify this layer to form the desired microstructure. Chip etching quality constraints include etching depth, edge profile clarity, surface roughness, etc., which are important indicators for evaluating whether the etching process is successful. For example, a VCSEL chip etching task requires etching a batch of VCSEL chips to form a specific microcavity structure. The task contains detailed information about the batch of chips. The chip material is a gallium arsenide (GaAs) substrate, and the target layer is an aluminum oxide (Al2O3) layer 100 nanometers below the chip surface. The etching quality constraints include that the etching depth needs to be precisely controlled at 50 nanometers, the right-angle deviation of the edge profile is less than 5 degrees, and the surface roughness needs to be less than 1 nanometer.

[0018] Step S1 clarifies the detailed information of the chip etching process and provides clear goals and standards for subsequent optimization of process parameters.

[0019] Step S2: performing registration association on the VCSEL chip etching process factors according to the etching target layer information corresponding to the chip etching target layer, and establishing the VCSEL chip etching control registration space.

[0020] Specifically, the chip etching target layer information includes the material, position, thickness, etc. of the target layer, which directly determines the difficulty and requirements of etching. VCSEL chip etching process factors are process variables that affect the etching process, such as etching solution formula, etching time and etching temperature. According to the chip etching target layer information, that is, the material, thickness and position of the target layer, the appropriate etching process factors are automatically or manually selected, and these set process factors are aligned and associated with the target layer information to generate an etching control alignment space. The etching control alignment space is a set of all possible etching process parameter combinations. By aligning the etching target layer information with the etching process factors, all possible parameter combinations are generated, providing a basis for the subsequent decision space generation.

[0021] Step S3: Based on the etching target layer information and according to the chip etching quality constraint, an etching decision is made on the VCSEL chip etching control registration space to generate a VCSEL chip etching decision space that meets a predetermined etching decision capacity.

[0022] Specifically, the etching decision space is a set of process parameter combinations that can meet the etching quality constraints after screening and optimization. The predetermined etching decision capacity is the number of parameter combinations in the decision space, which needs to be sufficient to ensure the flexibility of the process, but not too much to avoid wasting computing resources. First, based on the chip etching quality constraints, the simulation tool is used to evaluate the different etching parameter combinations in the VCSEL chip etching control registration space, and the process parameter combinations that meet the chip etching quality constraints are screened out. For example, if the etching quality constraints require an etching depth of 50 nanometers and a surface roughness of less than 1 nanometer, then all process parameter combinations that can meet these standards will be retained. After screening, an etching decision space containing a predetermined etching decision capacity is formed. All process parameter combinations in this space can meet the predetermined quality standards, ensuring the efficiency and accuracy of the etching process.

[0023] Step S4: performing optimization analysis on the VCSEL chip etching decision space according to the chip etching quality fitness function to obtain a VCSEL chip etching optimization process.

[0024] Specifically, the chip etching quality fitness function is a mathematical model used to quantify the relationship between etching process parameters and etching quality. It converts etching quality constraints into specific numerical indicators to help evaluate the pros and cons of different parameter combinations. The VCSEL chip etching optimization process is to find the best etching process parameters from the decision space through optimization analysis, which can optimize the etching quality requirements. First, a fitness function is defined based on etching quality constraints, such as etching depth, edge profile, surface roughness, etc. This function maps the process parameters to a numerical value, and the higher the value means the better the etching quality. Select an optimization algorithm, such as genetic algorithm (GA), particle swarm optimization (PSO) or simulated annealing, to perform optimization analysis on the parameter combination in the decision space. The algorithm will automatically iterate, evaluate each set of parameters according to the fitness function, and gradually approach the optimal solution. After multiple rounds of iterative optimization, a set of process parameter combinations that can maximize the fitness function is determined, namely the VCSEL chip etching optimization process.

[0025] Step S4 further optimizes the process parameters through optimization analysis, ensuring that the etching process can accurately meet the quality requirements, providing a strong guarantee for the high-precision manufacturing of VCSEL chips.

[0026] Step S5: etching the VCSEL chip to be etched according to the VCSEL chip etching optimization process.

[0027] Specifically, the optimal process parameters determined in step S4, including the etching solution formula, etching time, etching temperature and other information, are input into the etching equipment for setting. The VCSEL chip to be etched is placed on the workbench of the etching equipment, and the alignment system of the equipment ensures that the chip is accurately aligned with the etching area to prepare for etching. Start the etching equipment and perform etching according to the set process parameters. The equipment will accurately control the etching process according to the parameters of the optimization process to ensure that the etching depth, selectivity and surface quality meet the requirements. After etching is completed, the chip is quality checked, including etching depth, edge profile, surface roughness, etc., to ensure that the preset etching quality standards are met. If any non-compliance is found, this information is fed back to the optimization algorithm as input for subsequent optimization. The etching quality of each VCSEL chip is ensured by the precise execution of step S5.

[0028] Furthermore, step S2 of the embodiment of the present application further includes:

[0029] The VCSEL chip etching process factors include etching solution formula, etching time and etching temperature; judging whether the chip etching target layer is a single etching target layer; if the chip etching target layer is a single etching target layer, taking the etching target layer information as the etching process retrieval constraint, and taking the VCSEL chip etching process factor as the etching process retrieval target; performing etching control record retrieval on the chip production end based on the etching process retrieval constraint and the etching process retrieval target to obtain an etching control scheme retrieval set; performing trigger interval identification on the etching control scheme retrieval set based on the VCSEL chip etching process factor to obtain the VCSEL chip etching control registration space.

[0030] Specifically, in the etching process of VCSEL chips, the etching solution formula, etching time and etching temperature are three key process factors. The etching solution formula defines the type and proportion of chemicals used in the etching process. Different etching solution formulas are suitable for etching different materials. For example, for the etching of GaAs-based VCSELs, chloride-containing etching solutions may be used to achieve high selectivity and fast etching. Etching time refers to the length of time the etching process lasts, which is directly related to the etching rate and etching depth. Too long etching time may lead to over-etching, while too short time may lead to incomplete etching. Etching temperature, that is, the ambient temperature during the etching process, has a significant effect on the etching rate and the chemical activity of the etching solution. Generally speaking, an increase in temperature will increase the etching rate, but it may also increase the non-selectivity of the etching process, resulting in surface damage or increased sidewall roughness. The choice of etching temperature requires a balance between improving etching efficiency and maintaining etching quality.

[0031] First, determine whether the etching target layer is a single layer, that is, whether the etching operation is only for a specific layer on the chip, rather than multiple layers at the same time. If so, use the etching target layer information as a constraint condition and the etching process factor as a retrieval target to retrieve historical etching control records, find etching control schemes under similar conditions, and obtain an etching control scheme retrieval set. The etching control scheme retrieval set is a set of etching control schemes that meet current process requirements retrieved from historical records. Analyze the retrieved etching control scheme retrieval set to determine the trigger interval of the etching process factor, that is, the effective range of the etching process factor. Within these intervals, the etching process can be effectively controlled. Based on the trigger interval identification results, an etching control registration space is formed, that is, all valid process parameter combinations.

[0032] For example, assume that the etching target layer is a single 100nm thick aluminum oxide layer located 200nm below the chip surface. First, determine that this is indeed a single etching target layer, and then use the properties and location information of the aluminum oxide layer as retrieval constraints, and the etching solution formula, etching time and etching temperature as retrieval targets to retrieve etching control solutions under similar conditions from historical etching control records. The retrieved solutions use HF solutions of different concentrations as etching solutions, with etching times between 8 and 12 minutes and etching temperatures between 20°C and 30°C. Based on these results, an etching control registration space containing all valid process parameter combinations is formed.

[0033] Furthermore, step S2 of the embodiment of the present application further includes:

[0034] If the chip etching target layer is not a single etching target layer, the etching target layer information is disassembled according to the hierarchical structure of the chip etching target layer to obtain multi-level etching target layer parameters; based on the multi-level etching target layer parameters, the VCSEL chip etching process factors are respectively aligned and associated to obtain a multi-layer etching control alignment space; based on the multi-layer etching control alignment space, the VCSEL chip etching control alignment space is generated.

[0035] Specifically, when the chip etching target layer is multi-layered rather than a single layer, the etching target layer information is decomposed into multi-level etching target layer parameters based on the hierarchical structure of the target layer, and an independent set of etching target parameters is established for each layer. For the etching target layer parameters of each layer, they are aligned and associated with the VCSEL chip etching process factors, and the etching solution formula, etching time and etching temperature of each layer are analyzed to ensure that the etching parameters of each layer match the characteristics of the target layer, and to establish the etching control alignment space of each layer. The etching control alignment spaces of each layer are summarized and integrated to generate a comprehensive etching control alignment space applicable to the entire chip etching process to ensure the continuity and consistency of the etching process.

[0036] For example, assume that the etching target layer includes a 100nm thick SiO2 layer (located at a depth of 200nm) and a 50nm thick Si3N4 layer (immediately below the SiO2 layer). First, the etching target information of the two layers is disassembled to obtain their respective material, thickness and position information. Then, the SiO2 layer and the Si3N4 layer are respectively aligned with the etching solution formula, etching time and etching temperature to form their respective etching control alignment spaces. For example, the SiO2 layer is suitable for etching with HF solution, with a time range of 5 to 10 minutes and a temperature between 20°C and 25°C; while the Si3N4 layer requires a mixture of HNO3 and HF, with a time range of 8 to 12 minutes and a temperature between 25°C and 30°C. Finally, the two etching control alignment spaces are integrated to form a comprehensive etching control alignment space for the entire chip etching process.

[0037] Further, such as Figure 2 As shown, step S3 of the embodiment of the present application also includes:

[0038] Step S31: Based on the etching target layer information, an etching decision is made according to the VCSEL chip etching control registration space to obtain a VCSEL chip etching solution space.

[0039] Step S32: extracting a first VCSEL chip etching scheme according to the VCSEL chip etching scheme space.

[0040] Step S33: Based on the etching target layer information and the first VCSEL chip etching scheme, a first etching quality prediction result is obtained according to an etching quality prediction model.

[0041] Step S34: determining whether the first etching quality prediction result satisfies the chip etching quality constraint, wherein the chip etching quality constraint includes etching sidewall roughness constraint, etching accuracy constraint and etching balance constraint.

[0042] Step S35: If the first etching quality prediction result meets the chip etching quality constraint, the first VCSEL chip etching scheme is recorded as a first VCSEL chip etching decision, and the first VCSEL chip etching decision is added to the VCSEL chip etching decision space.

[0043] Step S36: If the first etching quality prediction result does not meet the chip etching quality constraint, the first VCSEL chip etching solution is eliminated.

[0044] Step S37: continuing to optimize the VCSEL chip etching solution space according to the chip etching quality constraint and the etching quality prediction model until the etching decision capacity of the VCSEL chip etching decision space meets the predetermined etching decision capacity.

[0045] Specifically, for each etching target layer, according to its material and thickness, a suitable etching solution formula and etching conditions are selected from the registration space to generate multiple possible etching schemes, which are summarized to obtain an initial etching scheme space. The etching scheme space is a set of possible etching schemes generated based on the etching control registration space.

[0046] A scheme is randomly extracted from the etching scheme space, namely the first VCSEL chip etching scheme, and its etching quality is predicted using the etching quality prediction model. The etching quality prediction model is used to predict the etching quality under a specific etching scheme. For a specific etching scheme, the etching quality prediction model outputs the predicted values ​​of the roughness, precision and balance of the etching sidewall under the scheme. The prediction result is compared with the etching quality constraint. If the prediction result meets the quality constraint, the first VCSEL chip etching scheme is confirmed to be valid, marked as the first VCSEL chip etching decision and added to the etching decision space; if not, the scheme is eliminated. If the decision capacity of the current etching decision space does not meet the predetermined requirements, the above process is repeated until the capacity of the decision space meets the requirements.

[0047] Step S3 ensures that the etching scheme can meet the etching quality requirements with high precision through the execution of the above sub-steps, and provides a selection basis for the subsequent etching scheme optimization.

[0048] Furthermore, step S33 of the embodiment of the present application further includes:

[0049] The etching quality prediction model includes an input layer, an etching sidewall roughness prediction layer, an etching accuracy prediction layer, an etching balance prediction layer and an output layer; based on the etching target layer information and the first VCSEL chip etching scheme, according to the etching sidewall roughness prediction layer, a first predicted etching sidewall roughness is obtained; based on the etching target layer information and the first VCSEL chip etching scheme, according to the etching accuracy prediction layer, a first predicted etching accuracy is obtained; based on the etching target layer information and the first VCSEL chip etching scheme, according to the etching balance prediction layer, a first predicted etching balance is obtained; based on the first predicted etching sidewall roughness, the first predicted etching accuracy and the first predicted etching balance, according to the output layer, the first etching quality prediction result is output.

[0050] Specifically, the etching quality prediction model is a multi-layer neural network model used to predict key quality indicators in the etching process, including an input layer, an etching sidewall roughness prediction layer, an etching accuracy prediction layer, an etching balance prediction layer and an output layer. The input layer is used to receive input data, including etching target layer information and VCSEL chip etching scheme; the etching sidewall roughness prediction layer is used to predict the roughness of the sidewall during the etching process; the etching accuracy prediction layer is used to predict the accuracy of the etching depth and shape; the etching balance prediction layer is used to predict the uniformity of material removal during the etching process; the output layer is used to output the final prediction result, that is, the etching quality prediction result.

[0051] The etching quality prediction model can be built and trained through deep learning frameworks such as TensorFlow or PyTorch. First, a large amount of etching process data needs to be collected, including etching process parameters, etching target layer information, and actual etching quality results (including specific etching sidewall roughness, etching accuracy, and etching balance). Then, a multi-layer neural network is selected as the initial model architecture, and the model is trained using the collected data. During the training process, the model learns how to predict the etching quality based on the input features by continuously adjusting its internal parameters to minimize the prediction error. This step requires multiple iterations to optimize the model performance. The generalization ability of the model is tested on independent validation sets and test sets to evaluate the accuracy and reliability of the model. According to the results of validation and testing, the model is adjusted and optimized until the model converges to obtain a trained etching quality prediction model for predicting the etching quality of the VCSEL chip etching solution.

[0052] Taking the first VCSEL chip etching scheme as an example, the etching target layer information and the first VCSEL chip etching scheme are input into the input layer of the etching quality prediction model. Then, the etching quality prediction model predicts the etching sidewall roughness, etching accuracy and etching balance through the etching sidewall roughness prediction layer, etching accuracy prediction layer and etching balance prediction layer. Finally, the etching quality prediction model summarizes these prediction results into the output layer and outputs the first etching quality prediction result.

[0053] Through the above steps, the etching quality prediction model accurately predicts the etching quality of the etching scheme and provides a scientific basis for etching decision-making.

[0054] Furthermore, step S4 of the embodiment of the present application also includes:

[0055] According to the VCSEL chip etching decision space, extract the kth etching decision, where k is a positive integer; perform etching quality fitness analysis on the kth etching decision based on the chip etching quality fitness function to obtain the kth chip etching quality fitness; according to the VCSEL chip etching decision space, extract the k+1th etching decision, and calculate the k+1th chip etching quality fitness according to the chip etching quality fitness function; based on the kth chip etching quality fitness and the k+1th chip etching quality fitness, perform current etching quality fitness optimization on the kth etching decision and the k+1th etching decision to determine the current winning etching quality fitness and the current winning etching decision; based on the current winning etching quality fitness, perform iterative optimization on the current winning etching decision according to the chip etching quality fitness function and the VCSEL chip etching decision space, until the number of iterative optimizations meets the iterative optimization number threshold, and output the VCSEL chip etching optimization process.

[0056] Specifically, the kth etching decision is extracted from the etching decision space, where k is a positive integer, and the kth chip etching quality fitness of the kth etching decision is calculated by the defined etching quality fitness function. Through an optimization algorithm, such as a genetic algorithm, a particle swarm optimization, etc., the next decision, i.e., the k+1th etching decision, is extracted, and its quality fitness, i.e., the k+1th chip etching quality fitness, is calculated. The fitness of the two decisions is compared, and the larger value of the two is taken as the current winning etching quality fitness, and the corresponding etching decision is taken as the current winning etching decision. Then, iterative optimization is continued in the etching decision space, and the next decision is extracted for chip etching quality fitness calculation and comparison until the preset iterative optimization number threshold is met. The iterative optimization number threshold is a pre-set number threshold for the iterative optimization process. When the iterative optimization number reaches the iterative optimization number threshold, the optimization is stopped, and the current winning etching decision is output as the VCSEL chip etching optimization process.

[0057] Through this process, step S4 can determine the optimal etching decision from the etching decision space through iterative optimization, thereby ensuring that the final etching process achieves the best quality.

[0058] Furthermore, the chip etching quality fitness function described in the embodiment of the present application is:

[0059] .

[0060] Among them, EQF represents the chip etching quality fitness, γ represents the predetermined etching quality fitness analysis factor, 0<γ<1, EQD represents the predicted etching sidewall roughness, QDO represents the expected etching sidewall roughness, EQA represents the predicted etching accuracy, QAO represents the expected etching accuracy, EQS represents the predicted etching balance, and QSO represents the expected etching balance.

[0061] Specifically, the chip etching quality fitness function comprehensively considers three key indicators, namely, etching sidewall roughness, etching accuracy and etching balance, to quantitatively evaluate the chip etching quality. By comparing the difference between the predicted value and the expected value, it provides a fitness score for the etching process to help optimize the etching process. The higher the EQF value, the closer the etching quality is to the expected value and the better the etching process is. The parameter γ is used to adjust the sensitivity of the fitness score to ensure that the fitness score remains sufficiently sensitive to the difference in etching quality. EQD, EQA and EQS respectively characterize the predicted etching sidewall roughness, predicted etching accuracy and predicted etching balance, which are calculated by the etching quality prediction model. QDO, QAO and QSO respectively characterize the expected etching sidewall roughness, expected etching accuracy and expected etching balance, which are determined based on the requirements and standards of the manufacturing process.

[0062] In summary, the VCSEL chip etching process quality control method provided in the embodiment of the present application has the following technical effects:

[0063] According to the chip production end, a VCSEL chip etching task is received, wherein the VCSEL chip etching task includes a VCSEL chip to be etched, and a chip etching target layer and a chip etching quality constraint corresponding to the VCSEL chip to be etched. This step provides specific goals and standards for the subsequent process parameter setting and clarifies the process control orientation. According to the etching target layer information corresponding to the chip etching target layer, the VCSEL chip etching process factors are aligned and associated, and a VCSEL chip etching control alignment space is established. This step improves the pertinence and applicability of the process parameters and provides a structured parameter space for subsequent optimization decisions. Based on the etching target layer information, an etching decision is made on the VCSEL chip etching control alignment space according to the chip etching quality constraint, and the etching quality of the VCSEL chip etching solution is predicted according to the etching quality prediction model, and a VCSEL chip etching decision space that meets the predetermined etching decision capacity is generated. This step realizes the optimal combination of process parameters to ensure that the etching process meets both quality constraints and achieves optimal efficiency. According to the chip etching quality fitness function, the VCSEL chip etching decision space is optimized and analyzed to obtain the VCSEL chip etching optimization process. This step determines the optimal VCSEL chip etching process from the decision space to ensure that the etching quality reaches the highest standard. The VCSEL chip to be etched is etched according to the VCSEL chip etching optimization process.

[0064] In general, the embodiments of the present application achieve precise control of the VCSEL chip etching process through gradually refined control strategies and optimization algorithms, ensuring that the etching process parameters match the requirements of specific chips, and significantly improving the accuracy of VCSEL chip etching and product consistency.

[0065] Embodiment 2, as Figure 3 As shown, an embodiment of the present application provides a VCSEL chip etching process quality control device, the device comprising:

[0066] The task receiving unit 10 is used to receive a VCSEL chip etching task according to a chip production end, wherein the VCSEL chip etching task includes a VCSEL chip to be etched, and a chip etching target layer and a chip etching quality constraint corresponding to the VCSEL chip to be etched.

[0067] The registration and association unit 20 is used to perform registration and association on the VCSEL chip etching process factors according to the etching target layer information corresponding to the chip etching target layer, and establish the VCSEL chip etching control registration space.

[0068] The etching decision unit 30 is used to make an etching decision on the VCSEL chip etching control registration space based on the etching target layer information and the chip etching quality constraint, and generate a VCSEL chip etching decision space that meets a predetermined etching decision capacity.

[0069] The process optimization unit 40 is used to perform optimization analysis on the VCSEL chip etching decision space according to the chip etching quality fitness function to obtain the VCSEL chip etching optimization process.

[0070] The optimization process execution unit 50 is used to etch the VCSEL chip to be etched according to the VCSEL chip etching optimization process.

[0071] Furthermore, the registration association unit 20 in the embodiment of the present application is also used to perform the following steps:

[0072] The VCSEL chip etching process factors include etching solution formula, etching time and etching temperature; judging whether the chip etching target layer is a single etching target layer; if the chip etching target layer is a single etching target layer, taking the etching target layer information as the etching process retrieval constraint, and taking the VCSEL chip etching process factor as the etching process retrieval target; performing etching control record retrieval on the chip production end based on the etching process retrieval constraint and the etching process retrieval target to obtain an etching control scheme retrieval set; performing trigger interval identification on the etching control scheme retrieval set based on the VCSEL chip etching process factor to obtain the VCSEL chip etching control registration space.

[0073] Furthermore, the registration association unit 20 in the embodiment of the present application is also used to perform the following steps:

[0074] If the chip etching target layer is not a single etching target layer, the etching target layer information is disassembled according to the hierarchical structure of the chip etching target layer to obtain multi-level etching target layer parameters; based on the multi-level etching target layer parameters, the VCSEL chip etching process factors are respectively aligned and associated to obtain a multi-layer etching control alignment space; based on the multi-layer etching control alignment space, the VCSEL chip etching control alignment space is generated.

[0075] Furthermore, the etching decision unit 30 in the embodiment of the present application is also used to perform the following steps:

[0076] Based on the etching target layer information, an etching decision is made according to the VCSEL chip etching control registration space to obtain a VCSEL chip etching solution space; according to the VCSEL chip etching solution space, a first VCSEL chip etching solution is extracted; based on the etching target layer information and the first VCSEL chip etching solution, a first etching quality prediction result is obtained according to an etching quality prediction model; it is judged whether the first etching quality prediction result meets the chip etching quality constraint, wherein the chip etching quality constraint includes an etching sidewall roughness constraint, an etching accuracy constraint, and an etching balance constraint; if the first etching quality prediction result satisfies the chip etching quality constraint, the etching quality constraint satisfies the chip etching quality constraint; If the etching quality prediction result satisfies the chip etching quality constraint, the first VCSEL chip etching scheme is recorded as a first VCSEL chip etching decision, and the first VCSEL chip etching decision is added to the VCSEL chip etching decision space; if the first etching quality prediction result does not meet the chip etching quality constraint, the first VCSEL chip etching scheme is eliminated; and the VCSEL chip etching scheme space is continuously optimized according to the chip etching quality constraint and the etching quality prediction model until the etching decision capacity of the VCSEL chip etching decision space meets the predetermined etching decision capacity.

[0077] Furthermore, the etching decision unit 30 in the embodiment of the present application is also used to perform the following steps:

[0078] The etching quality prediction model includes an input layer, an etching sidewall roughness prediction layer, an etching accuracy prediction layer, an etching balance prediction layer and an output layer; based on the etching target layer information and the first VCSEL chip etching scheme, according to the etching sidewall roughness prediction layer, a first predicted etching sidewall roughness is obtained; based on the etching target layer information and the first VCSEL chip etching scheme, according to the etching accuracy prediction layer, a first predicted etching accuracy is obtained; based on the etching target layer information and the first VCSEL chip etching scheme, according to the etching balance prediction layer, a first predicted etching balance is obtained; based on the first predicted etching sidewall roughness, the first predicted etching accuracy and the first predicted etching balance, according to the output layer, the first etching quality prediction result is output.

[0079] Furthermore, the process optimization unit 40 in the embodiment of the present application is also used to perform the following steps:

[0080] According to the VCSEL chip etching decision space, extract the kth etching decision, where k is a positive integer; perform etching quality fitness analysis on the kth etching decision based on the chip etching quality fitness function to obtain the kth chip etching quality fitness; according to the VCSEL chip etching decision space, extract the k+1th etching decision, and calculate the k+1th chip etching quality fitness according to the chip etching quality fitness function; based on the kth chip etching quality fitness and the k+1th chip etching quality fitness, perform current etching quality fitness optimization on the kth etching decision and the k+1th etching decision to determine the current winning etching quality fitness and the current winning etching decision; based on the current winning etching quality fitness, perform iterative optimization on the current winning etching decision according to the chip etching quality fitness function and the VCSEL chip etching decision space, until the number of iterative optimizations meets the iterative optimization number threshold, and output the VCSEL chip etching optimization process.

[0081] Furthermore, the chip etching quality fitness function described in the embodiment of the present application is:

[0082] .

[0083] Among them, EQF represents the chip etching quality fitness, γ represents the predetermined etching quality fitness analysis factor, 0<γ<1, EQD represents the predicted etching sidewall roughness, QDO represents the expected etching sidewall roughness, EQA represents the predicted etching accuracy, QAO represents the expected etching accuracy, EQS represents the predicted etching balance, and QSO represents the expected etching balance.

[0084] Through the above detailed description of the VCSEL chip etching process quality control method in this specification, those skilled in the art can clearly understand the VCSEL chip etching process quality control device in this embodiment. For the device disclosed in Example 2, since it corresponds to the method disclosed in Example 1 and has corresponding functional units and beneficial effects, the relevant parts can be referred to the method part description.

[0085] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for controlling the quality of VCSEL chip etching process, characterized in that: The method comprises: According to the chip production end, a VCSEL chip etching task is received, wherein the VCSEL chip etching task includes a VCSEL chip to be etched, a chip etching target layer corresponding to the VCSEL chip to be etched, and a chip etching quality constraint, wherein the chip etching quality constraint includes an etching side wall roughness constraint, an etching accuracy constraint, and an etching balance constraint; According to the etching target layer information corresponding to the chip etching target layer, the VCSEL chip etching process factors are registered and associated to establish the VCSEL chip etching control registration space, wherein the chip etching target layer information includes the material, position, and thickness of the target layer, and the etching control registration space is a set containing all possible etching process parameter combinations; Based on the etching target layer information, an etching decision is made on the VCSEL chip etching control registration space according to the chip etching quality constraint, and a VCSEL chip etching decision space that satisfies a predetermined etching decision capacity is generated, wherein the etching decision space is a set of process parameter combinations that meet the etching quality constraint after screening and optimization, and the predetermined etching decision capacity is the number of parameter combinations in the decision space; Performing optimization analysis on the VCSEL chip etching decision space according to the chip etching quality fitness function to obtain the VCSEL chip etching optimization process, wherein the chip etching quality fitness function is a mathematical model used to quantify the relationship between etching process parameters and etching quality; Etching the VCSEL chip to be etched according to the VCSEL chip etching optimization process; According to the etching target layer information corresponding to the chip etching target layer, the VCSEL chip etching process factor is registered and associated to establish the VCSEL chip etching control registration space, including: The VCSEL chip etching process factors include etching solution formula, etching time and etching temperature; Determining whether the chip etching target layer is a single etching target layer; If the chip etching target layer is a single etching target layer, the etching target layer information is used as an etching process retrieval constraint, and the VCSEL chip etching process factor is used as an etching process retrieval target; Performing etching control record retrieval on the chip production end based on the etching process retrieval constraint and the etching process retrieval target to obtain an etching control scheme retrieval set; Based on the VCSEL chip etching process factor, the etching control scheme retrieval set is identified with a trigger interval to obtain the VCSEL chip etching control registration space, where the trigger interval is a valid range of the etching process factor.

2. The VCSEL chip etching process quality control method according to claim 1, characterized in that: Determining whether the chip etching target layer is a single etching target layer includes: If the chip etching target layer is not a single etching target layer, disassemble the etching target layer information according to the hierarchical structure of the chip etching target layer to obtain multi-level etching target layer parameters, where the multi-level etching target layer parameters include material, thickness and position information; Based on the multi-level etching target layer parameters, the VCSEL chip etching process factors are respectively registered and associated to obtain a multi-layer etching control registration space; The VCSEL chip etching control registration space is generated according to the multi-layer etching control registration space.

3. The VCSEL chip etching process quality control method according to claim 1, characterized in that: Based on the etching target layer information, an etching decision is made on the VCSEL chip etching control registration space according to the chip etching quality constraint to generate a VCSEL chip etching decision space that meets a predetermined etching decision capacity, including: Based on the etching target layer information, an etching decision is made according to the VCSEL chip etching control registration space to obtain a VCSEL chip etching solution space, where the etching solution space is a set of possible etching solutions generated based on the etching control registration space; Extracting a first VCSEL chip etching plan according to the VCSEL chip etching plan space; Based on the etching target layer information and the first VCSEL chip etching scheme, and according to an etching quality prediction model, obtaining a first etching quality prediction result; determining whether the first etching quality prediction result satisfies the chip etching quality constraint, If the first etching quality prediction result satisfies the chip etching quality constraint, recording the first VCSEL chip etching scheme as a first VCSEL chip etching decision, and adding the first VCSEL chip etching decision to the VCSEL chip etching decision space; If the first etching quality prediction result does not meet the chip etching quality constraint, eliminating the first VCSEL chip etching solution; The VCSEL chip etching solution space is continuously optimized according to the chip etching quality constraint and the etching quality prediction model until the etching decision capacity of the VCSEL chip etching decision space meets the predetermined etching decision capacity.

4. The VCSEL chip etching process quality control method according to claim 3, characterized in that: Based on the etching target layer information and the first VCSEL chip etching scheme, and according to an etching quality prediction model, a first etching quality prediction result is obtained, including: The etching quality prediction model includes an input layer, an etching sidewall roughness prediction layer, an etching accuracy prediction layer, an etching balance prediction layer and an output layer; Based on the etching target layer information and the first VCSEL chip etching scheme, and according to the etching sidewall roughness prediction layer, a first predicted etching sidewall roughness is obtained; Based on the etching target layer information and the first VCSEL chip etching scheme, and according to the etching accuracy prediction layer, a first predicted etching accuracy is obtained; Based on the etching target layer information and the first VCSEL chip etching scheme, and according to the etching balance prediction layer, a first predicted etching balance is obtained; Based on the first predicted etching sidewall roughness, the first predicted etching accuracy and the first predicted etching balance, the first etching quality prediction result is output according to the output layer.

5. The VCSEL chip etching process quality control method according to claim 1, characterized in that: The VCSEL chip etching decision space is optimized and analyzed according to the chip etching quality fitness function to obtain the VCSEL chip etching optimization process, including: Extracting the kth etching decision according to the VCSEL chip etching decision space, where k is a positive integer; Performing etching quality fitness analysis on the k-th etching decision based on the chip etching quality fitness function to obtain the k-th chip etching quality fitness; Extracting the k+1th etching decision according to the VCSEL chip etching decision space, and calculating the k+1th chip etching quality fitness according to the chip etching quality fitness function; Based on the k-th chip etching quality fitness and the k+1-th chip etching quality fitness, optimizing the current etching quality fitness of the k-th etching decision and the k+1-th etching decision to determine the current winning etching quality fitness and the current winning etching decision; Based on the current winning etching quality fitness, the current winning etching decision is iteratively optimized according to the chip etching quality fitness function and the VCSEL chip etching decision space, until the number of iterative optimizations meets the iterative optimization number threshold, and the VCSEL chip etching optimization process is output.

6. The VCSEL chip etching process quality control method according to claim 1, characterized in that: The chip etching quality fitness function is: ； Among them, EQF represents the chip etching quality fitness, γ represents the predetermined etching quality fitness analysis factor, 0<γ<1, EQD represents the predicted etching sidewall roughness, QDO represents the expected etching sidewall roughness, EQA represents the predicted etching accuracy, QAO represents the expected etching accuracy, EQS represents the predicted etching balance, and QSO represents the expected etching balance.

7. VCSEL chip etching process quality control device, characterized in that: The device is used to perform the VCSEL chip etching process quality control method according to any one of claims 1 to 6, and the device comprises: A task receiving unit, the task receiving unit is used to receive a VCSEL chip etching task according to a chip production end, wherein the VCSEL chip etching task includes a VCSEL chip to be etched, and a chip etching target layer and a chip etching quality constraint corresponding to the VCSEL chip to be etched, and the chip etching quality constraint includes an etching side wall roughness constraint, an etching accuracy constraint, and an etching balance constraint; A registration and association unit, the registration and association unit is used to perform registration and association on the VCSEL chip etching process factors according to the etching target layer information corresponding to the chip etching target layer, and establish the VCSEL chip etching control registration space, the chip etching target layer information includes the material, position, and thickness of the target layer, and the etching control registration space is a set containing all possible etching process parameter combinations; An etching decision unit, wherein the etching decision unit is used to make an etching decision on the VCSEL chip etching control registration space based on the etching target layer information and the chip etching quality constraint, and generate a VCSEL chip etching decision space that meets a predetermined etching decision capacity. The etching decision space is a set of process parameter combinations that meet the etching quality constraint after screening and optimization, and the predetermined etching decision capacity is the number of parameter combinations in the decision space; A process optimization unit, wherein the process optimization unit is used to perform optimization analysis on the VCSEL chip etching decision space according to a chip etching quality fitness function to obtain a VCSEL chip etching optimization process, wherein the chip etching quality fitness function is a mathematical model used to quantify the relationship between etching process parameters and etching quality; An optimization process execution unit, the optimization process execution unit is used to etch the VCSEL chip to be etched according to the VCSEL chip etching optimization process; The registration association unit is also used to perform the following steps: The VCSEL chip etching process factor includes etching solution formula, etching time and etching temperature; judging whether the chip etching target layer is a single etching target layer; if the chip etching target layer is a single etching target layer, taking the etching target layer information as the etching process retrieval constraint, and taking the VCSEL chip etching process factor as the etching process retrieval target; performing etching control record retrieval on the chip production end based on the etching process retrieval constraint and the etching process retrieval target to obtain an etching control scheme retrieval set; performing trigger interval identification on the etching control scheme retrieval set based on the VCSEL chip etching process factor to obtain the VCSEL chip etching control registration space, and the trigger interval is the effective range of the etching process factor.

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