A configurable channelization implementation method and system for intelligent signal identification

Abstract

The present invention discloses a configurable channelization implementation method and system for intelligent signal identification, which belongs to the field of signal detection technology. The method includes: dividing an AD sampling signal into two parallel paths, delaying the first path signal and making the second path signal zero-delayed; performing extraction and multi-phase filtering based on a RAM architecture on each delayed signal to obtain a multi-phase signal, performing FFT transformation to obtain channelized original data; converting, combining in the time domain and sorting channels on the channelized original data to obtain ordered channelized baseband IQ data. Signal delay, extraction and multi-phase filtering are implemented based on RAM, without the need to use shift registers, and only a small number of multipliers are required for calculation. Since RAM is rich in resources in FPGA, it will not increase computing resources; and signal delay, extraction, multi-phase filtering, etc. are implemented by controlling the read and write addresses, with low processing data volume and computational complexity, and the implementation process is concise and efficient.

Description

Technical Field

[0001] The present invention relates to the technical field of signal detection, and in particular to a configurable channelization implementation method and system for intelligent signal identification. Background Art

[0002] With the development of wireless communication technology, the demand for detecting various types of signals is increasing. The signal bandwidth varies with different signals, which puts higher requirements on signal detection technology. In order to adapt to this diverse signal environment, researchers are developing intelligent detection methods that can adapt to complex signal recognition such as different bandwidths and different types. Channelization processing methods can divide a signal within a large bandwidth into small bandwidth signals in several channels, thus providing a basis for intelligent signal recognition. Although existing channel processing methods have made some progress, they still need to be further optimized to meet the needs of signal detection and recognition.

[0003] The current common channelization processing method is to use a shift register in the FPGA to delay extraction of each channel, and then perform multiplication and accumulation to obtain a multi-phase signal. This method consumes a large number of shift registers and multipliers, and the complexity is high when mapped to the FPGA circuit. Especially when a large-scale channelization method with more than 1024 channels adopts this method, due to the limitations of resources such as shift registers and multipliers and the complexity of implementation, large-scale channelization applications are often not implemented in general FPGAs. The currently published channelization processing methods are incomplete and have the defect of spectrum aliasing between adjacent channels. Although some processing methods do not produce spectrum aliasing between adjacent channels, they have high implementation complexity and require the use of a large number of resources.

[0004] For example, the invention patent with announcement number CN104767703B discloses a digital channelized receiver system for broadcast signal monitoring. Its digital channelized module uses RAM to cache data, but requires additional random access memory (RAM) to adjust the data order for inverse fast Fourier transform (IFFT), which is bound to increase complexity while increasing resources.

[0005] In addition, the invention patent with publication number CN104932992A discloses a design method for microwave digital flexible forwarding technology with variable bandwidth granularity. Its digital channel is implemented based on RAM, but its implementation complexity is relatively high, which is specifically manifested in three aspects: first, RAM needs to use dual clocks, a high-multiple clock and a data clock. The frequency of the high-multiple clock is three times that of the data clock. While increasing the clock complexity, when the data clock frequency is relatively high, the three-fold high-multiple clock cannot operate normally in the processor; second, when the number of channels is D, this invention needs to use an IFFT with a length of 2D and a Fast Fourier Transform (Fast Fourier Transform, FFT) with a length of 2D to realize data conversion. The increase in the amount of data processed leads to an increase in computational complexity; especially when D is large, the required computing resources and time will increase significantly; third, stack processing is required before IFFT transformation to realize data sorting, and after FFT transformation, additional RAM, ROM and multipliers are required to realize processing before output sorting, which is more complex in calculation and requires additional resources. Summary of the invention

[0006] The purpose of the present invention is to overcome the problems of the prior art and provide a configurable channelization implementation method and system for intelligent signal identification.

[0007] The object of the present invention is to achieve the following technical solution: a configurable channelization implementation method for intelligent signal identification, the method comprising the following steps:

[0008] The sampling signal is divided into a first sampling signal and a second sampling signal in parallel, and the first sampling signal is delayed by D1 / 2 sampling clocks based on RAM to obtain a first delayed signal; the second sampling signal is processed with zero delay to obtain a second delayed signal; D1 is the actual number of channels configured at runtime, D1=2N, where N is a natural number, N=1, 2, 3, ..., log2(D), and D represents the maximum number of channels;

[0009] Based on the RAM architecture, the first sampling signal and the second sampling signal are extracted and multi-phase filtered to obtain a first multi-phase signal and a second multi-phase signal;

[0010] Performing fast Fourier transform processing on the first multi-phase signal and the second multi-phase signal to obtain first original data and second original data;

[0011] The first original data and the second original data are subjected to data conversion processing according to the channel arrangement odd-even sequence, and then subjected to time domain combination and channel sorting processing to obtain ordered channelized baseband in-phase orthogonal data.

[0012] In one example, the processing method for delaying the first sampling signal by D1 / 2 sampling clocks is as follows:

[0013] At each sampling moment, the write address of the RAM increases by one, and the read address is equal to the write address minus D1 / 2.

[0014] In one example, the first sampling signal and the second sampling signal are extracted and multi-phase filtered based on the RAM architecture, including the following sub-steps:

[0015] At each sampling moment, the first delayed signal and the second delayed signal are written into K-1 RAMs of the first RAM storage control unit and the second RAM storage control unit respectively; K represents the quantity;

[0016] At each sampling moment, the first extracted signal data and the second extracted signal data are read out from each RAM of the first RAM storage control unit and the second RAM storage control unit respectively;

[0017] At each sampling moment, K first polyphase filter coefficients and second polyphase filter coefficients are read out from the ROMs of the first ROM storage control unit and the second ROM storage control unit respectively;

[0018] At each sampling moment, the first extracted signal data is multiplied by the first filter coefficient, and the first extracted signal data is multiplied by the second filter coefficient to obtain K products respectively, and the K products are summed to obtain the first multi-phase signal and the second multi-phase signal.

[0019] In one example, the write addresses of K-1 RAMs are kept synchronized, and return to zero when counting to D1-1, and the addresses of the write address registers correspond to the channel sequence in reverse order.

[0020] In one example, the read address and the write address of each RAM in the first RAM storage control unit and the second RAM storage control unit are equal.

[0021] In one example, the read address register ROM_ADDR and the write address memory WRADDR of the ROM in the first ROM storage control unit and the second ROM storage control unit satisfy the following relationship:

[0022] ROM_ADDR=WRADDR+Ci;

[0023] Wherein, Ci represents a constant related to the number of channels.

[0024] In one example, converting the raw data, combining the data in the time domain, and sorting the channels includes the following sub-steps:

[0025] The first original data is kept unchanged, and the second original data is arranged in channel parity in a manner that the first channel is an odd number, the odd channel data remains unchanged, and the even channel data is subjected to a bitwise inversion and addition operation;

[0026] The data of the same channel in the first original data and the second original data are combined in the time domain in a manner that the first original data is at a previous moment and the second original data is at a current moment;

[0027] By sorting the channels in ascending order of frequency, ordered channelized baseband in-phase and orthogonal data are obtained.

[0028] The present invention also includes a configurable channelization implementation system for intelligent signal identification, which is used to execute the method formed by any one of the above examples or a combination of multiple examples, and the system includes:

[0029] The distribution and delay module is used to divide the sampling signal into a first sampling signal and a second sampling signal in parallel, and then delay the first sampling signal by D1 / 2 sampling clocks based on the RAM to obtain a first delayed signal; and perform zero-delay processing on the second sampling signal to obtain a second delayed signal;

[0030] The extraction / multiphase filtering and reconfiguration module is connected to the allocation and delay module, and is used to extract and multiphase filter the first sampling signal and the second sampling signal according to the RAM architecture to obtain the first multiphase signal and the second multiphase signal;

[0031] a transform module, connected to the extraction / multiphase filtering and reconfiguration module, and configured to perform fast Fourier transform processing on the first multiphase signal and the second multiphase signal to obtain first original data and second original data;

[0032] The data conversion / combination and channel sorting module is connected to the transformation module, performs data conversion processing on the first original data and the second original data obtained according to the parity order of the channel arrangement, and then performs time domain combination and channel sorting processing to obtain ordered channelized baseband in-phase orthogonal data.

[0033] In one example, the decimation / polyphase filtering and reconfiguration module includes a first decimation / polyphase filtering and reconfiguration submodule and a second decimation / polyphase filtering and reconfiguration submodule, and the transformation module includes a first transformation submodule and a second transformation submodule;

[0034] The first extraction / polyphase filtering and reconfiguration submodule includes a first RAM storage control unit, a first ROM storage control unit and a first multiplication-accumulation unit; the first RAM storage control unit includes multiple serial RAMs, each RAM output end and the first ROM storage control unit output end are connected to the first multiplication-accumulation unit, and the output end of the first multiplication-accumulation unit is connected to the first conversion submodule; or, the first RAM storage control unit includes multiple parallel RAMs, each RAM output end and the first ROM storage control unit output end are connected to the first multiplication-accumulation unit, and the output end of the first multiplication-accumulation unit is connected to the first conversion submodule;

[0035] The second extraction / multi-phase filtering and reconfiguration submodule includes a second RAM storage control unit, a second ROM storage control unit and a second multiplication-accumulation unit; the second RAM storage control unit includes multiple serial RAMs, each RAM output end and the output end of the second ROM storage control unit are connected to the second multiplication-accumulation unit, and the output end of the second multiplication-accumulation unit is connected to the second conversion submodule; or, the second RAM storage control unit includes multiple parallel RAMs, each RAM output end and the output end of the second ROM storage control unit are connected to the second multiplication-accumulation unit, and the output end of the second multiplication-accumulation unit is connected to the second conversion submodule.

[0036] In one example, the data conversion / combination and channel sorting module includes:

[0037] A data conversion unit, used to keep the first original data unchanged, and perform channel parity arrangement on the second original data in a manner that the first channel is odd, the odd channel data remains unchanged, and the even channel data performs a bitwise inversion and addition operation;

[0038] A data combining unit, connected to the data converting unit, for combining the data of the same channel in the first original data and the second original data in the time domain in a manner that the first original data is at a previous moment and the second original data is at a current moment;

[0039] The channel sorting unit is connected to the data combining unit and is used to sort the channels in ascending order of frequency to obtain ordered channelized baseband in-phase and orthogonal data.

[0040] It should be further explained that the technical features corresponding to the above system examples can be combined or replaced with each other to form a new technical solution.

[0041] Compared with the prior art, the present invention has the following beneficial effects:

[0042] 1. In one example, signal delay, extraction, and multi-phase filtering are implemented based on RAM, without the need to use shift registers, and only a small number of multipliers are needed for calculation. Since RAM is rich in resources in FPGA, it will not increase computing resources; further, signal delay, extraction, multi-phase filtering and other processing are implemented by controlling the read and write addresses, the amount of data processed is low, and there is no need to perform stack processing, the calculation complexity is low, and the implementation process is simple and efficient. At the same time, the present invention performs parallel processing and recombining of two signals, which can effectively control the extraction multiple, so that the channelized sampling rate and the channel bandwidth are in a multiple relationship, and the channelized sampling rate and the bandwidth are not equal, which will not cause aliasing of the spectrum between adjacent channels, and avoid signal distortion after channelization. Furthermore, during the operation process, the number of channels can be reconfigured by changing the mapping relationship between the channel and the RAM address to achieve new signal extraction and filtering processing, which can flexibly adapt to the needs of different bandwidths and extraction rates in different application scenarios; the number of channels supports large-scale channelized applications greater than 1024, which can meet the refined analysis of large-bandwidth signals.

[0043] 2. In one example, the address count of the write address register returns to zero when it reaches D1-1, and the channel is quickly reconfigured by changing the D1 value. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The specific implementation methods of the present invention are further described in detail below in conjunction with the accompanying drawings. The accompanying drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The same reference numerals are used in these drawings to represent the same or similar parts. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0045] Figure 1 A method flow chart provided for an example of the present invention;

[0046] Figure 2 A RAM serial timing system framework diagram provided for an example of the present invention;

[0047] Figure 3 A RAM parallel system framework diagram provided for an example of the present invention. DETAILED DESCRIPTION

[0048] The technical solution of the present invention is described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] In the description of the present invention, it should be noted that the use of ordinal numbers (eg, "first and second", etc.) is to distinguish objects and is not limited to the order and cannot be understood as indicating or implying relative importance.

[0050] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, "connection" should be understood in a broad sense, for example, it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0051] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0052] For a certain number of channels, the corresponding prototype filter order is L, and the polyphase filter order is L / D, where D is the maximum number of configurable channels. The number of RAMs used for signal extraction, polyphase filtering, and channel reconfiguration is K-1, with a length of D and a width equal to the bit width of the analog-to-digital (AD) sampling signal. Reading takes precedence when reading and writing the same RAM address.

[0053] Furthermore, signal delay, extraction, polyphase filtering and channel reconfiguration are implemented based on RAM. The polyphase filter coefficients are stored in ROM. The depth of ROM is 2*D and the width is the bit width of K filter coefficients. The prototype filter coefficients corresponding to different channels are stored in ROM in the order of D, D / 2, D / 4, D / 8, ..., 8, 4, 2 channels. The number of channels in channel reconfiguration can be changed in real time during operation, and the number of channels can be reconfigured to D1=2. N , where N=1, 2, 3,…, log2(D).

[0054] In one example, if Figure 1 As shown, a configurable channelization implementation method for intelligent signal identification includes the following steps:

[0055] S10: dividing the sampling signal into a first sampling signal and a second sampling signal in parallel, delaying the first sampling signal by D1 / 2 sampling clocks to obtain a first delayed signal; performing zero-delay processing on the second sampling signal to obtain a second delayed signal.

[0056] In this step, the delay is implemented using RAM. When reading and writing the same address, the read priority is given. The width of the read address register and the write address register is equal to log2(D / 2). At each sampling moment, a data is written to the RAM. The initial value of the write address register is 0. When it increments to D1 / 2-1, it returns to zero. The read address register is equal to the write address register minus D1 / 2. In this way, at each sampling clock, the data read from the RAM is the data after the delay of D1 / 2 sampling clocks.

[0057] S20: Based on the RAM architecture, the first sampling signal and the second sampling signal are extracted and multi-phase filtered to obtain a first multi-phase signal and a second multi-phase signal.

[0058] In this step, two sampling signals are extracted through K-1 RAMs, and the extracted signals are multiplied and summed with the polyphase filter coefficients at the corresponding sampling moments stored in the ROM to obtain a polyphase signal for subsequent data processing.

[0059] S30: Perform fast Fourier transform processing on the first multi-phase signal and the second multi-phase signal to obtain first original data and second original data.

[0060] In this step, the multiphase signal is subjected to FFT transformation processing with a length of D2, and the length of FFT D2 is consistent with the number of channels D1. When the number of channels D1 changes, the length of FFT changes accordingly. After the transformation, the channelized original in-phase orthogonal data is obtained.

[0061] S40: performing data conversion processing on the first original data and the second original data according to the channel arrangement parity sequence, and then performing time domain combination and channel sorting processing to obtain ordered channelized baseband in-phase and quadrature data (IQ data).

[0062] Among them, the time domain combination is used to perform data alignment processing on the first original data and the second original data in the time domain; the channel sorting processing is used to sort the aligned data according to the channel order, that is, to sort the channels in ascending order of frequency.

[0063] The method of the present invention uses RAM to delay, extract and multi-phase filter the AD sampling signal, and then performs FFT transformation, converts, combines and sorts the transformed data to obtain ordered channelized baseband IQ data. Among them, signal extraction, multi-phase filtering and channel reconfiguration in the channelization processing method are all implemented based on RAM, without the need to use shift registers, and only a small number of multipliers are needed, which can greatly save processor resources. The channel can be configured in real time and can be flexibly applied to application scenarios with different requirements for the number of channels and bandwidth. Furthermore, the main feature of the method of the present invention is that it uses RAM architecture to realize signal delay, extraction, multi-phase filtering and channel number reconfiguration, can be efficiently implemented based on FPGA, can realize up to 8192 channels in a single general-purpose FPGA, and can realize large-scale configurable channelized receivers on general-purpose FPGAs.

[0064] In one example, in step S20, the first sampling signal and the second sampling signal are extracted and multi-phase filtered based on the RAM architecture, including the following sub-steps:

[0065] S201: At each sampling moment, write the first delayed signal and the second delayed signal into K-1 RAMs of the first RAM storage control unit and the second RAM storage control unit respectively.

[0066] In this step, at each sampling moment, the first delay signal and the second delay signal are written into the first RAM storage control unit and the second RAM storage control unit respectively, and the outputs of the K-1 previous RAMs connected in series in each storage control unit are connected to the inputs of the next RAM. Further, the write addresses of the K-1 RAMs are kept synchronized, that is, at each sampling moment, the write address values ​​of the K-1 RAMs are equal, which is equivalent to updating the K-1 caches of a certain channel at each sampling moment. The length of the RAM is L1, and the value of L1 is the same as the maximum number of channels D. The initial value of the K-1 write address registers WRADDR of the RAM is 0, and when the write address register increases to D1-1, it returns to zero. Every increase of the write address register of the RAM is a data written to the corresponding channel, and the reconfiguration of the channel is achieved by changing the value of the number of channels D1. Since the number of coefficients of the multi-phase filter is K, that is, at each sampling moment, the number of data that needs to participate in the multi-phase filtering calculation of a certain channel is K, after deducting an existing data at the current moment, K-1 data still needs to be stored, and the number of RAMs is obtained to be K-1. Since the maximum number of configurable channels is D, that is, each RAM needs to cache a maximum of D data, the length of the RAM is D. At each sampling moment, the write address register is incremented, that is, the data cached in the high address unit of each RAM is later than the data in the low address unit, so the incoming data is written to the RAM in reverse order of the channels, that is, the address of the write address register corresponds to the channel order in reverse order.

[0067] Optionally, the first RAM storage control unit and K-1 serially connected K-1 in the first RAM storage control unit may be replaced with K parallel RAMs, which can also achieve the purpose of signal extraction and multi-phase filtering.

[0068] S202: At each sampling moment, read out the first extracted signal data and the second extracted signal data from each RAM of the first RAM storage control unit and the second RAM storage control unit respectively.

[0069] In this step, at each sampling moment, the read address register RDADDR_i of the i-th RAM is RDADDR_i=WRADDR, i is the index of the RAM, i=1, 2, ..., K-1. Since the RAM is read-first, that is, the data written and read from each RAM differ by D1 sampling moments. At sampling moment n, the RAM numbered 1 reads the data at time n-D1, and the RAM numbered 2 reads the data at time n-2*D1. By analogy, the RAM numbered K-1 reads the data at time n-(K-1)*D1. Together with the data at the current moment n, they constitute K data for multi-phase filtering calculation in a certain channel. Compared with the input data, these K data are extracted D1 times. It can be seen that the extraction of the signal is achieved by periodically counting the read and write addresses of the K-1 RAMs with a length of D1.

[0070] S203: At each sampling moment, read out K first polyphase filter coefficients and second polyphase filter coefficients from the ROMs of the first ROM storage control unit and the second ROM storage control unit respectively.

[0071] In this step, at each sampling moment, K filter coefficients are read out from the ROM. The prototype filter coefficients when the number of channels is D, D / 2, D / 4, D / 8, ..., 8, 4, 2 are stored in the ROM. The storage order of the prototype filter coefficients in the ROM is according to the order of the number of channels being D, D / 2, D / 4, D / 8, ..., 8, 4, 2. The read address register ROM_ADDR of the ROM and the write address memory WRADDR satisfy: ROM_ADDR=WRADDR+Ci, where Ci is a constant related to the number of channels. It can be seen from the storage order of the prototype filter coefficients in the ROM that when the number of channels is D, Ci=0; when the number of channels is D / 2, Ci=D; when the number of channels is D / 4, Ci=D+D / 2; when the number of channels is 2, Ci=D+D / 2+D / 4+...+4.

[0072] S204: At each sampling moment, the first extracted signal data is correspondingly multiplied by the first filter coefficient, and the first extracted signal data is correspondingly multiplied by the second filter coefficient to obtain K products respectively, and the K products are summed to obtain a first multi-phase signal and a second multi-phase signal.

[0073] In this step, the multi-phase signal generated by the data read out from RAM address unit 0 is recorded as multi-phase data 0, the multi-phase signal generated by the data read out from address unit 1 is recorded as multi-phase data 1, and so on. The multi-phase signal generated by the data read out from address unit D1-1 is recorded as multi-phase data D1-1.

[0074] S205: At each sampling moment, write the first multi-phase signal and the second multi-phase signal into the first conversion submodule and the second conversion submodule respectively.

[0075] In this step, the first multiphase signal and the second multiphase signal are respectively written into the FFT transformation submodule of length D2, the length D2 of the FFT is equal to the number of channels D1, the multiphase data 0 corresponds to the first point of the FFT, the multiphase data 1 corresponds to the second point of the FFT, and so on, the multiphase data D1-1 corresponds to the D2 point of the FFT. After the transformation, the first and second original data are obtained.

[0076] In one example, step S40 performs data conversion processing on the first original data and the second original data according to the parity order of the channel arrangement, and then performs time domain combination and channel sorting processing, including the following sub-steps:

[0077] S401: Keep the first original data unchanged, and perform channel parity arrangement on the second original data in a manner that the first channel is odd, the odd channel data remains unchanged, and the even channel data is bitwise inverted and added by one;

[0078] S402: combining the data of the same channel in the first original data and the second original data in the time domain in a manner that the first original data is at a previous moment and the second original data is at a current moment;

[0079] S403: Sort the channels in ascending order of frequency to obtain ordered channelized baseband in-phase and orthogonal data.

[0080] The above examples are combined to obtain a preferred example of the present invention, in which the method comprises the following steps:

[0081] S1: Divide the sampling signal into a first sampling signal and a second sampling signal in parallel, delay the first sampling signal by D1 / 2 sampling clock based on RAM to obtain a first delayed signal; perform zero-delay processing on the second sampling signal to obtain a second delayed signal;

[0082] S2: extracting and multi-phase filtering the first sampling signal and the second sampling signal based on the RAM architecture, including the following sub-steps:

[0083] S21: at each sampling moment, writing the first delayed signal and the second delayed signal into K-1 RAMs of the first RAM storage control unit and the second RAM storage control unit respectively;

[0084] S22: at each sampling moment, reading out the first extracted signal data and the second extracted signal data from each RAM of the first RAM storage control unit and the second RAM storage control unit respectively;

[0085] S23: at each sampling moment, read out K first polyphase filter coefficients and second polyphase filter coefficients from the ROMs of the first ROM storage control unit and the second ROM storage control unit respectively;

[0086] S24: at each sampling moment, correspondingly multiplying the first extracted signal data by the first filter coefficient, correspondingly multiplying the first extracted signal data by the second filter coefficient, respectively obtaining K products, and summing the K products respectively to obtain a first multi-phase signal and a second multi-phase signal;

[0087] S3: Performing fast Fourier transform processing on the first multi-phase signal and the second multi-phase signal to obtain first original data and second original data;

[0088] S4: converting, combining in the time domain, and sorting in the channels the first original data and the second original data, including the following sub-steps:

[0089] S41: Keep the first original data unchanged, and perform channel parity arrangement on the second original data in a manner that the first channel is odd, the odd channel data remains unchanged, and the even channel data is bit-wise inverted and added by one;

[0090] S42: combining the data of the same channel in the first original data and the second original data in the time domain in a manner that the first original data is at a previous moment and the second original data is at a current moment;

[0091] S43: Sort the channels in ascending order of frequency to obtain ordered channelized baseband IQ data.

[0092] The present invention also includes a configurable channelization implementation system for intelligent signal identification, which is used to execute the method formed by any one of the above examples or a combination of multiple examples, such as Figure 2 As shown, it includes a distribution and delay module, an extraction / multiphase filtering and reconfiguration module, a transformation module, a data conversion / combination and channel sorting module connected in sequence.

[0093] The allocation and delay module is used to divide the sampling signal into a first sampling signal and a second sampling signal in parallel, and then delay the first sampling signal by D1 / 2 sampling clocks based on the RAM to obtain a first delayed signal; and perform zero-delay processing on the second sampling signal to obtain a second delayed signal;

[0094] The extraction / multi-phase filtering and reconfiguration module is used to extract and multi-phase filter the first sampling signal and the second sampling signal according to the RAM architecture to obtain a first multi-phase signal and a second multi-phase signal;

[0095] The transformation module includes a first transformation submodule and a second transformation submodule, which respectively perform fast Fourier transformation processing on the first multi-phase signal and the second multi-phase signal to obtain first original data and second original data;

[0096] The data conversion / combination and channel sorting module is used to convert, combine in time domain and sort in channels the first original data and the second original data to obtain ordered channelized baseband in-phase and orthogonal data.

[0097] In one example, the decimation / polyphase filtering and reconfiguration module includes a first decimation / polyphase filtering and reconfiguration submodule and a second decimation / polyphase filtering and reconfiguration submodule;

[0098] like Figure 2 As shown, the first extraction / polyphase filtering and reconfiguration submodule includes a first RAM storage control unit, a first ROM storage control unit and a first multiplication-accumulation unit, the first RAM storage control unit includes multiple serial RAMs, each RAM output end and the first ROM storage control unit output end are connected to the first multiplication-accumulation unit, and the output end of the first multiplication-accumulation unit is connected to the first conversion submodule. The second extraction / polyphase filtering and reconfiguration submodule includes a second RAM storage control unit, a second ROM storage control unit and a second multiplication-accumulation unit, the second RAM storage control unit includes multiple serial RAMs, each RAM output end and the second ROM storage control unit output end are connected to the second multiplication-accumulation unit, and the output end of the second multiplication-accumulation unit is connected to the second conversion submodule.

[0099] Among them, the first RAM storage control unit and the second RAM storage control unit include K-1 RAMs, which are used to store the first delayed signal and the second delayed signal at each sampling moment; at the same time, the read and write address control is realized through the write address register and the read address memory of the RAM to realize signal extraction, multi-phase filtering and channel reconfiguration processing. The first ROM storage control unit and the second ROM storage control unit are used to realize the storage of multi-phase filter coefficients according to the read address control. The first multiplication and accumulation unit and the second multiplication and accumulation unit are used to multiply and accumulate the first extracted signal data and the second extracted signal data with the first multi-phase filter coefficient and the second multi-phase filter coefficient to generate the first multi-phase signal and the second multi-phase signal.

[0100] As an implementation method, Figure 3 As shown, the first extraction / polyphase filtering and reconfiguration submodule includes a first RAM storage control unit, a first ROM storage control unit and a first multiplication-accumulation unit, the first RAM storage control unit includes K parallel RAMs, the K RAM output ends and the first ROM storage control unit output end are connected to the first multiplication-accumulation unit, and the output end of the first multiplication-accumulation unit is connected to the first conversion submodule. The second extraction / polyphase filtering and reconfiguration submodule includes a second RAM storage control unit, a second ROM storage control unit and a second multiplication-accumulation unit, the second RAM storage control unit includes multiple parallel RAMs, each RAM output end and the second ROM storage control unit output end are connected to the second multiplication-accumulation unit, and the output end of the second multiplication-accumulation unit is connected to the second conversion submodule. Optionally, the first RAM storage control unit and the second RAM storage control unit may also include K-1 parallel RAMs, the K-1 RAM output end in the first RAM storage control unit is connected to the first multiplication-accumulation unit, and the K-1 RAM output end in the second RAM storage control unit is connected to the second multiplication-accumulation unit.

[0101] Optionally, in the configurable channelization implementation system of the parallel or serial RAM architecture, the first extraction / polyphase filtering and reconfiguration submodule also includes a first cache unit, the second extraction / polyphase filtering and reconfiguration submodule also includes a second cache unit, the first multiplication and accumulation unit is connected to the first transformation submodule via the first cache unit, and the second multiplication and accumulation unit is connected to the second transformation submodule via the second cache unit.

[0102] In one example, the data conversion / combination and channel sorting module includes a data conversion unit, a data combination unit, and a channel sorting unit connected in sequence.

[0103] The data conversion unit is used to convert the channelized original IQ data:

[0104] The first original data is kept unchanged, and the second original data is arranged in channel parity in a manner that the first channel is odd, the odd channel data remains unchanged, and the even channel data is subjected to a bitwise inversion and addition operation.

[0105] The data combination unit is used to combine the data of the same channel in two paths in chronological order in the time domain:

[0106] The data of the same channel in the first original data and the second original data are combined in the time domain in a manner that the first original data is at a previous moment and the second original data is at a current moment.

[0107] The channel sorting unit is used to sort the channels in ascending order of frequency to obtain ordered channelized baseband in-phase and orthogonal data.

[0108] In a specific optional embodiment, the sampling clock frequency is f clkK =204.8MHz, the AD data width after sampling is 16 bits, and the number of channels is D=4096, so the number of channels can be configured as D1=2, 4, 8, ..., 1024, 2048, 4096. The order of the polyphase filter is 8, and the length of the RAM used for extraction and polyphase filtering is 4096, the width is 16, and the number is 7. During operation, the number of channels D1 is configured as D1=4096.

[0109] The AD sampling data is divided into two paths, and the length of the RAM used for delay is 2048. The first path of data is output after a delay of 2048 sampling clocks, and the second path has zero delay.

[0110] The delayed data of the first channel is written into 7 serially connected RAMs at the sampling clock frequency. The output of the previous RAM is equal to the input of the next RAM. The read address register and write address register of the RAM have a bit width of 12. The initial values ​​of the write address registers of the 7 RAMs are all 0, and 1 is added at each sampling moment. When the address register of the RAM counts to D1=4095, it returns to zero. Since the data is written into the RAM in an address incrementing manner, it is equivalent to writing a data to the cache with channel number 4096 when writing address 0, and writing a data to the cache with channel number 1 when writing address 4095, so the data is written into the RAM in the reverse order of the channel. Because the number of polyphase filter coefficients is 8, that is, the number of data used for polyphase filtering calculation in each channel is 8, excluding the data at the current moment, each channel only needs to cache 7 data, so the number of RAMs is 7. Since the maximum number of channels supported is 4096, the length of the RAM is 4096.

[0111] The 7 RAMs are numbered in the order of 1 to 7. At each sampling moment, the read address value of the RAM numbered i is equal to the write address, that is, the read and write addresses of the 7 RAMs are the same at each sampling moment. For example, at moment n, the write address is 0, and its corresponding channel is 4096. When operating on the same address of the RAM, read priority is given. At this time, the data written to the first RAM address unit 0 and the data read out are generated at a time difference of 4096 sampling clocks, that is, the generation time of the read data is n-4096, and the generation time of the data read out from the 2nd to 7th RAMs is n-4096*2, n-4096*3, ..., n-4096*7, respectively. The data read out from the 7 RAMs plus the data at the current moment is equivalent to 8 data obtained after the input data is extracted 4096 times. At the same time, 8 filter coefficients are read out from ROM address 0, multiplied with the corresponding 8 data to obtain 8 products, and then summed to obtain a multi-phase data of channel 4096. When the read address changes from 0 to 4095, 4096 multi-phase data are generated.

[0112] The 4096 multi-phase data are input into the FFT converter with a length of 4096 for FFT transformation, wherein the multi-phase data with addresses 0 to 4095 correspond to the 1st to 4096th points of the FFT in sequence, and the first original data of the 4096 channels are obtained after transformation.

[0113] The second channel of data is similarly subjected to decimation, polyphase filtering and FFT transformation to obtain another channel of 4096 channels of second original data.

[0114] The data of the 4096 channels in the first path remain unchanged, and the 4096 channels in the second path are sorted in an odd-even manner, the odd channel data remain unchanged, and the even channel data are bit-inverted and added 1.

[0115] The data of each of the 4096 channels are combined in time in the manner of the first path being the previous moment and the second path being the current moment, and then the channels are reordered in ascending frequency order to obtain 4096 ordered channelized baseband IQ data, where the decimation multiple of each channel is 2048. The combination of the two paths is equivalent to 4096-fold decimation and then 2-fold interpolation, so the sampling rate after channelization is twice the channel bandwidth. The channelized sampling rate is not equal to the bandwidth, which will not cause aliasing of the spectrum between adjacent channels and avoid signal distortion after channelization.

[0116] If you need to reconfigure the number of channels to other values, such as 1024, you only need to change the channel number parameter D1=1024.

[0117] The above specific implementation methods are detailed descriptions of the present invention. It cannot be determined that the specific implementation methods of the present invention are limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions and substitutions can be made without departing from the concept of the present invention, which should be regarded as belonging to the protection scope of the present invention.

Claims

1. A configurable channelization implementation method for intelligent signal identification, characterized in that: The following steps are involved: The sampling signal is divided into a first sampling signal and a second sampling signal in parallel, and the first sampling signal is delayed by D1 / 2 sampling clocks based on the RAM to obtain a first delayed signal; The second sampling signal is processed with zero delay to obtain the second delayed signal; D1 is the actual number of channels configured during runtime, D1=2 N , where N is a natural number, N=1, 2, 3, …, log2(D), and D represents the maximum number of configurable channels; Based on the RAM architecture, the first sampling signal and the second sampling signal are extracted and multi-phase filtered to obtain a first multi-phase signal and a second multi-phase signal; Performing fast Fourier transform processing on the first multi-phase signal and the second multi-phase signal to obtain first original data and second original data; Performing data conversion processing on the first original data and the second original data according to the channel arrangement parity sequence, and then performing time domain combination and channel sorting processing to obtain ordered channelized baseband in-phase orthogonal data; Based on the RAM architecture, the first sampling signal and the second sampling signal are extracted and multi-phase filtered, including the following sub-steps: At each sampling moment, the first delayed signal and the second delayed signal are written into K-1 RAMs of the first RAM storage control unit and the second RAM storage control unit respectively; K represents the quantity; At each sampling moment, the first extracted signal data and the second extracted signal data are read out from each RAM of the first RAM storage control unit and the second RAM storage control unit respectively; At each sampling moment, K first polyphase filter coefficients and second polyphase filter coefficients are read out from the ROMs of the first ROM storage control unit and the second ROM storage control unit respectively; At each sampling moment, the first extracted signal data is correspondingly multiplied by the first filter coefficient, and the first extracted signal data is correspondingly multiplied by the second filter coefficient to obtain K products respectively, and the K products are summed to obtain a first multi-phase signal and a second multi-phase signal; The raw data is converted, combined in the time domain, and sorted in the channels, including the following sub-steps: The first original data is kept unchanged, and the second original data is arranged in channel parity in a manner that the first channel is an odd number, the odd channel data remains unchanged, and the even channel data is subjected to a bitwise inversion and addition operation; The data of the same channel in the first original data and the second original data are combined in the time domain in a manner that the first original data is at a previous moment and the second original data is at a current moment; By sorting the channels in ascending order of frequency, ordered channelized baseband in-phase and orthogonal data are obtained.

2. The configurable channelization implementation method for intelligent signal identification according to claim 1, characterized in that: The processing method for delaying the first sampling signal by D1 / 2 sampling clocks is as follows: At each sampling moment, the write address of the RAM increases by one, and the read address is equal to the write address minus D1 / 2.

3. The configurable channelization implementation method for intelligent signal identification according to claim 1, characterized in that: The write addresses of K-1 RAMs are kept synchronized, and return to zero when counting to D1-1. The addresses of the write address registers correspond to the channel sequence in reverse order; K represents the quantity.

4. The configurable channelization implementation method for intelligent signal identification according to claim 1, characterized in that: The read address and the write address of each RAM in the first RAM storage control unit and the second RAM storage control unit are equal.

5. The configurable channelization implementation method for intelligent signal identification according to claim 1, characterized in that: The ROM read address register ROM_ADDR and the write address memory WRADDR in the first ROM storage control unit and the second ROM storage control unit satisfy the following relationship: ROM_ADDR=WRADDR+Ci; Wherein, Ci represents a constant related to the number of channels.

6. A configurable channelization implementation system for intelligent signal identification, used to execute the method according to any one of claims 1 to 5, characterized in that: include: A distribution and delay module, used for dividing the sampling signal into a first sampling signal and a second sampling signal in parallel, and then delaying the first sampling signal by D1 / 2 sampling clocks based on the RAM to obtain a first delayed signal; Performing zero-delay processing on the second sampling signal to obtain a second delayed signal; The extraction / multiphase filtering and reconfiguration module is connected to the allocation and delay module, and is used to extract and multiphase filter the first sampling signal and the second sampling signal according to the RAM architecture to obtain the first multiphase signal and the second multiphase signal; a transform module, connected to the extraction / multiphase filtering and reconfiguration module, and configured to perform fast Fourier transform processing on the first multiphase signal and the second multiphase signal to obtain first original data and second original data; The data conversion / combination and channel sorting module is connected to the transformation module, performs data conversion processing on the first original data and the second original data according to the parity order of the channel arrangement, and then performs time domain combination and channel sorting processing to obtain ordered channelized baseband in-phase orthogonal data; The first sampling signal and the second sampling signal are extracted and multi-phase filtered according to the RAM architecture, including the following sub-steps: At each sampling moment, the first delayed signal and the second delayed signal are written into K-1 RAMs of the first RAM storage control unit and the second RAM storage control unit respectively; K represents the quantity; At each sampling moment, the first extracted signal data and the second extracted signal data are read out from each RAM of the first RAM storage control unit and the second RAM storage control unit respectively; At each sampling moment, K first polyphase filter coefficients and second polyphase filter coefficients are read out from the ROMs of the first ROM storage control unit and the second ROM storage control unit respectively; At each sampling moment, the first extracted signal data is correspondingly multiplied by the first filter coefficient, and the first extracted signal data is correspondingly multiplied by the second filter coefficient to obtain K products respectively, and the K products are summed to obtain a first multi-phase signal and a second multi-phase signal; The data conversion / combination and channel sorting modules include: A data conversion unit, used for keeping the first original data unchanged, and performing channel parity arrangement on the second original data in a manner that the first channel is an odd number, the odd channel data remains unchanged, and the even channel data performs a bitwise inversion and addition operation; A data combining unit, connected to the data converting unit, for combining the data of the same channel in the first original data and the second original data in the time domain in a manner that the first original data is the previous moment and the second original data is the current moment; The channel sorting unit is connected to the data combining unit and is used to sort the channels in ascending order of frequency to obtain ordered channelized baseband in-phase and orthogonal data.

7. The configurable channelization implementation system for intelligent signal identification according to claim 6, characterized in that: The extraction / polyphase filtering and reconfiguration module includes a first extraction / polyphase filtering and reconfiguration submodule and a second extraction / polyphase filtering and reconfiguration submodule, and the transformation module includes a first transformation submodule and a second transformation submodule; The first extraction / polyphase filtering and reconfiguration submodule includes a first RAM storage control unit, a first ROM storage control unit and a first multiplication and accumulation unit; The first RAM storage control unit includes multiple serial RAMs, each RAM output end and the first ROM storage control unit output end are connected to the first multiplication and accumulation unit, and the output end of the first multiplication and accumulation unit is connected to the first conversion submodule; or, the first RAM storage control unit includes multiple parallel RAMs, each RAM output end and the first ROM storage control unit output end are connected to the first multiplication and accumulation unit, and the output end of the first multiplication and accumulation unit is connected to the first conversion submodule; The second extraction / polyphase filtering and reconfiguration submodule includes a second RAM storage control unit, a second ROM storage control unit and a second multiplication and accumulation unit; The second RAM storage control unit includes multiple serial RAMs, each RAM output end and the second ROM storage control unit output end are connected to the second multiplication and accumulation unit, and the output end of the second multiplication and accumulation unit is connected to the second conversion submodule; Or, the second RAM storage control unit includes multiple parallel RAMs, each RAM output end and the second ROM storage control unit output end are connected to the second multiplication and accumulation unit, and the output end of the second multiplication and accumulation unit is connected to the second transformation submodule.

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