A BM algorithm implementation device for long series polynomial synthesis based on FPGA

Abstract

The present invention discloses a BM algorithm implementation device for long series polynomial synthesis based on FPGA, comprising: a control module for initialization, iterative calculation to complete the BM algorithm solution of polynomial synthesis; a sequence module for caching input sequence; an output polynomial module for caching the output polynomial of iterative calculation; an intermediate polynomial module for caching the intermediate polynomial of iterative calculation; the sequence module, the output polynomial module and the intermediate polynomial module are all connected to the control module. The sequence cache and the polynomial cache of the present invention are all implemented by large-capacity FPGA on-chip BRAM, which is convenient for increasing the working clock frequency, and the timing design is simple, which is suitable for the BM algorithm solution of long series polynomial synthesis; at the same time, in the process of iterative update, the reading and writing operations of the polynomial are carried out simultaneously in a pipeline manner, which can improve the calculation speed of the BM algorithm.

Description

Technical Field

[0001] The present invention relates to the technical field of linear feedback polynomial synthesis, and more specifically, to a BM algorithm implementation device for long series polynomial synthesis based on FPGA. Background Art

[0002] set up yes For a sequence of length N, The polynomial on is: ;

[0003] in, , if the elements in the sequence satisfy the recurrence relation: ; ; then it is called Generate binary sequence .in Indicates is the feedback polynomial If is a product that produces And the feedback polynomial of the linear shift register with the smallest series, is the number of stages of the shift register, then It is called the linear comprehensive solution of the sequence.

[0004] The Berlekamp-Massey algorithm (BM algorithm for short) uses an iterative approach to solve the sequence The linear comprehensive solution of . The process of BM algorithm is as follows:

[0005] 1. Initialization and settings: ;

[0006] in, is the current output polynomial, is the current output polynomial series, is the intermediate polynomial, is the series of the intermediate polynomial, n is the number of iterations, and m is The corresponding sample point index.

[0007] 2. Iterative calculation

[0008] The iterative calculation starts from n=0, and the iterative calculation formula is as follows: ;

[0009] in, The difference calculated by the n-th iteration is discussed in two cases:

[0010] when =0, then , is the output polynomial after iterative update.

[0011] when =1, There are two cases for the iterative formula:

[0012] 1) If =0, then , is the output polynomial series after iterative update;

[0013] 2) If ≠0, then , .

[0014] when =1, The iteration formula is as follows:

[0015] 1) If ,but ;

[0016] 2) If ,but Remain unchanged.

[0017] The BM algorithm uses an iterative calculation method, which is particularly suitable for FPGA implementation. When the polynomial series is short, the register resources used in iterative calculation are relatively small, and FPGA can meet the logic resource requirements. When the polynomial series is tens of thousands, the register resources used in iterative calculation will also reach tens of thousands, and the timing will become very complicated. Using registers for iterative calculation will consume a lot of resources or even be impossible to implement.

[0018] FPGA has large-scale on-chip BRAM resources. BRAM resources have the advantages of large capacity and high speed. If BRAM can be used to replace the shift register used for iteration, the problem of implementing the BM algorithm for long series polynomial synthesis can be solved. Conventionally, the cache depth supported by BRAM resources is as high as one million samples. Therefore, it is necessary to develop a BM algorithm implementation device for long series polynomial synthesis based on FPGA. Summary of the invention

[0019] The purpose of the present invention is to provide a BM algorithm implementation device for long series polynomial synthesis based on FPGA to overcome the defects of the prior art.

[0020] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0021] A BM algorithm implementation device for long series polynomial synthesis based on FPGA, comprising:

[0022] The control module is used for initialization and iterative calculation to complete the BM algorithm solution of polynomial synthesis;

[0023] Sequence module, used to cache input sequences;

[0024] Output polynomial module, used to cache the output polynomial of iterative calculation;

[0025] Intermediate polynomial module, used to cache intermediate polynomials of iterative calculations;

[0026] The sequence module, the output polynomial module and the intermediate polynomial module are all connected to the control module;

[0027] The control module includes an iterative controller, a difference calculation multiplication unit, a difference calculation accumulation unit, and an iterative calculation XOR addition unit. The iterative controller receives the difference calculation result d n , issue a control command to complete the iterative calculation; the difference calculation multiplication unit receives the output binary sequence a of the sequence module n and the coefficients f of the output polynomial module cur (x), perform binary multiplication operation, and the output result is connected to the difference calculation accumulation unit, which receives the output of the difference calculation multiplication unit, performs binary accumulation operation, and outputs the difference calculation result d n Connected to the iterative controller, the iterative calculation XOR addition unit receives the coefficients f of the output polynomial module cur (x) and the coefficient of the intermediate polynomial module fm(x), perform binary XOR addition operation, and output the result f next (x) Connect to the output polynomial module.

[0028] Furthermore, the sequence module includes a sequence write controller, a sequence buffer and a sequence read controller. Under the control of the control module, the sequence write controller sequentially writes one binary sequence sample point in each iteration cycle. , and cached through the sequence cache, the sequence read controller reads out l in reverse order cur +1 length binary sequence sample .

[0029] Furthermore, the output polynomial module includes an output polynomial write controller, an output polynomial buffer, and an output polynomial read controller. Under the control of the control module, the output polynomial read controller sequentially reads out the output polynomial buffer from the output polynomial buffer in each iteration cycle. cur +1 length output polynomial coefficients , the output polynomial write controller sequentially writes l next +1 length output polynomial coefficients to the output polynomial buffer.

[0030] Furthermore, the intermediate polynomial module includes an intermediate polynomial write controller, an intermediate polynomial cache, and an intermediate polynomial read controller. Under the control of the control module, the intermediate polynomial read controller sequentially reads the intermediate polynomial coefficients after adding zeros from the intermediate polynomial cache in each iteration cycle. , the intermediate polynomial write controller sequentially writes l cur +1 length intermediate polynomial coefficients To the intermediate polynomial cache, l cur is the series of the current output polynomial sequence, and lm is the series of the intermediate polynomial.

[0031] Furthermore, the control method of the device includes:

[0032] S1, initialization state: set l cur =0, lm=0, m=0, n=0, the output polynomial write controller will f cur (x) = 1 is written to the output polynomial buffer, and the intermediate polynomial write controller writes fm(x) = 1 to the intermediate polynomial buffer. cur is the series of the current output polynomial sequence, lm is the series of the intermediate polynomial, m is the sample point index corresponding to the intermediate polynomial, n is the number of iterations, and f cur (x) is the current output polynomial, fm(x) is the intermediate polynomial;

[0033] S2, Sequence write state: Sequence write controller writes 1 sequence sample point sequentially to sequence buffer 22;

[0034] S3, difference calculation state: the sequence read controller reads out l in reverse order cur +1 sequence sample point, output polynomial read controller sequentially reads out l cur +1 polynomial coefficient, difference calculation multiplication unit and difference calculation accumulation unit complete the difference of the nth step in real time calculate;

[0035] S4, iterative judgment state: when =0, set n=n+1 and return to S2; when =1, enter state S5;

[0036] S5, iterative variable update status: update each state value, and then enter S6. The update method of the state variable is as follows:

[0037] When l cur =0, the zero-adding amount s=n+1 of the intermediate polynomial read controller is set, otherwise s=nm is set;

[0038] When n+1-l cur >cur When setting l next =n+1-l cur , m=n, lm=l cur , set the intermediate polynomial update flag fm_update = 1; otherwise set l next = l cur , fm_update=0;

[0039] S6, iterate the polynomial update state, and the output polynomial read controller sequentially reads f from the output polynomial cache cur (x) cur +1 polynomial coefficient, the intermediate polynomial read controller sequentially reads out the s+lm+1 polynomial coefficients of fm(x) after adding zeros, and the iterative XOR addition unit calculates and outputs f in real time next (x) The coefficients of the polynomial, the output polynomial write controller real-time f next (x) polynomial l next +1 coefficient is written to the output polynomial cache. When fm_update=1, the intermediate polynomial write controller writes f in real time. cur (x) cur +1 polynomial coefficient is written to the intermediate polynomial cache. After the polynomial update is completed, set l cur =l next , set n=n+1 and return to state S2.

[0040] Compared with the prior art, the advantages of the present invention are as follows: the sequence cache and polynomial cache of the present invention are all implemented by large-capacity FPGA on-chip BRAM, which is convenient for increasing the working clock frequency, has a simple timing design, and is suitable for solving long-series polynomial comprehensive BM algorithm; at the same time, in the process of iterative update, the reading and writing operations of the polynomial are performed simultaneously in a pipeline manner, which can improve the calculation speed of the BM algorithm. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 It is a schematic diagram of a BM algorithm implementation device for long series polynomial synthesis based on FPGA of the present invention.

[0043] Figure 2 It is a schematic diagram of writing and reading the sequence cache in the present invention.

[0044] Figure 3 It is a schematic diagram of writing and reading of the polynomial cache in the present invention. DETAILED DESCRIPTION

[0045] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.

[0046] See also Figure 1 As shown, this embodiment discloses a BM algorithm implementation device for long series polynomial synthesis based on FPGA, including: a control module 1, used for initialization, iterative calculation to complete the BM algorithm solution of polynomial synthesis; a sequence module 2, used for caching input sequences; an output polynomial module 3, used for caching output polynomials of iterative calculations; an intermediate polynomial module 4, used for caching intermediate polynomials of iterative calculations; the sequence module 2, the output polynomial module 3 and the intermediate polynomial module 4 are all connected to the control module 1.

[0047] In this embodiment, it is assumed that the number of polynomials to be solved is L=10000, so the three cache depths H in this embodiment are all set to 16384 to meet the requirements, the cache width is 1 bit, and each cache can be implemented using 1 BRAM.

[0048] In this embodiment, the control module 1 includes an iterative controller 11, a difference calculation multiplication unit 12, a difference calculation accumulation unit 13, and an iterative calculation XOR addition unit 14. The difference calculation multiplication unit 12 is connected to the difference calculation accumulation unit 13 and the iterative calculation XOR addition unit 14. The control module initializes the entire module and then iteratively calculates to complete the BM algorithm solution of the polynomial synthesis. The iterative controller 11 is used to receive the difference calculation result d n , issue a control command, complete the iterative calculation, the difference calculation multiplication unit 12 receives the output binary sequence a of the sequence module n and the coefficients f of the output polynomial module cur (x), performs binary multiplication operation, and the output result is connected to the difference calculation accumulation unit. In this embodiment, the difference calculation multiplication unit 12 performs two 1-bit multiplication operations, which can be realized using a simple 2-input lookup table. The difference calculation accumulation unit 13 receives the output of the difference calculation multiplication unit, performs binary accumulation operation, and outputs the difference calculation result d n Connected to the iterative controller, in this embodiment, the difference calculation accumulation unit 13 completes the accumulation of two 1-bits, which can be achieved using an XOR operation. The iterative calculation XOR addition unit 14 receives the coefficient f of the output polynomial module cur (x) and the coefficient of the intermediate polynomial module fm(x), perform binary XOR addition operation, and output the result fnext (x) Connect to the output polynomial module.

[0049] In this embodiment, the sequence module 2 includes a sequence write controller 21, a sequence buffer 22 and a sequence read controller 23. Under the control of the control module 1, the sequence write controller 21 sequentially writes a binary sequence sample point in each iteration cycle. , and cached by the sequence cache 22, the sequence read controller 23 reads out l in reverse order cur +1 length binary sequence sample , Figure 2 The schematic diagram of writing and reading the sequence module is shown in FIG. The sequence buffer 22 is configured as 16384 in depth and 1 in width, which can be realized by using 1 BRAM. Since the sequence buffer is written in a sequential loop, there is no limit on the length of the input sequence.

[0050] In this embodiment, the output polynomial module 3 includes an output polynomial write controller 31, an output polynomial buffer 32, and an output polynomial read controller 33. Under the control of the control module, the output polynomial read controller 33 sequentially reads out the output polynomial buffer 32 in each iteration cycle. cur +1 length output polynomial coefficients , output polynomial write controller 31 sequentially writes l next +1 length output polynomial coefficients To output polynomial buffer 32, Figure 3 The schematic diagram of writing and reading the polynomial module is shown in Figure 1. The output polynomial buffer 32 is configured as 16384 deep and 1 bit wide, which can be realized using 1 BRAM.

[0051] In this embodiment, the intermediate polynomial module 4 includes an intermediate polynomial write controller 41, an intermediate polynomial cache 42, and an intermediate polynomial read controller 43. Under the control of the control module, the intermediate polynomial read controller 43 sequentially reads the intermediate polynomial coefficients after adding zeros from the intermediate polynomial cache 42 in each iteration cycle. , the intermediate polynomial write controller 41 sequentially writes l cur +1 length intermediate polynomial coefficients To the intermediate polynomial buffer 42, l cur is the series of the current output polynomial sequence, lm is the series of the intermediate polynomial, and the intermediate polynomial cache 42 is configured as 16384 depth and 1 bit width, which can be implemented using 1 BRAM.

[0052] The control method of the BM algorithm implementation device based on FPGA long series polynomial synthesis of the present invention comprises:

[0053] Step S1, initialization state: set lcur =0, lm=0, m=0, n=0, the output polynomial write controller 31 will f cur (x)=1 is written into the output polynomial buffer 32, and the intermediate polynomial write controller 41 writes fm(x)=1 into the intermediate polynomial buffer 42. cur is the series of the current output polynomial sequence, lm is the series of the intermediate polynomial, m is the sample point index corresponding to the intermediate polynomial, n is the number of iterations, and f cur (x) is the current output polynomial, fm(x) is the intermediate polynomial;

[0054] Step S2, sequence writing state: the sequence writing controller 21 sequentially writes 1 sequence sample point to sequence buffer 22;

[0055] Step S3, difference calculation state: the sequence read controller 23 reads out l in reverse order cur +1 sequence sample point, output polynomial read controller 33 sequentially reads out l cur +1 polynomial coefficient, the difference calculation multiplication unit 12 and the difference calculation accumulation unit 13 complete the difference of the nth step in real time calculate;

[0056] Step S4, iterative judgment state: when =0, set n=n+1 and return to S2; when =1, enter state S5;

[0057] Step S5, iterative variable update state: update each state value, and after completion, enter S6. The state variable update method is as follows:

[0058] When l cur =0, the zero-adding amount s=n+1 of the intermediate polynomial read controller 43 is set, otherwise s=nm;

[0059] When n+1-l cur > cur When setting l next =n+1-l cur , m=n, lm=l cur , set the intermediate polynomial update flag fm_update = 1; otherwise set l next = l cur , fm_update=0;

[0060] Step S6, iterate the polynomial update state, and the output polynomial read controller 33 sequentially reads f from the output polynomial buffer cur (x) cur+1 polynomial coefficient, the intermediate polynomial read controller 43 sequentially reads out the s+lm+1 polynomial coefficients of fm(x) after adding zeros, and the iterative XOR addition unit 14 calculates and outputs f in real time. next (x) The coefficients of the polynomial, the output polynomial write controller 31 real-time f next (x) polynomial l next +1 coefficient is written into the output polynomial buffer. When fm_update=1, the intermediate polynomial write controller 41 writes f in real time. cur (x) cur +1 polynomial coefficient is written to the intermediate polynomial buffer 42. After the polynomial update is completed, set l cur =l next , set n=n+1 and return to state S2.

[0061] The sequence cache and polynomial cache of the present application are all implemented using large-capacity FPGA on-chip BRAM, which is convenient for increasing the working clock frequency and has a simple timing design, and is suitable for solving long-series polynomial comprehensive BM algorithm; at the same time, during the iterative update process, the reading and writing operations of the polynomial are performed simultaneously in a pipelined manner, which can improve the calculation speed of the BM algorithm.

[0062] Although the embodiments of the present invention are described in conjunction with the accompanying drawings, the patent owner may make various variations or modifications within the scope of the appended claims. As long as they do not exceed the protection scope described in the claims of the present invention, they should be within the protection scope of the present invention.

Claims

1. A BM algorithm implementation device for long series polynomial synthesis based on FPGA, characterized in that: include: The control module is used for initialization and iterative calculation to complete the BM algorithm solution of polynomial synthesis; Sequence module, used to cache input sequences; Output polynomial module, used to cache the output polynomial of iterative calculation; Intermediate polynomial module, used to cache intermediate polynomials of iterative calculations; The sequence module, the output polynomial module and the intermediate polynomial module are all connected to the control module; The control module includes an iterative controller, a difference calculation multiplication unit, a difference calculation accumulation unit, and an iterative calculation XOR addition unit. The iterative controller receives the difference calculation result d n , issue a control command to complete the iterative calculation; the difference calculation multiplication unit receives the output binary sequence a of the sequence module n and the coefficients f of the output polynomial module cur (x), perform binary multiplication operation, and the output result is connected to the difference calculation accumulation unit, which receives the output of the difference calculation multiplication unit, performs binary accumulation operation, and outputs the difference calculation result d n Connected to the iterative controller, the iterative calculation XOR addition unit receives the coefficients f of the output polynomial module cur (x) and the coefficient of the intermediate polynomial module fm(x), perform binary XOR addition operation, and output the result f next (x) connected to the output polynomial module; The sequence module includes a sequence write controller, a sequence buffer and a sequence read controller. Under the control of the control module, the sequence write controller sequentially writes a binary sequence sample point in each iteration cycle. , and cached through the sequence cache, the sequence read controller reads out l in reverse order cur +1 length binary sequence sample ; The output polynomial module includes an output polynomial write controller, an output polynomial buffer, and an output polynomial read controller. Under the control of the control module, the output polynomial read controller sequentially reads out the output polynomial buffer from the output polynomial buffer in each iteration cycle. cur +1 length output polynomial coefficients , the output polynomial write controller sequentially writes l next +1 length output polynomial coefficients to the output polynomial buffer; The intermediate polynomial module includes an intermediate polynomial write controller, an intermediate polynomial cache, and an intermediate polynomial read controller. Under the control of the control module, the intermediate polynomial read controller sequentially reads the intermediate polynomial coefficients after adding zeros from the intermediate polynomial cache in each iteration cycle. , the intermediate polynomial write controller sequentially writes l cur +1 length intermediate polynomial coefficients To the intermediate polynomial cache, l cur is the series of the current output polynomial sequence, and lm is the series of the intermediate polynomial.

2. The BM algorithm implementation device for long series polynomial synthesis based on FPGA according to claim 1, characterized in that: The control method of the device includes: S1, initialization state: set l cur =0, lm=0, m=0, n=0, the output polynomial write controller will f cur (x) = 1 is written to the output polynomial buffer, and the intermediate polynomial write controller writes fm(x) = 1 to the intermediate polynomial buffer. cur is the series of the current output polynomial sequence, lm is the series of the intermediate polynomial, m is the sample point index corresponding to the intermediate polynomial, n is the number of iterations, and f cur (x) is the current output polynomial, fm(x) is the intermediate polynomial; S2, Sequence write state: Sequence write controller writes 1 sequence sample point sequentially to the sequence cache; S3, difference calculation state: the sequence read controller reads out l in reverse order cur +1 sequence sample point, output polynomial read controller sequentially reads out l cur +1 polynomial coefficient, difference calculation multiplication unit and difference calculation accumulation unit complete the difference of the nth step in real time calculate; S4, iterative judgment state: when When , set n=n+1 and return to S2; when When , enter state S5; S5, iterative variable update status: update each state value, and then enter S6. The update method of the state variable is as follows: When l cur =0, the zero-adding amount s=n+1 of the intermediate polynomial read controller is set, otherwise s=nm is set; When n+1-l cur > cur When setting l next =n+1-l cur , m=n, lm=l cur , set the intermediate polynomial update flag fm_update = 1; otherwise set l next = l cur , fm_update=0; S6, iterate the polynomial update state, and the output polynomial read controller sequentially reads f from the output polynomial cache cur (x) cur +1 polynomial coefficient, the intermediate polynomial read controller sequentially reads out the s+lm+1 polynomial coefficient of fm(x) after adding zeros, and the iterative XOR addition unit calculates and outputs f in real time next (x) The coefficients of the polynomial, the output polynomial write controller real-time f next (x) polynomial l next +1 coefficient is written to the output polynomial cache. When fm_update=1, the intermediate polynomial write controller writes f in real time. cur (x) cur +1 polynomial coefficient is written to the intermediate polynomial cache. After the polynomial update is completed, set l cur =l next , set n=n+1 and return to state S2.

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