A memory and a control method thereof

Abstract

The present invention provides a memory and a control method thereof, wherein the memory comprises: a flash memory chip, wherein some storage blocks are divided into system blocks; an error correction module, which is electrically connected to the flash memory chip, and when editing a secondary address mapping table, if the secondary address mapping table reports an error and the error correction fails, the error correction module generates and sends error reporting data; a reconstruction module, which is electrically connected to the error correction module and receives the error reporting data, and after the error correction of the error correction module fails, the reconstruction module generates a fused secondary table and replaces the secondary address mapping table in the system block with the fused secondary table; wherein the fused secondary table includes the secondary address mapping table in the system block, the secondary address mapping table stored in the cache module, and the address mapping information of the latest edited user data in the system block. The present invention provides a memory and a control method thereof, which can improve the data storage stability of the memory.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory and a control method thereof. Background Art

[0002] Flash memory media has the characteristic of not being easily volatile when power is off, so it is widely used in the storage field. Since flash memory stores data relying on level flipping, the data stored in the flash memory may also be lost. Therefore, the error checking and correcting (ECC) capability is related to the storage stability of the memory.

[0003] In the case of read and write data errors, the error checking and correction technology can detect data errors in time and correct the erroneous data. However, in the case of abnormal power failure or unstable power supply, the error correction data exceeds the error correction capability of the error checking and correction technology, and the storage system will report an error. The read and write data that cannot be corrected will be lost. Summary of the invention

[0004] The object of the present invention is to provide a memory and a control method thereof, which can improve the data storage stability of the memory.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a memory, comprising:

[0007] A flash memory chip, the flash memory chip comprising a plurality of storage blocks, wherein some of the storage blocks are divided into system blocks, and the system blocks store a primary address mapping table and a secondary address mapping table;

[0008] A cache module, electrically connected to the flash memory chip and the host computer, allowing the primary address mapping table and the secondary address mapping table to be edited in the cache module;

[0009] an error correction module, electrically connected to the flash memory chip, and when editing the secondary address mapping table, if the secondary address mapping table reports an error and the error correction fails, the error correction module generates and sends error data; and

[0010] A reconstruction module, electrically connected to the error correction module and receiving the error reporting data, wherein after the error correction module fails to correct an error, the reconstruction module generates a fused secondary table and replaces the secondary address mapping table in the system block with the fused secondary table;

[0011] The fused secondary table includes the secondary address mapping table in the system block, the secondary address mapping table stored in the cache module, and address mapping information of the most recently edited user data in the system block.

[0012] In one embodiment of the present invention, the secondary address mapping table stores address mapping information of the user data, and the primary address mapping table stores address mapping information of the secondary address mapping table, wherein the address mapping information is a mapping relationship between the logical address and the physical address of the user data.

[0013] In one embodiment of the present invention, the reconstruction module includes a marking unit. When the secondary address mapping table reports an error and the error correction fails, the marking unit marks the secondary address mapping table that reports an error and the error correction fails as a table to be rebuilt, and records the serial number of the table to be rebuilt and the logical address of the table to be rebuilt.

[0014] In one embodiment of the present invention, the reconstruction module includes an old data query unit, and according to the logical address of the table to be rebuilt, the old data query unit obtains the old table information of the table to be rebuilt from the first-level address mapping table, wherein the old table information includes the address mapping information when the table to be rebuilt was last edited.

[0015] In one embodiment of the present invention, the reconstruction module includes a scanning unit, which is electrically connected to the system block, allowing the scanning unit to read the system block and, based on the address mapping information stored in the system block, obtain a physical address range of the flash memory chip related to the address mapping information, wherein the physical address range includes an initial address and an end address, allowing the scanning unit to scan the physical address range and, based on the address mapping information in the physical address range, reconstruct a secondary address mapping table as the address mapping information of the most recently edited user data in the system block.

[0016] In one embodiment of the present invention, the reconstruction module includes a data filling unit, which stores single or multiple types of blank data. When the secondary address mapping table reports an error and error correction fails, the data filling unit is allowed to fill the blank data into the secondary address mapping table that reports an error and error correction fails, wherein the blank data is preset data.

[0017] In one embodiment of the present invention, the reconstruction module includes a programming unit. When the secondary address mapping table reports an error and the error correction fails, the programming unit is allowed to transfer the secondary address mapping table filled with the blank data to the cache module, and the programming unit is allowed to transfer the erroneous system block to the bad block pool. After completing the programming task, the programming unit generates a task construction indication signal.

[0018] In one embodiment of the present invention, the reconstruction module includes a task construction unit, which receives the task construction indication signal and establishes a reconstruction task in the task queue of the memory, wherein the priority of the reconstruction task is lower than the instruction task of the host computer.

[0019] In one embodiment of the present invention, the system block also stores an erase count record table, a read count record table, and a valid data number record table, as well as the secondary address mapping table transferred from the cache module, wherein the erase count record table stores the erase counts of multiple storage blocks, the read count record table stores the read counts of multiple storage blocks, and the valid data number record table stores the valid data counts of multiple storage blocks.

[0020] The present invention provides a memory control method, based on the memory as described above, characterized in that it comprises the following steps:

[0021] When reading and writing user data, generating a secondary address mapping table according to the address mapping information of the user data;

[0022] According to the logical address of the secondary address mapping table, read the secondary address mapping table with the same logical address from the flash memory chip into the cache module, and edit the secondary address mapping table and the primary address mapping table in the cache module;

[0023] When editing the secondary address mapping table, if the secondary address mapping table reports an error and the error correction fails, the error correction module generates and sends error reporting data; and

[0024] The reconstruction module receives the error data, and after the error correction module fails to correct the error, the reconstruction module generates a fused secondary table according to the secondary address mapping table in the system block, the secondary address mapping table stored in the cache module, and the address mapping information of the most recently edited user data in the system block; and

[0025] The fused secondary table replaces the secondary address mapping table in the system block that reports an error and fails error correction.

[0026] As described above, the present invention provides a memory and a control method thereof. When the address mapping information of user data in the memory cannot be corrected due to a fault, the address mapping information that cannot be corrected can be restored on the basis of completing the work instructions of the host computer, which can improve the data storage stability of the memory without affecting the working performance of the memory itself. In addition, the memory and a control method thereof provided by the present invention can completely restore the address mapping information of user data, thereby avoiding the system block being directly treated as a bad block and improving the service life of the memory.

[0027] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0029] Figure 1 FIG. 4 is a schematic diagram of the structure of a memory in an embodiment of the present invention.

[0030] Figure 2 FIG. 4 is a flow chart of a method for controlling a memory in an embodiment of the present invention.

[0031] Figure 3 The figure is a schematic diagram of the mapping relationship between the primary address mapping table and the secondary address mapping table in one embodiment of the present invention.

[0032] In the figure: 10, memory; 20, main controller; 21, error correction module; 22, reconstruction module; 221, data filling unit; 222, programming unit; 223, marking unit; 224, task construction unit; 225, old data query unit; 226, scanning unit; 227, fusion reconstruction unit; 30, cache module; 40, flash memory chip; 41, storage block; 411, storage page; 42, system block; 50, host computer. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] See also Figure 1 and Figure 2As shown, the present invention provides a memory 10. The memory 10 includes a main controller 20, a cache module 30 and a flash memory chip 40, wherein the main controller 20 is electrically connected to a host computer 50 through an interface to receive instructions and data from the host computer 50 and to feed back data of the main controller 20. In this embodiment, the main controller 20 includes an error correction module 21 and a reconstruction module 22. In this embodiment, the flash memory chip 40 is electrically connected to the error correction module 21 to perform error correction on the data read and written by the flash memory chip 40 during the read and write process of the flash memory chip 40. It should be noted that the error correction module 21 can complete the error check and correction of the flash memory chip 40 through a low-density parity check code (LDPC). The present invention does not limit the error correction algorithm of the error correction module 21. In the present invention, when the error correction data exceeds the error correction capability of the error correction module 21, the error correction module 21 will mark the current error correction data as an uncorrectable error, generate error reporting data, and then report the error reporting data to the main controller 20. It should be noted that the main controller 20 may be a microprocessor-based controller, wherein the microprocessor is, for example, a Reduced Instruction System Computer (RISC), and specifically an ARM processor. The reconstruction module 22 is electrically connected to the error correction module 21, and receives the error reporting data of the error correction module 21. In the present invention, when the uncorrectable error in the error reporting data originates from the address mapping information, the control method of the memory 10 provided by the present invention may be executed. Specifically, the control method of the memory 10 provided by the present invention includes steps S100 to S500.

[0035] Step S100: When an uncorrectable secondary address mapping table appears in the memory 10, the uncorrectable secondary address mapping table is marked as a table to be rebuilt, and blank data is filled into the table to be rebuilt.

[0036] Step S200, obtaining the system block where the table to be rebuilt is located, moving the system block into the bad block pool, and constructing a reconstruction task in the task queue of the main controller 20, wherein the reconstruction task is executed when the memory 10 is in an idle state.

[0037] Step S300: In the reconstruction task, according to the serial number of the table to be reconstructed, the system block is retrieved and a secondary address mapping table which is valid before the table to be reconstructed appears and has the same serial number is obtained from the system block as the first table to be merged.

[0038] Step S400: If there is an action of updating table information between the table to be rebuilt and the first table to be merged, scan the storage block corresponding to the address mapping information according to the address mapping information stored in the system block, and establish a secondary address mapping table of user data as the second table to be merged.

[0039] Step S500: Obtain the secondary address mapping table in the cache module as the third table to be merged.

[0040] Step S600: merge the first table to be merged, the second table to be merged, and the third table to be merged to obtain a merged secondary table, and replace the secondary address mapping table in the system block with the merged secondary table.

[0041] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, when an uncorrectable secondary address mapping table appears in the memory 10, step S100 is executed. The host write command is a data write instruction sent by the host computer 50, which is used to write user data to the memory 10. After receiving the host write command, the memory 10 reads the secondary address mapping table from the flash memory chip 40 to the cache module 30 according to the logical address of the user data, and edits the secondary address mapping table in the cache module 30. In the process of reading out the secondary address mapping table, if the error correction module 21 finds that the secondary address mapping table is wrong and the error correction fails, the current secondary address mapping table is an uncorrectable secondary address mapping table, and step S100 is executed.

[0042] See also Figures 1 to 3 As shown, in one embodiment of the present invention, it should be noted that the data written into the memory 10 has a logical address and a physical address, wherein the physical address is the storage location of the written data in the memory 10. When writing data, an address mapping relationship is established between the logical address and the physical address of the written data, so that when the written data is retrieved, the physical address of the written data can be found according to the address mapping relationship. Among them, the address mapping relationship of the written data can be stored in a specific position of the memory 10 in the form of a linked list. In this embodiment, the linked list of the address mapping relationship storing the user data is set as a secondary address mapping table. Similarly, the secondary address mapping table also has a physical address and a logical address, wherein the logical address of the secondary address mapping table can also be embodied as a serial number of the secondary address mapping table. In this embodiment, a mapping relationship is established between the physical address and the logical address of the secondary address mapping table, and is expressed in the form of a linked list, thereby obtaining a primary address mapping table. When reading or writing data, the edited data may be the data that has been written, so according to the logical address of the user data, it can be determined whether the secondary address mapping table needs to be changed. Specifically, when the cache module 30 or the flash memory chip 40 has a secondary address mapping table with the same logical address as the user data currently to be edited, the relevant secondary address mapping table is read into the cache module 30, and the read secondary address mapping table is edited while the user data is written.

[0043] See also Figures 1 to 3As shown, in one embodiment of the present invention, it should be noted that the flash memory chip 40 includes a plurality of storage blocks 41, wherein the storage block 41 may be a physical block of a NAND flash memory, and each storage block 41 has a unique device number. The storage block 41 includes a plurality of storage pages 411, and the storage page 411 may be a physical page of a NAND flash memory. In this embodiment, part of the storage blocks 41 may be divided into system blocks 42 during the card opening stage of the memory 10. The system block 42 is used to store table information of the flash memory chip 40. In this embodiment, the system block 42 stores a primary address mapping table, a secondary address mapping table, an erase count record table, a read count record table, and a valid data count record table. The erase count record table stores the erase counts of a plurality of storage blocks 41, the read count record table stores the read counts of a plurality of storage blocks 41, and the valid data count record table stores the valid data counts of a plurality of storage blocks 41.

[0044] See also Figures 1 to 3 As shown, in one embodiment of the present invention, it should be noted that the secondary address mapping table stored in the system block 42 includes a secondary address mapping table directly stored in the flash memory chip 40 and a secondary address mapping table flushed from the cache module 30 to the system block 42. In this embodiment, the cache module 30 can be set to be normally open, and the secondary address mapping tables in the system block 42 are all transferred from the cache module 30. In other embodiments of the present invention, the cache module 30 can also be closed, and the main controller 20 is directly electrically connected to the flash memory chip 40. After the secondary address mapping table is generated, it is directly stored in the system block 42. Specifically, in this embodiment, a flush cycle or a flush threshold is set. When the time for storing data in the cache module 30 reaches the flush cycle, or when the stored data in the cache module 30 reaches the flush threshold, the secondary address mapping table in the cache module 30 is transferred to the system block 42, so as to obtain better storage stability while taking into account the high performance of the memory 10.

[0045] See also Figures 1 to 3As shown, in one embodiment of the present invention, in step S100, the secondary address mapping table that cannot be corrected is marked as a table to be rebuilt, and blank data is filled in the table to be rebuilt. The blank data is data of all 0 or all 1. Then the address mapping information of the currently written user data is written into the table to be rebuilt to avoid the loss of the address mapping information of the current user data. The table to be rebuilt with the written data is written back to the system block 42. It should be noted that after the secondary address mapping table is edited and written back to the system block 42, the corresponding primary address mapping table also needs to adjust the physical address. The physical address of the original secondary address mapping table is the old physical address. Because it does not correspond to the actual data, the original secondary address mapping table becomes invalid data, and the old secondary address mapping table can be recycled in the garbage collection process (garbage collection, gc). The present invention first fills the secondary address mapping table with address mapping information, and then writes it into the system block 42 to avoid affecting the execution of the host write command of the memory 10.

[0046] See also Figures 1 to 3 As shown, in one embodiment of the present invention, in step S200, the system block 42 corresponding to the table to be rebuilt is first moved into the bad block pool. Specifically, the address information of the system block 42 is written into the bad block table to avoid calling the system block 42 where the table to be rebuilt is located when writing information later, thereby improving the stability of the storage system. In step S200, a reconstruction task can be constructed in the task queue of the main controller 20 at the same time or before and after the system block 42 is first moved into the bad block pool. The reconstruction task is only executed in the idle state of the memory 10. It should be noted that the idle state of the memory 10 means that the main controller 20 has executed the instructions of the host computer 50 and has not received new instructions from the host computer 50 within a preset time.

[0047] See also Figures 1 to 3 As shown, in one embodiment of the present invention, in step S300, when the memory 10 enters the idle state, the reconstruction task is executed, namely, step S300 to step S600. In step S300, the serial number of the table to be reconstructed is obtained. Wherein obtaining the serial number of the table to be reconstructed can also be equivalent to obtaining the logical address of the table to be reconstructed. It should be noted that the table to be reconstructed is copied from the system block 42 to the cache module 30, so the original data of the table to be reconstructed can also be found in the system block 42. According to the logical address of the table to be reconstructed, the corresponding system block 42 is retrieved. Specifically, from the corresponding system block 42, according to the logical address of the table to be reconstructed, the first-level address mapping table is retrieved to obtain the physical address of the table to be reconstructed. From the corresponding physical address, a second-level address mapping table that is the same as the serial number of the table to be reconstructed and valid is obtained, and the found second-level address mapping table is used as the first table to be fused.

[0048] See also Figures 1 to 3As shown, in one embodiment of the present invention, if there is an action of updating table information between the table to be rebuilt and the first table to be merged. Specifically, according to the logical address and the serial number, the physical addresses of the first table to be merged and the table to be rebuilt found in the system block 42 are inconsistent, then the current first table to be merged cannot actually represent the original data of the table to be rebuilt, but represents the data updated before the table to be rebuilt. That is, in step S300, only the invalid secondary address mapping table with the same serial number as the table to be rebuilt is found, and step S400 is executed. In step S400, the address mapping information of the user data and the address mapping information of the secondary address mapping table are stored in the system block 42. According to the address mapping information of the user data, the storage range of the user data in the flash memory chip 40 can be obtained. According to the address mapping information of the secondary address mapping table, the storage range of the secondary address mapping table in the system block 42 can be obtained. In this embodiment, by scanning the storage block 41 corresponding to the address mapping information of the user data, the secondary address mapping table of the user data corresponding to the system block 42 is reconstructed. Specifically, the physical addresses of all the secondary address mapping tables are found according to the logical address range in the primary address mapping table in the system block 42. From the physical addresses of all the secondary address mapping tables, the physical addresses of the user data involved in all the secondary address mapping tables are found. The physical addresses of the user data involved are searched accordingly, and the secondary address mapping tables are reconstructed according to the logical addresses and actual physical addresses of the user addresses stored in the storage block 41. In this embodiment, the reconstructed secondary address mapping tables are all the secondary address mapping tables in the system block 42. It should be noted that in the process of obtaining the second table to be merged, the originally valid secondary address mapping tables in the system block 42 can be directly inherited and the reconstruction process can be skipped.

[0049] See also Figures 1 to 3As shown, in another embodiment of the present invention, if there is an action of updating table information between the table to be rebuilt and the first table to be merged. Specifically, according to the logical address and serial number of the table to be rebuilt, the physical addresses of the first table to be merged and the table to be rebuilt found in the system block 42 are inconsistent, then the current first table to be merged cannot actually represent the original data of the table to be rebuilt, but represents the data updated before the table to be rebuilt. That is, in step S300, only the invalid secondary address mapping table with the same serial number as the table to be rebuilt is found, and step S400 is executed. In step S400, the address mapping information updated between the first table to be merged and the table to be rebuilt is stored in the system block 42. For example, the logical address of the user data in the first table to be merged is LBA1, and the physical address of the user data is PBA1. After the table information is updated, the logical address of the user data is still LBA1, but the physical address of the user data has actually been changed to PBA5. The correct information of the user data is stored in the table to be rebuilt that is not filled with blank data, and the information of the table to be rebuilt has been lost at this time. However, according to the logical address LBA1 of the user data found in the first table to be merged, the user data corresponding to the logical address LBA1 can be found by retrieving the storage block 41 involved in the system block 42, and the actual physical address PB5 of the user data can be obtained. The address mapping information of the user data is re-established as the second table to be merged. It should be noted here that although the specific physical address of the user data cannot be directly known, the physical address of the user data located at the previous sequence number of the table to be rebuilt and the physical address of the user data located at the next sequence number of the table to be rebuilt can be obtained according to the sequence number of the table to be rebuilt. Among them, the physical address of the user data at the previous sequence number of the table to be rebuilt is marked as the first physical address, and the physical address of the user data at the next sequence number of the table to be rebuilt is marked as the second physical address. According to the range from the first physical address to the second physical address, the corresponding storage block 41 is retrieved, and the user data of the required logical address can be quickly retrieved.

[0050] See also Figures 1 to 3As shown, in one embodiment of the present invention, in step S500, the secondary address mapping table in the cache module 30 is obtained as the third table to be merged. It should be noted here that the table to be rebuilt extracted from the cache module 30 does not store only one address mapping information, but may store multiple address mapping information of user data. Therefore, in this embodiment, in step S600, the secondary address mapping table currently written into the cache module 30, the secondary address mapping table rebuilt by retrieving part of the storage block 41 in the flash memory chip 40, and the original data of the table to be rebuilt in the original system block 42 are merged to reconstruct the secondary address mapping table in the system block 42. It should be noted here that during the period from establishing the reconstruction task to executing the reconstruction task, the table to be rebuilt has been written with new address mapping information, so when merging, the secondary address mapping table in the cache module 30 should also be merged. In addition, it should be noted that during the period from establishing the reconstruction task to executing the reconstruction task, if the secondary address mapping table is flushed, the flushed secondary address mapping table can be found from the primary address mapping table as part of the third table to be merged. In step S600, in this embodiment, the merged L2 address mapping table is used to replace all L2 address mapping tables in the original system block 42. In another embodiment of the present invention, the merged L2 address mapping table is used to replace the table to be rebuilt.

[0051] See also Figures 1 to 3 As shown, in one embodiment of the present invention, the reconstruction module 22 includes a data filling unit 221, a programming unit 222, a marking unit 223, a task construction unit 224, an old data query unit 225, a scanning unit 226 and a fusion reconstruction unit 227. When the secondary address mapping table reports an error and the error correction fails, the marking unit 223 marks the secondary address mapping table that reports an error and the error correction fails as a table to be reconstructed, and records the serial number of the table to be reconstructed and the logical address of the table to be reconstructed. The data filling unit 221 stores single or multiple types of blank data. When the secondary address mapping table reports an error and the error correction fails, the data filling unit 221 fills the blank data into the secondary address mapping table that reports an error and the error correction fails, wherein the blank data is preset data, such as all 1 data or all 0 data. Wherein, when the secondary address mapping table reports an error and the error correction fails, the programming unit 222 transfers the table to be rebuilt filled with blank data to the cache module 30, and the programming unit 222 transfers the erroneous system block 42 to the bad block pool. After the programming unit 222 completes the programming task, it generates a task construction indication signal. Wherein, the task construction unit 224 receives the task construction indication signal and establishes a reconstruction task in the task queue of the main controller 20, wherein the priority of the reconstruction task is lower than the instruction task of the host computer 50. In the present invention, the data filling unit 221 and the marking unit 223 are used to implement step S100. The task construction unit 224 and the programming unit 222 are used to implement step S200.

[0052] See also Figures 1 to 3 As shown, in one embodiment of the present invention, according to the logical address of the table to be rebuilt, the old data query unit 225 obtains the old table information of the table to be rebuilt from the first-level address mapping table, wherein the old table information includes the address mapping information when the table to be rebuilt was last edited. Specifically, the old data query unit 225 executes step S400 to query and obtain the first table to be merged. The old data query unit 225 is used to implement step S300. The scanning unit 226 reads the system block 42, and obtains the physical address range of the flash memory chip 40 related to the address mapping information according to the address mapping information stored in the system block 42, wherein the physical address range includes the initial address and the end address. The scanning unit 226 scans the storage page 411 between the initial address and the end address, and reconstructs the second-level address mapping table according to the address mapping information in the physical address range as the second table to be merged. The scanning unit 226 is used to implement step S400. The fusion reconstruction unit 227 merges the first table to be merged, the second table to be merged, and the third table to be merged as a fused second-level table. The secondary address mapping table in the system block 42 is replaced with the fused secondary table, thereby completing the reconstruction task. The fused reconstruction unit 227 is used to implement steps S500 to S600. Among them, when the reconstruction task is completed, the programming unit 222 deletes the reconstruction task from the task queue of the main controller 20. When there are multiple reconstruction tasks at the same time, the reconstruction tasks are executed in sequence from early to late in the order of the establishment time of the reconstruction tasks. When the to-be-reconstructed tables of some reconstruction tasks come from the same system block 42, the corresponding reconstruction tasks can be executed simultaneously. When the reconstruction task of the system block 42 is completed, the programming unit 222 removes the system block 42 from the bad block pool.

[0053] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A memory, characterized in that: include: A flash memory chip, the flash memory chip comprising a plurality of storage blocks, wherein some of the storage blocks are divided into system blocks, and the system blocks store a primary address mapping table and a secondary address mapping table; A cache module, electrically connected to the flash memory chip and the host computer, allowing the primary address mapping table and the secondary address mapping table to be edited in the cache module; an error correction module, electrically connected to the flash memory chip, and when editing the secondary address mapping table, if the secondary address mapping table reports an error and the error correction fails, the error correction module generates and sends error data; and A reconstruction module, electrically connected to the error correction module and receiving the error reporting data, wherein after the error correction module fails to correct an error, the reconstruction module generates a fused secondary table and replaces the secondary address mapping table in the system block with the fused secondary table; The fused secondary table includes the secondary address mapping table in the system block, the secondary address mapping table stored in the cache module, and address mapping information of the most recently edited user data in the system block.

2. A memory according to claim 1, characterized in that: The secondary address mapping table stores address mapping information of the user data, and the primary address mapping table stores address mapping information of the secondary address mapping table, wherein the address mapping information is a mapping relationship between a logical address and a physical address of the user data.

3. A memory according to claim 1, characterized in that: The reconstruction module includes a marking unit. When the secondary address mapping table reports an error and the error correction fails, the marking unit marks the secondary address mapping table that reports an error and the error correction fails as a table to be rebuilt, and records the serial number of the table to be rebuilt and the logical address of the table to be rebuilt.

4. A memory according to claim 3, characterized in that: The reconstruction module includes an old data query unit, which obtains old table information of the table to be rebuilt from the primary address mapping table according to the logical address of the table to be rebuilt, wherein the old table information includes the address mapping information of the table to be rebuilt when it was last edited.

5. A memory according to claim 1, characterized in that: The reconstruction module includes a scanning unit, which is electrically connected to the system block, allowing the scanning unit to read the system block and, based on the address mapping information stored in the system block, obtain a physical address range of the flash memory chip related to the address mapping information, wherein the physical address range includes an initial address and an end address, allowing the scanning unit to scan the physical address range and, based on the address mapping information in the physical address range, reconstruct a secondary address mapping table as the address mapping information of the most recently edited user data in the system block.

6. A memory according to claim 1, characterized in that: The reconstruction module includes a data filling unit, which stores single or multiple types of blank data. When the secondary address mapping table reports an error and error correction fails, the data filling unit is allowed to fill the blank data into the secondary address mapping table that reports an error and error correction fails, wherein the blank data is preset data.

7. A memory according to claim 6, characterized in that: The reconstruction module includes a programming unit. When the secondary address mapping table reports an error and the error correction fails, the programming unit is allowed to transfer the secondary address mapping table filled with the blank data to the cache module, and the programming unit is allowed to transfer the erroneous system block to the bad block pool. After completing the programming task, the programming unit generates a task construction indication signal.

8. A memory according to claim 7, characterized in that: The reconstruction module comprises a task construction unit, which receives the task construction indication signal and establishes a reconstruction task in the task queue of the memory, wherein the priority of the reconstruction task is lower than the instruction task of the host computer.

9. The memory according to claim 1, characterized in that: The system block also stores an erase count record table, a read count record table, and a valid data number record table, as well as the secondary address mapping table transferred from the cache module, wherein the erase count record table stores the erase counts of multiple storage blocks, the read count record table stores the read counts of multiple storage blocks, and the valid data number record table stores the valid data counts of multiple storage blocks.

10. A memory control method, based on the memory according to claim 1, characterized in that: The following steps are involved: When reading and writing user data, generating a secondary address mapping table according to the address mapping information of the user data; According to the logical address of the secondary address mapping table, read the secondary address mapping table with the same logical address from the flash memory chip into the cache module, and edit the secondary address mapping table and the primary address mapping table in the cache module; When editing the secondary address mapping table, if the secondary address mapping table reports an error and the error correction fails, the error correction module generates and sends error reporting data; and The reconstruction module receives the error data, and after the error correction module fails to correct the error, the reconstruction module generates a fused secondary table according to the secondary address mapping table in the system block, the secondary address mapping table stored in the cache module, and the address mapping information of the most recently edited user data in the system block; as well as The fused secondary table replaces the secondary address mapping table in the system block that reports an error and fails error correction.

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