Automatic optimization method and system for PCB board splitting path based on machine learning

Abstract

The present application discloses a method and system for automatic optimization of PCB panel splitting paths based on machine learning, the method comprising: collecting PCB panel splitting data; extracting features from PCB panel splitting data using feature engineering methods; constructing and training a hyperbolic space classification-aware continuous semantic segmentation model; inputting the feature set of PCB panel splitting data into a machine learning model to generate a first PCB panel splitting path; generating a d‑DNNF circuit using a d‑DNNF compiler, and optimizing the first PCB panel splitting path using the d‑DNNF circuit to generate a second PCB panel splitting path. The present application also provides a corresponding system. The method and system realize intelligent optimization of PCB panel splitting paths by combining machine learning and logical reasoning techniques, improve panel splitting accuracy and efficiency, reduce material waste, and provide an efficient and accurate panel splitting solution for the PCB manufacturing industry.

Description

Technical Field

[0001] The present application relates to the technical field of printed circuit board manufacturing, and in particular to a method and system for automatically optimizing a PCB panel splitting path based on machine learning. Background Art

[0002] In the PCB manufacturing process, panel separation is a key step, which directly affects the quality and production efficiency of the product. Traditional PCB panel separation path planning mainly relies on manual experience or simple algorithms. These methods often have difficulty in finding the optimal panel separation path in complex PCB layouts. With the increasing complexity and miniaturization of PCB design, traditional methods face the following problems:

[0003] Insufficient panel separation accuracy: Manual planning is prone to errors, affecting product quality.

[0004] Inefficiency: Simple algorithms have difficulty handling complex layouts, are time-consuming and inefficient.

[0005] These problems lead to increased PCB production costs, unstable product quality, and difficulty in meeting the high requirements of modern electronic product manufacturing. Summary of the invention

[0006] In view of this, the present application provides a method and system for automatic optimization of PCB panel splitting paths based on machine learning, which solves the problems of low accuracy, poor efficiency and weak adaptability of PCB panel splitting path planning in the prior art.

[0007] The present application embodiment provides a method for automatically optimizing a PCB board splitting path based on machine learning, comprising:

[0008] Collect PCB sub-board data;

[0009] Using feature engineering methods to extract features from the PCB panel data;

[0010] Constructing and training a machine learning model, wherein the machine learning model is a hyperbolic space classification-aware continuous semantic segmentation model;

[0011] Inputting the feature set of the PCB panel splitting data into the machine learning model to generate a first PCB panel splitting path;

[0012] A d-DNNF circuit is generated by using a d-DNNF compiler, and the d-DNNF circuit is used to optimize the first PCB board splitting path to generate a second PCB board splitting path.

[0013] The feature engineering method is used to extract features from the PCB panel data, including:

[0014] The PCB panel data is subjected to feature classification and decomposed into an image feature subset, a numerical feature subset and a text feature subset;

[0015] Calculate the marginal contribution of each feature in different feature subsets, and obtain the Shapley value of each feature based on the marginal contribution, wherein the Shapley value is used to characterize the importance of the feature;

[0016] Based on the Shapley value of each feature, rank the importance of each feature;

[0017] Through the alignment algorithm, the features of different modalities are mapped to a unified feature space.

[0018] Calculate the marginal contribution of each feature in different feature subsets, and based on the marginal contribution, obtain the Shapley value of each feature, including:

[0019] Use convolutional neural networks to extract a subset of image features of PCB layouts;

[0020] Obtain the numerical feature subset and text feature subset of PCB production parameters;

[0021] For each feature, consider its marginal contribution in different feature subsets;

[0022] The Shapley value of each feature is approximately calculated using permutation sampling.

[0023] After mapping the features of different modalities to a unified feature space, the method further includes:

[0024] In the feature space, principal component analysis (PCA) is used to reduce the dimensionality of high-dimensional features;

[0025] LASSO regularization is applied, and the Shapley value of each feature is combined to screen out a feature set whose correlation is higher than a first threshold and whose importance is higher than a second threshold. The feature set is the feature set to be input into the machine learning model.

[0026] Construct and train a machine learning model, which is a hyperbolic space classification-aware continuous semantic segmentation model, including:

[0027] A hyperbolic space metric model is defined, wherein the hyperbolic space metric is a Poincare sphere model;

[0028] Construct a hyperbolic spatial convolutional neural network architecture and back-propagation algorithm;

[0029] Define a state space and an action space, wherein the state space is the PCB board state, and the action space is the PCB board separation operation;

[0030] Designing a reward function based on building PCB depaneling quality evaluation indicators, wherein the indicators include depaneling accuracy, depaneling efficiency, and material utilization rate;

[0031] Historical PCB panel sub-board data is used for supervised learning pre-training, and K-fold cross validation is used to evaluate the performance of the model.

[0032] Inputting the feature set of the PCB panel splitting data into the machine learning model to generate a first PCB panel splitting path, including:

[0033] Inputting the feature set of the PCB panel data into the hyperbolic space classification-aware continuous semantic segmentation model;

[0034] Perform forward propagation to generate the first PCB board splitting path suggestion;

[0035] Converting the first PCB depaneling path suggestion into actual depaneling path coordinates;

[0036] A smoothing algorithm is applied to smooth the panel separation path to form the first PCB panel separation path.

[0037] Generating a d-DNNF circuit using a d-DNNF compiler, and optimizing the first PCB board splitting path using the d-DNNF circuit to generate a second PCB board splitting path, including:

[0038] Convert the first PCB board splitting path into a Boolean expression;

[0039] Inputting the Boolean expression into the d-DNNF compiler to generate a d-DNNF circuit;

[0040] In the d-DNNF circuit, detecting and removing Tseitin variables and Tseitin artifacts to simplify the d-DNNF circuit;

[0041] Probabilistic reasoning is performed based on the simplified d-DNNF circuit to optimize the first PCB board splitting path to generate the second PCB board splitting path.

[0042] In the d-DNNF circuit, detecting and removing Tseitin variables and Tseitin artifacts includes:

[0043] Identifying Tseitin variables, wherein the Tseitin variables are auxiliary variables introduced by the markers during the conversion process of the d-DNNF compiler;

[0044] traversing the d-DNNF circuit, identifying a subcircuit containing only Tseitin variables, and locating Tseitin artifacts in the subcircuit;

[0045] Starting from the leaf nodes, Tseitin variables and Tseitin artifacts are removed layer by layer.

[0046] Probabilistic reasoning is performed based on the simplified d-DNNF circuit to optimize the first PCB board separation path, including:

[0047] Assigning prior probabilities to line segments of the first PCB board separation path;

[0048] Perform probabilistic reasoning using bottom-up probability computation;

[0049] Based on the probabilistic reasoning results, the optimal board partitioning path combination is selected.

[0050] The embodiment of the present application also provides a method system for automatically optimizing a PCB board splitting path based on machine learning, including:

[0051] Collection module, used to collect PCB sub-board data;

[0052] A feature extraction module is used to extract features from the PCB panel data using a feature engineering method;

[0053] A construction module is used to construct and train a machine learning model, wherein the machine learning model is a hyperbolic space classification-aware continuous semantic segmentation model;

[0054] A generating module, used for inputting the feature set of the PCB panel data into the machine learning model to generate a first PCB panel path;

[0055] The optimization module is used to generate a d-DNNF circuit using a d-DNNF compiler, and optimize the first PCB board splitting path using the d-DNNF circuit to generate a second PCB board splitting path.

[0056] The present application also provides a computer device, the computer device comprising:

[0057] at least one processor; and,

[0058] a memory communicatively connected to the at least one processor; wherein,

[0059] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the above-mentioned automatic optimization method of PCB board sub-board paths based on machine learning.

[0060] An embodiment of the present application also provides a computer-readable storage medium, which stores computer instructions, and the computer instructions are used to enable a computer to execute the above-mentioned automatic optimization method of PCB board sub-path based on machine learning.

[0061] An embodiment of the present application also provides a computer program product, including computer instructions, characterized in that when the computer instructions are executed by a processor, the steps of the above-mentioned method for automatic optimization of PCB board sub-board paths based on machine learning are implemented.

[0062] This application has the following technical effects:

[0063] 1. Improve the accuracy of PCB depaneling: Through machine learning models and d-DNNF circuit optimization, more accurate PCB depaneling paths can be generated to reduce human errors.

[0064] 2. Improve efficiency: The automated optimization process significantly reduces manual planning time and speeds up PCB production.

[0065] 3. Optimize material utilization: Intelligent algorithms take into account material utilization and reduce material waste during PCB production.

[0066] 4. Enhanced adaptability: The machine learning model can adapt to different types of PCB designs, improving the versatility of the system.

[0067] 5. Continuous improvement: By continuously learning from historical data, the system can continuously optimize its performance and improve the quality of PCB depaneling.

[0068] 6. Reduce costs: By improving efficiency and reducing material waste, the cost of PCB production is effectively reduced.

[0069] 7. Intelligent decision support: It provides intelligent decision support for the PCB production process and improves the production management level. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Figure 1 A flowchart of a method for automatically optimizing a PCB board splitting path based on machine learning provided in an embodiment of the present application;

[0071] Figure 2 A structural diagram of a d-DNNF circuit provided in an embodiment of the present application;

[0072] Figure 3 The optimized d-DNNF circuit structure provided in the embodiment of the present application;

[0073] Figure 4 A schematic diagram of a first PCB board splitting path provided in an embodiment of the present application;

[0074] Figure 5 A schematic diagram of a second PCB board splitting path provided in an embodiment of the present application;

[0075] Figure 6A module structure diagram of a PCB board splitting path automatic optimization method system based on machine learning provided in an embodiment of the present application;

[0076] Figure 7 A module structure diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0077] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. In addition, the technical features involved in each embodiment of the present application described below can be combined with each other as long as they do not conflict with each other.

[0078] Figure 1 FIG. 1 is a flow chart of a method for automatically optimizing a PCB board splitting path based on machine learning in an embodiment of the present invention. Figure 1 As shown, the embodiment of the present invention includes the following steps:

[0079] S 1: Collect PCB sub-board data.

[0080] In this step, the system collects various data related to PCB depaneling. This data comes from multiple sources, including but not limited to:

[0081] 1.1 PCB design file: contains detailed layout information of PCB, such as circuit routing, component locations, etc.

[0082] 1.2 Production parameters: such as board type, thickness, number of layers, etc.

[0083] 1.3 Historical board splitting records: including past successful and failed board splitting path data.

[0084] 1.4 Quality control data: records the success rate and defect rate of different panel separation schemes.

[0085] 1.5 Equipment parameters: such as performance parameters and working range of the board splitter.

[0086] During the data collection process, it is necessary to ensure the integrity and accuracy of the data. This can be done by establishing an automated data collection system or using IoT technology to collect data on the production line in real time. At the same time, in order to protect sensitive information, the collected data needs to be anonymized and encrypted.

[0087] S 2: Extract features from the PCB panel data using a feature engineering method.

[0088] Feature extraction is key to the performance of machine learning models. This step aims to extract the most relevant and informative features from the raw PCB depaneling data. It includes the following sub-steps:

[0089] S 2.1: Feature classification is performed on the PCB panel data to decompose the data into an image feature subset, a numerical feature subset, and a text feature subset.

[0090] The purpose of this step is to process different types of data separately to facilitate subsequent feature extraction and processing. This can be done in the following ways:

[0091] Image feature subset: including PCB layout diagram, component distribution diagram, etc.

[0092] Numerical feature subset: includes quantitative data such as board size, thickness, number of layers, and number of components.

[0093] Text feature subset: includes text information such as PCB model, material description, and production precautions.

[0094] S 2.2: Calculate the marginal contribution of each feature in different feature subsets, and obtain the Shapley value of each feature based on the marginal contribution, where the Shapley value is used to characterize the importance of the feature.

[0095] The Shapley value is derived from game theory and is used to measure the contribution (importance) of each feature to model prediction. The calculation steps are as follows:

[0096] S 2.2.1: Extract a subset of image features of PCB layout using convolutional neural networks.

[0097] Pre-trained CNN models, such as ResNet or VGG, can be used to extract high-level features of PCB layout drawings.

[0098] For the unique features of PCB, special convolution kernels can be designed to capture features such as circuit traces and pads.

[0099] Specifically, the embodiment of the present application uses a specially designed convolutional neural network (CNN) to extract features of PCB layout images. This CNN model needs to take into account the particularity of PCB images, including its complex circuits, multi-layer structures, and various components. The following are the specific steps:

[0100] A1. Image preprocessing:

[0101] Resize the PCB layout images to a fixed size, such as 1024x1024 pixels.

[0102] Normalize the image and scale the pixel values ​​to the range 0-1.

[0103] Apply data augmentation techniques such as rotation, flipping, brightness adjustment, etc. to increase the robustness of the model.

[0104] A2. CNN architecture design:

[0105] Input layer: accepts the preprocessed PCB image with a size of 1024x1024x3 (RGB three channels).

[0106] Sequence of convolutional layers:

[0107] a. First convolutional layer: 64 3x3 convolution kernels, stride 1, padding 'same'.

[0108] b. Second convolutional layer: 128 3x3 convolution kernels with a stride of 2.

[0109] c. The third convolutional layer: 256 3x3 convolution kernels, stride 1, padding 'same'.

[0110] d. Fourth convolutional layer: 512 3x3 convolution kernels with a stride of 2.

[0111] Each convolutional layer is followed by a batch normalization layer and a ReLU activation function.

[0112] A max pooling layer with a pooling size of 2x2 is added after the second and fourth convolutional layers.

[0113] A3. Special convolution kernel design:

[0114] In order to better capture the unique features of PCB, a special convolution kernel is designed:

[0115] a. Line detection convolution kernel: used to detect small lines on PCB, with sizes of 1x5 and 5x1.

[0116] b. Pad detection convolution kernel: used to detect circular or square pads, size is 5x5.

[0117] c. Component detection convolution kernel: used to detect large components, size is 7x7.

[0118] A4. Attention Mechanism:

[0119] A spatial attention module is introduced to help the model focus on key areas in PCB images.

[0120] Use channel attention mechanisms, such as the Squeeze-and-Excitation module, to enhance the weights of important feature channels.

[0121] A5. Multi-scale feature fusion:

[0122] The feature pyramid network (FPN) structure is used to fuse feature maps of different scales.

[0123] This helps capture both the global layout and local details of the PCB.

[0124] A6. Feature extraction:

[0125] After the last convolutional layer of CNN, a global average pooling (GAP) layer is used.

[0126] The GAP layer outputs a feature vector of fixed size, such as 512 dimensions.

[0127] A7. Dimensionality reduction and feature selection:

[0128] Principal component analysis (PCA) is applied to the 512-dimensional feature vector to reduce it to 128 dimensions.

[0129] L1 regularization (LASSO) is used for feature selection to further reduce the number of features to 64 dimensions.

[0130] A8. Model training:

[0131] Use a large amount of labeled PCB image data for training.

[0132] The cross entropy loss function and Adam optimizer are used.

[0133] The learning rate is initially set to 0.001, and a learning rate decay strategy is used.

[0134] Use early stopping to prevent overfitting and stop training when the performance on the validation set no longer improves.

[0135] A9. Model evaluation and fine-tuning:

[0136] The model performance was evaluated using confusion matrix, precision, recall, and F1 score.

[0137] By visualizing the activation map of the convolutional layer, we can analyze the focus of the model and adjust the model structure accordingly.

[0138] A10. Feature explanation:

[0139] Use techniques such as Grad-CAM to generate heat maps that show the areas of the PCB that the model is focusing on.

[0140] These visualizations can help engineers understand and validate the model’s decision-making process.

[0141] Through this carefully designed CNN model, the embodiment of the present application can effectively extract the key features of the PCB layout image and provide high-quality input data for subsequent board splitting path optimization. This method can not only capture the complex structure of the PCB, but also adapt to PCB designs of different types and sizes, improving the versatility and robustness of the entire system.

[0142] S 2.2.2: Obtain numerical feature subsets and text feature subsets of PCB production parameters.

[0143] For numerical features, you can use the original value directly or perform standardization.

[0144] For text features, word embedding techniques such as Word2Vec or BERT can be used to convert text into numerical vectors.

[0145] S 2.2.3: For each feature, consider its marginal contribution in different feature subsets.

[0146] Marginal contribution refers to the improvement in model performance when adding a feature to the existing features.

[0147] S 2.2.4: Use permutation sampling to approximate the Shapley value of each feature.

[0148] Since the exact calculation of the Shapley value is very complex, the embodiment of the present application uses a permutation sampling method for approximate calculation.

[0149] The complexity of Shapley value calculation increases exponentially with the number of features, so for high-dimensional feature space (for example, greater than 3 dimensions), accurate calculation is unrealistic. Permutation sampling method is an efficient approximate calculation method. Specifically include:

[0150] 1. Definition of Shapley value: For feature i, its Shapley value is:

[0151] φi = Σ(S⊆N\{i}) [|S|!(n-|S|-1)! / n!] * [v(S∪{i}) v(S)];

[0152] Where N is the set of all features, n is the total number of features, and v is the value function.

[0153] 2. Implementation of permutation sampling algorithm:

[0154] a. Initialization:

[0155] Set the sampling times M (e.g. M=1000);

[0156] Create an array of length n to store the cumulative sum of the Shapley values ​​of each feature;

[0157] b. Sampling cycle:

[0158] for m = 1 to M:

[0159] Generate a random permutation π of features;

[0160] Initialize the prefix feature set S to an empty set;

[0161] for i = 1 to n:

[0162] Calculate the marginal contribution of feature π(i):

[0163] mc = v(S∪{π(i)}) v(S)

[0164] Update the cumulative sum of Shapley values ​​of feature π(i):

[0165] shapley_sum[π(i)] += mc

[0166] Add feature π(i) to the prefix feature set S;

[0167] c. Calculate the final Shapley value:

[0168] for i = 1 to n:

[0169] shapley[i] = shapley_sum[i] / M

[0170] 3. Design of value function v:

[0171] For the PCB depaneling problem, v can be defined as the improvement in model performance when certain features are included.

[0172] For example, v could be the classification accuracy or the R² value of a regression model when a particular set of features is included.

[0173] 4. Computational optimization:

[0174] Parallel computing: Use multithreading or distributed computing to process different permutations in parallel.

[0175] Incremental computation: In each permutation, v(S∪{i}) can be computed incrementally based on the results of v(S), rather than recomputing the entire model.

[0176] 5. Sampling strategy optimization:

[0177] Stratified sampling: Stratify the features according to their prior importance to ensure that important features are fully sampled.

[0178] Adaptive sampling: Dynamically adjust the sampling times and increase the sampling times for features with large variance of Shapley value estimation.

[0179] 6. Confidence Interval Estimation:

[0180] The confidence interval for each Shapley value was estimated using the Bootstrap method.

[0181] Calculate the standard error: SE(φi) = sqrt(Σ(φi,m-φi)² / (M(M-1)))

[0182] 95% confidence interval: [φi - 1.96*SE(φi), φi + 1.96*SE(φi)]

[0183] 7. Calculation of Shapley value of feature group:

[0184] For highly correlated feature groups, group Shapley values ​​can be calculated.

[0185] Treating related feature groups as a whole reduces computational complexity.

[0186] 8. Sparse Approximation:

[0187] For large feature sets, sparse approximation methods can be used.

[0188] Most feature interactions were assumed to be zero and only main interaction effects were calculated.

[0189] 9. Result verification:

[0190] The algorithm was run multiple times with different random seeds to ensure the stability of the results.

[0191] Compare with other feature importance methods (such as feature importance of random forest) to verify the rationality of the results.

[0192] 10. Interpretability Analysis:

[0193] Generate a bar chart or heat map of Shapley values ​​to visually display feature importance.

[0194] For the top important features, in-depth domain knowledge analysis is performed to explain their impact on PCB sub-paneling.

[0195] 11. Dynamic update mechanism:

[0196] In practical applications, the Shapley value is recalculated periodically to capture the dynamic changes in feature importance.

[0197] Set trigger conditions (such as model performance degradation) to automatically start the Shapley value recalculation process.

[0198] Through this sophisticated Shapley value calculation method, the embodiment of the present application can accurately evaluate the contribution of each feature to PCB sub-panel optimization. This not only helps feature selection and model interpretation, but also guides subsequent feature engineering and model optimization processes. At the same time, through various optimization techniques, the embodiment of the present application ensures computational efficiency in high-dimensional feature space, making this method highly practical in actual PCB production environments.

[0199] S 2.3: Rank the importance of each feature based on its Shapley value.

[0200] Sort all features by Shapley value from large to small. The larger the Shapley value, the greater the contribution of the feature to the model prediction.

[0201] S 2.4: Through the alignment algorithm, the features of different modalities are mapped to a unified feature space.

[0202] Use alignment algorithms such as CCA or deep alignment networks to map image, numerical, and text features into the same feature space.

[0203] The purpose of this step is to enable different types of features to be compared and fused in the same space.

[0204] Specifically, in the PCB panel optimization problem, the embodiment of the present application needs to process features from different modes, such as image features, numerical features, and text features. It is crucial to align these heterogeneous features into a unified feature space. The following are the specific steps:

[0205] 1. Feature preprocessing:

[0206] a. Image features: have been extracted by CNN, with a dimension of 64 (according to the previous setting).

[0207] b. Numerical features: Standardization processing to make the mean 0 and the variance 1.

[0208] c. Text features: Use the pre-trained BERT model to extract 768-dimensional text embeddings.

[0209] 2. Deep Canonical Correlation Analysis (DCCA):

[0210] Goal: Learn to map different modal features into a common low-dimensional space (e.g. within 3 dimensions).

[0211] Architecture:

[0212] For the features of each modality, a deep neural network is constructed.

[0213] Network structure: Input -> FC(256) -> ReLU -> Dropout(0.5) -> FC(128) -> ReLU-> Dropout(0.5) -> FC(64)

[0214] Loss function: maximize the correlation between features after mapping to different modalities.

[0215] Optimization: Use the Adam optimizer, set the learning rate to 0.001, and use the learning rate decay strategy.

[0216] 3. Multimodal fusion enhanced by attention mechanism:

[0217] a. Self-attention layer:

[0218] The self-attention mechanism is applied to each modality separately.

[0219] Use multi-head attention and the number of heads is set to 8.

[0220] b. Cross-modal attention:

[0221] Calculate the attention weights between different modalities.

[0222] Use scaled dot-product attention mechanism.

[0223] 4. Adversarial Feature Alignment:

[0224] Adversarial training is introduced to reduce the differences in feature distributions of different modalities.

[0225] Architecture:

[0226] Feature Extractor: Maps the features of each modality into a common space.

[0227] Discriminator: tries to distinguish which modality a feature comes from.

[0228] Training process:

[0229] Feature extractor goal: to fool the discriminator into being unable to distinguish the source modality of the features.

[0230] Discriminator goal: accurately identify the source mode of the feature.

[0231] 5. Recurrent Neural Network (RNN) based sequence alignment:

[0232] A bidirectional LSTM network is used to process the feature sequence of each modality.

[0233] Apply attention mechanism to aggregate sequence information.

[0234] 6. Graph Neural Network (GNN) based structure alignment:

[0235] Construct a cross-modal graph structure, where nodes represent the features of different modalities.

[0236] Use Graph Attention Network (GAT) for message passing and feature updating.

[0237] 7. Multi-task learning framework:

[0238] Main task: PCB board sub-path optimization.

[0239] Auxiliary task: reconstruct the original features of each modality.

[0240] Jointly optimize the loss functions of the main task and auxiliary tasks.

[0241] 8. Progressive training strategy:

[0242] a. Stage 1: Pre-train the feature extractor for each modality separately.

[0243] b. Stage 2: Preliminary alignment using DCCA.

[0244] c. Phase 3: Introducing attention mechanism and adversarial training.

[0245] d. Stage 4: fine-tune the entire model.

[0246] 9. Regularization Techniques:

[0247] L2 regularization: prevents the model from overfitting.

[0248] Manifold regularization: maintains the local structure of the original feature space.

[0249] 10. Metric Learning:

[0250] The triplet loss is used to enhance the discriminability of features.

[0251] Ensure that different modal features of the same PCB sample are closer in the alignment space.

[0252] 11. Zero-shot learning extension:

[0253] Designing a shared semantic space allows the model to handle PCB types not seen during training.

[0254] 12. Uncertainty Modeling:

[0255] Using a variational autoencoder (VAE) structure, a probability distribution is generated for each aligned feature.

[0256] This helps the model estimate the uncertainty in feature alignment.

[0257] 13. Dynamic Weight Balancing:

[0258] Implement a dynamic weight mechanism to automatically adjust the weight of each modality according to its importance in the current task.

[0259] 14. Incremental learning mechanism:

[0260] Design an architecture that can continuously absorb new modalities or new features without completely retraining the model.

[0261] 15. Interpretability Analysis:

[0262] The importance of different modal features in the alignment space is analyzed using SHAP (SHapley Additive exPlanations) values.

[0263] Visualize attention weights to understand how the model fuses information from different modalities.

[0264] 16. Evaluation indicators:

[0265] The canonical correlation coefficient (CCA) is used to measure the degree of alignment of features of different modalities.

[0266] Design alignment quality metrics specific to PCB depaneling tasks.

[0267] Through this complex and comprehensive feature alignment method, the embodiment of the present application can effectively unify the multimodal features (images, numerical values, text) in the PCB depaneling problem into a common feature space. This not only improves the performance of subsequent machine learning models, but also enhances the robustness and generalization ability of the model. At the same time, by introducing a variety of advanced technologies, such as attention mechanisms, adversarial training, and uncertainty modeling, the embodiment of the present application ensures the high quality and reliability of the feature alignment process, laying a solid foundation for the precise optimization of the PCB depaneling path.

[0268] S 2.5: In the feature space, principal component analysis (PCA) is used to reduce the dimensionality of high-dimensional features.

[0269] PCA can reduce the dimensionality of features while retaining the most important information.

[0270] Choosing an appropriate number of principal components can usually retain more than 95% of the variance.

[0271] S 2.6: Apply LASSO regularization and combine the Shapley value of each feature to screen out a feature set whose correlation is higher than the first threshold and whose importance is higher than the second threshold. The feature set is the feature set to be input into the machine learning model.

[0272] LASSO regularization can further filter features and remove redundant and unimportant features.

[0273] Combined with the Shapley value, features that are truly important for model prediction can be better retained.

[0274] The first threshold and the second threshold can be set to determine the optimal value through cross-validation.

[0275] Specifically, in S2.6, the purpose is to select the most relevant and important feature subset from a large number of features to improve the performance and interpretability of the model. The embodiment of the present application will combine LASSO regularization and Shapley value to achieve this goal.

[0276] 1. LASSO regularization implementation:

[0277] a. Model settings:

[0278] A linear regression model was used as the base model;

[0279] Target variable: PCB depaneling quality indicators (such as depaneling accuracy, efficiency, etc.)

[0280] Features: all aligned features;

[0281] b. LASSO objective function:

[0282] L(β) = 1 / (2n) * ||y Xβ||²2 + λ * ||β||1;

[0283] Where n is the number of samples, y is the target variable, X is the feature matrix, β is the coefficient vector, and λ is the regularization parameter;

[0284] c. Regularization parameter selection:

[0285] Use k-fold cross validation (e.g. k=5);

[0286] Set the candidate value range of λ, such as [0.001, 0.01, 0.1, 1, 10];

[0287] Choose the lambda value that gives the best performance on the validation set;

[0288] d. Model training:

[0289] Use coordinate descent method to optimize LASSO objective function;

[0290] Set the maximum number of iterations (such as 1000) and the convergence threshold (such as 1e-4);

[0291] e. Feature correlation calculation:

[0292] Correlation = |βᵢ| / max(|β|), where βᵢ is the LASSO coefficient of the i-th feature;

[0293] 2. Combination of Shapley value and LASSO:

[0294] a. Normalized Shapley value:

[0295] Divide the Shapley value of each feature by the maximum absolute value of all Shapley values;

[0296] normalized_shapley[i] = shapley[i] / max(|shapley|);

[0297] b. Calculation of comprehensive importance score:

[0298] For each feature i, calculate the comprehensive score:

[0299] score[i] = α * normalized_shapley[i] + (1 α) * correlation[i];

[0300] α is a hyperparameter used to balance the weight of Shapley value and LASSO correlation, which can be optimized by grid search;

[0301] 3. Feature screening:

[0302] a. Set the threshold:

[0303] The first threshold (correlation threshold): such as 0.05;

[0304] The second threshold (importance threshold): such as 0.1;

[0305] b. Screening rules:

[0306] Keep features i that satisfy the following conditions:

[0307] (correlation[i] > first threshold) AND (normalized_shapley[i] > second threshold);

[0308] c. Threshold optimization:

[0309] Use grid search to try different threshold combinations;

[0310] Evaluation criteria: model performance on the validation set (e.g. R² score);

[0311] 4. Stability analysis:

[0312] a. Perform Bootstrap sampling (e.g. 1000 times);

[0313] b. Repeat steps 1-3 for each Bootstrap sample;

[0314] c. Calculate the frequency of each feature being selected;

[0315] d. Keep the features whose selected frequency exceeds a certain threshold (such as 0.9);

[0316] 5. Multicollinearity processing:

[0317] a. Calculate the correlation coefficient matrix between the retained features;

[0318] b. For feature pairs whose absolute value of correlation coefficient is higher than a threshold (such as 0.8):

[0319] Features with higher comprehensive importance scores are retained;

[0320] Remove another feature;

[0321] 6. Capturing nonlinear relationships:

[0322] a. Use the random forest model to evaluate feature importance;

[0323] b. Compare the feature importance of random forest with the results of linear LASSO;

[0324] c. For features with significant differences, consider adding interaction terms or polynomial features;

[0325] 7. Feature explanation:

[0326] a. Generate a partial dependency graph (PDP) for each retained feature;

[0327] b. Calculate the SHAP (SHapley Additive exPlanations) value to analyze the impact of features on model predictions;

[0328] 8. Incremental Feature Selection:

[0329] a. Start with an empty feature set;

[0330] b. Gradually add features sorted by their comprehensive importance scores;

[0331] c. Evaluate the model performance at each step until the performance no longer improves significantly;

[0332] 9. Time series feature considerations:

[0333] a. For time-dependent features, calculate the importance of lagged features;

[0334] b. Use the autocorrelation function (ACF) and partial autocorrelation function (PACF) to assist in selecting the optimal lag order;

[0335] 10. Domain knowledge integration:

[0336] a. Discuss the screening results with PCB design experts;

[0337] b. Based on expert advice, some features may be manually added or deleted;

[0338] 11. Dynamic feature importance update:

[0339] a. Design an online learning mechanism to regularly update feature importance;

[0340] b. Use a sliding window approach to ensure that feature importance reflects the latest data patterns;

[0341] 12. Visualization and Reporting:

[0342] a. Generate feature importance heatmap;

[0343] b. Create a feature correlation network diagram;

[0344] c. Write a detailed feature selection report, including the rationale for the selection of each feature;

[0345] Through this comprehensive feature screening method, the embodiment of the present application can select the most relevant and important feature set in the PCB panel optimization problem. This not only improves the performance and efficiency of the subsequent machine learning model, but also enhances the interpretability and stability of the model. At the same time, by combining the linear correlation of LASSO and the nonlinear importance of Shapley value, the embodiment of the present application ensures the comprehensiveness and robustness of the feature selection process. This method is particularly suitable for dealing with complex engineering problems such as PCB panelization, where there may be complex interactions between features.

[0346] S 3: Construct and train a machine learning model, wherein the machine learning model is a hyperbolic space classification-aware continuous semantic segmentation model.

[0347] This step aims to build a machine learning model that can effectively handle the PCB depaneling problem. The choice of the hyperbolic space model is based on its advantages in processing hierarchical data, which matches the complex structure of the PCB. It includes the following sub-steps:

[0348] S 3.1: Define a hyperbolic space metric model, where the hyperbolic space metric is a Poincare sphere model.

[0349] The Poincare sphere model is a representation of hyperbolic geometry that can represent infinite hyperbolic space in a finite Euclidean space.

[0350] Define the Poincaré sphere B n = {x ∈ R n : ||x|| < 1};

[0351] In the Poincare sphere model, the distance is defined as:

[0352] d(u,v) = arcosh(1 + 2||uv|| 2 / ((1-||u|| 2 )(1-||v|| 2 )));

[0353] where u and v are points inside the Poincare sphere.

[0354] S 3.2: Construct the hyperbolic spatial convolutional neural network architecture and back-propagation algorithm.

[0355] Special convolutional layers are designed to operate in hyperbolic space.

[0356] Modify the activation function to adapt it to the geometry of hyperbolic space.

[0357] Specifically,

[0358] Define the hyperbolic layer:

[0359] Implement hyperbolic matrix multiplication ⊗_H; implement hyperbolic bias addition ⊕_H; combine hyperbolic matrix multiplication and bias addition to form a complete hyperbolic transformation.

[0360] Design a hyperbolic convolution layer: define the convolution kernel in the hyperbolic space; implement the sliding window operation in the hyperbolic space; combine the hyperbolic transformation to complete the hyperbolic convolution operation.

[0361] Implement hyperbolic activation functions: Design a hyperbolic ReLU function, implement the hyperbolic sigmoid function, and consider other possible hyperbolic activation functions such as hyperbolic tanh.

[0362] Design hyperbolic pooling layer: implement hyperbolic max pooling; implement hyperbolic average pooling; consider adaptive pooling strategy to handle irregular PCB shapes.

[0363] Build a complete network architecture: design the encoder part, use hyperbolic convolution and pooling layers; design the decoder part, use hyperbolic deconvolution (transposed convolution); add skip connections to fuse features of different scales.

[0364] The backpropagation algorithm is adapted to the gradient calculation in the Poincare sphere model.

[0365] The construction of the back-propagation algorithm includes:

[0366] Define hyperbolic gradient: implement Riemannian gradient calculation; convert Euclidean gradient to hyperbolic gradient; implement gradient clipping to ensure numerical stability.

[0367] Design a hyperbolic optimizer: Implement a hyperbolic version of stochastic gradient descent (SGD) and design a hyperbolic Adam optimizer; consider other optimization algorithms suitable for hyperbolic space, such as Riemannian Adam.

[0368] Implement hyperbolic backpropagation: compute the gradient of the loss function with respect to each layer’s output; use the chain rule to compute parameter gradients layer by layer; apply parallel propagation to ensure that gradients are correctly propagated between different points.

[0369] Parameter update strategy, use exponential mapping to update parameters to hyperbolic space, implement momentum method, accelerate convergence and avoid local minima, consider learning rate scheduling strategies such as cosine annealing.

[0370] Implement automatic differentiation: define forward and backward propagation rules for hyperbolic operations, integrate into existing deep learning frameworks (such as PyTorch or TensorFlow), optimize computational graphs, and improve backpropagation efficiency.

[0371] Through these detailed steps, the embodiment of the present application can construct a classification-aware continuous semantic segmentation model running in a hyperbolic space. This method is particularly suitable for processing PCB board separation problems because:

[0372] 1. Hyperbolic space can better represent the hierarchical structure and topological relationship of PCB design.

[0373] 2. The classification-aware feature enables the model to handle segmentation and classification tasks simultaneously, which helps to identify different types of PCB components.

[0374] 3. Continuous semantic segmentation can generate accurate board partitioning paths instead of just rough area divisions.

[0375] This innovative approach has the potential to significantly improve the optimization of PCB breakout paths, especially when dealing with complex, multi-layer PCB designs.

[0376] Exemplarily, the hyperbolic spatial convolutional neural network architecture and back propagation algorithm include:

[0377] 1. Network architecture design:

[0378] Input layer: receives PCB layout image with dimensions [batch size, number of channels, height, width].

[0379] Sequence of convolutional layers:

[0380] a. First hyperbolic convolution layer: 32 3x3 kernels, stride 1, padding 1.

[0381] b. Second hyperbolic convolution layer: 64 3x3 convolution kernels, stride 1, padding 1.

[0382] c. The third hyperbolic convolution layer: 128 3x3 convolution kernels, stride 1, padding 1.

[0383] Each convolutional layer is followed by a ReLU activation function and a max pooling layer (2x2 pooling).

[0384] Fully connected layer:

[0385] a. The first hyperbolic fully connected layer: the input dimension depends on the output of the previous convolutional layer, and the output is 256 dimensions.

[0386] b. Second hyperbolic fully connected layer: 256-dimensional input, output dimension is set according to task requirements.

[0387] 2. Hyperbolic spatial convolution layer implementation:

[0388] Input processing: Mapping the input from the hyperbolic space (Poincaré sphere model) to the tangent space.

[0389] Convolution operation: Perform standard convolution operation in the tangent space.

[0390] Output processing: Map the convolution result from the tangent space back to the hyperbolic space.

[0391] 3. Hyperbolic space fully connected layer implementation:

[0392] Similar to the convolutional layer, the input is first mapped to the tangent space.

[0393] Perform linear transformations in tangent space.

[0394] Map the result back to hyperbolic space.

[0395] 4. Activation function and pooling:

[0396] Use the standard ReLU activation function.

[0397] The max pooling operation is performed directly in the hyperbolic space.

[0398] 5. Loss function design:

[0399] A custom loss function that combines panelization accuracy and efficiency.

[0400] Accuracy: Hyperbolic distance is used to measure the difference between the predicted value and the target value.

[0401] Efficiency part: Use mean square error to measure the gap between efficiency and ideal efficiency.

[0402] Total loss: the weighted sum of accuracy loss and efficiency loss.

[0403] 6. Back Propagation Algorithm:

[0404] Compute the gradient using automatic differentiation.

[0405] Implement gradient clipping to prevent gradient explosion.

[0406] After each parameter update, the parameters are projected back onto the Poincaré sphere, ensuring that they are always in a valid hyperbolic space.

[0407] 7. Optimizer selection:

[0408] The Adam optimizer is used and the learning rate is initially set to 0.001.

[0409] Implement a learning rate decay strategy to improve training stability.

[0410] 8. Training process:

[0411] Iterate through forward propagation, loss calculation, backpropagation, and parameter update.

[0412] Regularly evaluate model performance on the validation set.

[0413] Implement early stopping mechanism to prevent overfitting.

[0414] 9. Model Evaluation:

[0415] Evaluate model performance using specially designed PCB depaneling quality metrics.

[0416] Compare the performance differences between the hyperbolic space model and the traditional Euclidean space model.

[0417] 10. Visualization and Interpretation:

[0418] Visualize the distribution of features in hyperbolic space.

[0419] Analyze the impact of the representation learned by the model in hyperbolic space on PCB panelization optimization.

[0420] This hyperbolic space convolutional neural network architecture is particularly suitable for dealing with complex hierarchical problems such as PCB depaneling. It can represent richer relationships in a limited parameter space, which helps capture the subtle features and overall structure of the PCB layout, thereby generating more accurate depaneling paths. At the same time, by keeping the parameters in the hyperbolic space during the training process, the stability and consistency of the model are ensured.

[0421] S 3.3: Define a state space and an action space, wherein the state space is the PCB board state, and the action space is the PCB board separation operation.

[0422] State space: includes the current PCB layout, the divided parts, the remaining parts to be divided, etc.

[0423] Action space: including the position and direction of the dividing line, cutting tool selection, etc.

[0424] S 3.4: Design a reward function based on constructing PCB depaneling quality evaluation indicators, wherein the indicators include depaneling accuracy, depaneling efficiency, and material utilization.

[0425] Panel separation accuracy: evaluates the deviation of the separation line from the ideal position.

[0426] Depaneling efficiency: Consider the time and number of operations required to complete depaneling.

[0427] Material utilization: Calculate the waste ratio and effective PCB area ratio.

[0428] The reward function can be a weighted sum of these metrics, with the weights adjustable through experiments.

[0429] S 3.5: Use historical PCB panel data for supervised learning pre-training and use K-fold cross validation to evaluate the performance of the model.

[0430] Use the collected historical data for initial training to help the model converge quickly.

[0431] K-fold cross validation (such as K=5 or 10) is used to evaluate the generalization ability of the model.

[0432] According to the verification results, the model structure and hyperparameters are adjusted.

[0433] It should be noted that this step specifically includes:

[0434] 1. Data preparation:

[0435] a. Collect historical PCB sub-board data, including:

[0436] PCB layout image (normalized to 256x256 pixels);

[0437] Panel separation parameters (such as panel thickness, material type);

[0438] Successful board split paths (as labels);

[0439] Quality indicators of panel separation (such as accuracy, efficiency, and material utilization);

[0440] b. Data cleaning:

[0441] Remove outliers and incomplete data;

[0442] Handling missing values ​​(e.g. using mean filling or advanced interpolation methods);

[0443] c. Data augmentation:

[0444] Rotate, flip, and scale images;

[0445] Add noise to improve model robustness;

[0446] d. Feature Engineering:

[0447] Extract relevant features (e.g. edge density, component distribution) from PCB images;

[0448] Standardize or normalize numerical features;

[0449] 2. Dataset division:

[0450] a. Randomly divide the dataset into training set (70%), validation set (15%) and test set (15%);

[0451] b. Ensure that the sample distribution in each subset is similar (using stratified sampling);

[0452] 3. Model Architecture:

[0453] a. Input layer: receives processed PCB images and panel separation parameters;

[0454] b. Convolutional layer: uses convolution operations defined in hyperbolic space;

[0455] c. Pooling layer: performs maximum pooling operation in hyperbolic space;

[0456] d. Fully connected layer: uses linear transformation in hyperbolic space;

[0457] e. Output layer: predict the board splitting path and quality indicators;

[0458] 4. Loss function design:

[0459] a. Path prediction loss: using distance metric in hyperbolic space;

[0460] b. Quality indicator prediction loss: mean square error (MSE);

[0461] c. Total loss = α * path prediction loss + (1-α) * quality index prediction loss;

[0462] Where α is the balance factor, which can be tuned through the validation set;

[0463] 5. Optimizer selection:

[0464] Use the Adam optimizer, and the initial learning rate is set to 0.001;

[0465] Implement a learning rate decay strategy, such as decaying by 10% every 10 epochs;

[0466] 6. Training process:

[0467] a. Initialize model parameters (using He initialization);

[0468] b. For each epoch:

[0469] Perform forward propagation and back propagation on the training set;

[0470] Update model parameters;

[0471] Evaluate model performance on the validation set;

[0472] c. Implement an early stopping mechanism: if the performance of the validation set does not improve for 5 consecutive epochs, stop training;

[0473] d. Save the best model (the one with the best performance on the validation set);

[0474] 7. K-fold cross validation (assuming K=5):

[0475] a. Randomly divide the training set into 5 subsets of equal size;

[0476] b. Perform 5 training-validation cycles:

[0477] Each time, 4 subsets are used as training data and 1 subset is used as validation data;

[0478] Train the model and record performance metrics;

[0479] c. Calculate the average performance index and standard deviation of 5 cycles;

[0480] 8. Performance evaluation indicators:

[0481] a. For board path prediction:

[0482] Mean hyperbolic distance error;

[0483] Path overlap rate (the degree of overlap between the predicted path and the true path);

[0484] b. For quality indicator prediction:

[0485] Root mean square error (RMSE);

[0486] R² score;

[0487] c. Comprehensive indicators:

[0488] F1 score (treating path prediction as a classification problem);

[0489] Customized PCB sub-panel quality scores;

[0490] 9. Model tuning:

[0491] a. Use grid search or random search to optimize hyperparameters, such as:

[0492] Learning rate;

[0493] Batch size;

[0494] The number of network layers and neurons;

[0495] Regularization strength;

[0496] b. Perform K-fold cross validation on each set of hyperparameters and select the configuration with the best average performance;

[0497] 10. Model Interpretation Analysis:

[0498] a. Visualize the activation map of the convolutional layer to understand the PCB area that the model focuses on;

[0499] b. Analyze feature importance using SHAP (SHapley Additive exPlanations) values;

[0500] c. Generate a partial dependency plot (PDP) to understand the impact of specific features on the prediction;

[0501] 11. Robustness test:

[0502] a. Evaluate the final model performance on the test set;

[0503] b. Use different types of PCB data to test the generalization ability of the model;

[0504] c. Conduct adversarial testing to evaluate the model’s sensitivity to input perturbations;

[0505] 12. Continuous learning mechanism:

[0506] a. Design incremental learning schemes that allow models to adapt to new data without retraining;

[0507] b. Implement model version control to facilitate rollback and A / B testing;

[0508] 13. Deployment preparation:

[0509] a. Model compression (such as knowledge distillation or pruning) to adapt to actual production environments;

[0510] b. Convert the model to a format suitable for deployment (such as ONNX);

[0511] c. Design monitoring mechanisms to track the performance of the model in actual use;

[0512] Through this comprehensive pre-training and evaluation process, the embodiment of the present application can build a PCB board path optimization model that performs well on historical data and has good generalization ability. K-fold cross validation ensures that the estimation of model performance by the embodiment of the present application is reliable and is not affected by specific data partitioning. At the same time, through various analyses and tests, the embodiment of the present application can deeply understand the behavior of the model, providing an important basis for subsequent improvements and practical applications. This method not only improves the accuracy and reliability of the model, but also enhances its applicability in the actual PCB manufacturing process.

[0513] S 4: Inputting the feature set of the PCB panel splitting data into the machine learning model to generate a first PCB panel splitting path.

[0514] This step is to apply the previously extracted and processed features to the trained model to generate a preliminary PCB board splitting path. Specifically include:

[0515] S 4.1: Inputting the feature set of the PCB panel data into the hyperbolic space classification-aware continuous semantic segmentation model.

[0516] Make sure the format of your input features matches the model input layer.

[0517] Perform necessary normalization on the features.

[0518] S 4.2: Perform forward propagation to generate the first PCB panel path suggestion.

[0519] The model output is a probability distribution that represents the probability of each sub-plate position.

[0520] For example, it is assumed that the embodiment of the present application has a rectangular PCB board with a size of 200mm x 150mm, which needs to be divided into 4 small boards (2x2 layout).

[0521] 1. Input preparation:

[0522] Convert the image of the PCB board to a grayscale image of 256x256 pixels.

[0523] Other relevant features, such as board thickness, material type, component distribution, etc., are extracted to form a feature vector.

[0524] 2. Model input:

[0525] Image features: 256x256x1 tensor;

[0526] Other features: a vector containing 20 elements (assuming that there are 20 additional relevant features in this embodiment of the application);

[0527] 3. Forward propagation process:

[0528] a. Convolutional layer processing:

[0529] The first convolutional layer: extracts basic edge and shape features;

[0530] Second convolutional layer: recognizes more complex patterns, such as component outlines;

[0531] The third convolutional layer: captures the overall layout features;

[0532] b. Fully connected layer processing:

[0533] Combine convolutional features with other input features;

[0534] Perform nonlinear transformations in hyperbolic space;

[0535] c. Output layer:

[0536] Generate a 256x256x1 heat map, indicating the probability of each pixel being a segmentation line;

[0537] 4. Output explanation:

[0538] The high-value areas in the heat map indicate the locations of the split lines suggested by the model;

[0539] For example, two distinct bands of high values ​​may appear at x ≈ 128 and y ≈ 96;

[0540] 5. Post-processing:

[0541] Apply a threshold, such as taking the top 10% of high-value points in the heat map;

[0542] Use Hough transform to detect straight lines and find the most likely segmentation line;

[0543] The result might be two vertical lines: x = 100mm and y = 75mm;

[0544] 6. Preliminary board splitting path suggestions:

[0545] Horizontal cutting line: in the center of the board (y = 75 mm);

[0546] Vertical cutting line: in the center of the board (x = 100mm);

[0547] Cutting order recommendations: horizontal first, then vertical, or vertical first, then horizontal;

[0548] 7. Visualization:

[0549] Overlay the heat map on the original PCB image;

[0550] Draw suggested cutting lines and use different colors to indicate cutting priority;

[0551] 8. Confidence Assessment:

[0552] Give a confidence score for each proposed cut line;

[0553] For example: the confidence level of the horizontal cutting line is 92%, and the confidence level of the vertical cutting line is 88%;

[0554] 9. Potential Problems:

[0555] Mark potential problem areas, such as densely packed components near the cut line;

[0556] 10. Alternative solutions:

[0557] The model may also output suboptimal cutting solutions if the primary suggestion is not feasible;

[0558] For example, asymmetrical cutting: x = 95mm and y = 80mm.

[0559] This example shows how the model can transform complex PCB data into specific splitting path suggestions through forward propagation. It not only provides cutting locations, but also includes information such as confidence, potential problems and alternatives, providing a comprehensive reference for subsequent optimization and manual decision-making. The advantage of this method is that it can comprehensively consider multiple features of the PCB, including visual information and non-visual attributes, to provide more intelligent and reliable splitting suggestions.

[0560] S 4.3: Convert the first PCB depaneling path suggestion into actual depaneling path coordinates.

[0561] Convert the probability distribution of the model output into a specific sequence of coordinate points.

[0562] Threshold processing is required to retain only the few board locations with the highest probability.

[0563] S 4.4: Apply a smoothing algorithm to smooth the panel separation path to form the first PCB panel separation path.

[0564] Use smoothing algorithms such as B-spline or Bezier curves to make the board splitting path smoother and more continuous.

[0565] Make sure the smoothed paths still meet the physical constraints of the PCB breakout.

[0566] S 5: Generate a d-DNNF circuit using a d-DNNF compiler, and optimize the first PCB board splitting path using the d-DNNF circuit to generate a second PCB board splitting path.

[0567] This step introduces d-DNNF (Deterministic Decomposable Negation Normal Form) technology to further optimize the board splitting path. d-DNNF is a logical representation form that is particularly suitable for efficient probabilistic reasoning. The specific steps are as follows:

[0568] S 5.1: Convert the first PCB panel splitting path into a Boolean expression.

[0569] Represent the partition path as a series of Boolean variables and constraints.

[0570] For example, a PCB board can be divided into grids, and each grid point is represented by a Boolean variable to indicate whether it is a board separation point.

[0571] S 5.2: Input the Boolean expression into the d-DNNF compiler to generate a d-DNNF circuit.

[0572] Use an existing d-DNNF compiler, such as c2d or DSHARP, to convert the Boolean expression into d-DNNF form.

[0573] The d-DNNF form is deterministic and decomposable, which is beneficial for subsequent optimization operations.

[0574] S 5.3: In the d-DNNF circuit, detect and delete Tseitin variables and Tseitin artifacts to simplify the d-DNNF circuit.

[0575] S 5.3.1: Identify Tseitin variables, which are auxiliary variables introduced by the markers during the conversion process of the d-DNNF compiler.

[0576] The Chinese translation of “Tseitin variable” is “Cai Ting variable” or “Tseitin dependent variable”.

[0577] Tseitin transformation (Tseytin transformation or Tseitin transform) is a method to convert any combinational logic circuit into a conjunctive normal form (CNF) Boolean formula. In this transformation process, some new variables are introduced, which are called Tseitin variables.

[0578] The main advantage of Tseitin transformation is that the size of the output formula grows linearly with respect to the size of the input circuit, avoiding the problem of exponential growth of the equation size that may result from directly writing the circuit as a Boolean expression and then converting it to CNF. It has certain applications in the circuit satisfiability problem (SAT) and related logical reasoning and computing fields.

[0579] For example, for each logic gate, a new variable representing its output is introduced, which is the Tseitin variable. By introducing these variables and appending some pre-computed small CNF expressions related to the input and output, the entire output expression can be constructed, thus transforming the circuit satisfiability problem into a satisfiability solution for the CNF formula.

[0580] Tseitin variables are usually introduced when converting complex Boolean expressions to CNF (Conjunctive Normal Form). These variables introduce unnecessary complexity in the d-DNNF structure.

[0581] S 5.3.2: Traverse the d-DNNF circuit, identify subcircuits containing only Tseitin variables, and locate Tseitin artifacts in the subcircuits.

[0582] Tseitin artifact refers to the circuit structure that is generated by the introduction of Tseitin variables and has no substantial effect on the original problem.

[0583] S 5.3.3: Starting from the leaf nodes, remove Tseitin variables and Tseitin artifacts layer by layer.

[0584] This step can significantly simplify the d-DNNF circuit and improve the efficiency of subsequent probabilistic reasoning.

[0585] For example, the embodiment of the present application has a PCB board that needs to be cut at two locations. The embodiment of the present application converts this problem into a Boolean expression, and then generates a d-DNNF circuit through a d-DNNF compiler. Next, the embodiment of the present application will gradually detect and delete Tseitin variables and artifacts.

[0586] Initial Boolean expression:

[0587] (A ∧ B) ∨ (A ∧ C);

[0588] Here, A means "cut at position 1", B means "cut at position 2", and C means "cut at position 3".

[0589] S 5.3.1: Identify Tseitin variants;

[0590] When converting the above expression to d-DNNF form, the compiler introduces Tseitin variables to simplify complex Boolean formulas. Suppose the compiler introduces the following Tseitin variables:

[0591] T1 ⇔ (A ∧ B);

[0592] T2 ⇔ (¬A ∧ C);

[0593] Here, “¬” represents logical negation, and its function is to perform the inversion operation on the proposition or variable behind it. Then ¬A represents the logical negation operation on A.

[0594] Now, the expression of the embodiment of the present application becomes:

[0595] (T1 ∨ T2) ∧ (T1 ⇔ (A ∧ B)) ∧ (T2 ⇔ (¬A ∧ C));

[0596] In this example, T1 and T2 are the Tseitin variables.

[0597] S 5.3.2: Traverse the d-DNNF circuit, identify subcircuits containing only Tseitin variables, and locate Tseitin artifacts;

[0598] Assume that the structure of the d-DNNF circuit is as follows Figure 2 :

[0599] In this structure, the embodiment of the present application can identify the following Tseitin artifacts:

[0600] 1. T1 ⇔ (A ∧ B) this subcircuit;

[0601] 2. The existence of T2, since it is directly connected to the ∨ gate on the top layer;

[0602] S 5.3.3: Starting from the leaf nodes, remove Tseitin variables and Tseitin artifacts layer by layer;

[0603] The present application embodiment deletes Tseitin variables and artifacts according to the following steps:

[0604] 1. Delete the equivalence relation T1 ⇔ (A ∧ B) and directly replace T1 with (A ∧ B).

[0605] 2. Delete T2 and connect (¬A ∧ C) directly to the top-level ∨ gate.

[0606] The circuit structure of d-DNNF after deletion is as follows Figure 3 :

[0607] This simplified structure is equivalent to the original expression (A ∧ B) ∨ (¬A ∧ C) of the embodiment of the present application, but all Tseitin variables and artifacts are removed.

[0608] In the context of PCB breakout routing optimization, this means:

[0609] The embodiment of the present application deletes the additional variables (T1 and T2) introduced in the intermediate steps.

[0610] The simplified structure directly expresses the relationship between the cutting decisions: either cut at positions 1 and 2, or do not cut at position 1 but cut at position 3.

[0611] This simplification makes subsequent probabilistic reasoning more efficient because the embodiments of the present application do not need to consider those artificially introduced intermediate variables.

[0612] Through this process, the embodiment of the present application successfully simplifies the d-DNNF circuit, removes the redundant structure introduced during the compilation process, makes the circuit more compact and efficient, and provides a clearer logical basis for subsequent PCB board path optimization.

[0613] S 5.4: Performing probabilistic reasoning based on the simplified d-DNNF circuit to optimize the first PCB board splitting path to generate the second PCB board splitting path.

[0614] S 5.4.1: Assigning prior probabilities to line segments of the first PCB panel separation path.

[0615] Based on the reliability of the first PCB depaneling path, an initial probability is assigned to each depaneling point or line segment.

[0616] These probabilities can reflect the confidence of the embodiment of the present application in certain parts of the initial path.

[0617] S 5.4.2: Perform probabilistic reasoning using bottom-up probability computation.

[0618] Starting from the leaf nodes of the d-DNNF circuit, the probability of each node is calculated layer by layer.

[0619] By utilizing the structural characteristics of d-DNNF, the probability of complex queries can be calculated efficiently.

[0620] S 5.4.3: Based on the probabilistic reasoning results, select the optimal board splitting path combination.

[0621] According to the results of probability reasoning, the board splitting path combination with the highest overall probability is selected.

[0622] It is necessary to consider multiple local optimal solutions and select the global optimal solution from them.

[0623] Exemplarily, let the embodiment of the present application continue to use the previous PCB panel division example, assuming that the embodiment of the present application needs to select two of three possible positions (A, B, C) for cutting.

[0624] S 5.4.1: Assigning prior probabilities to line segments of the first PCB panel separation path.

[0625] In this step, the embodiment of the present application assigns a priori probability to each cutting position based on the initial PCB panel separation path suggestion and expert knowledge.

[0626] For example:

[0627] P(A) = 0.7 (probability of cutting at position A).

[0628] P(B) = 0.6 (probability of cutting at position B).

[0629] P(C) = 0.5 (probability of cutting at position C).

[0630] These probabilities reflect the initial belief of the embodiments of the present application regarding the feasibility of each cutting position.

[0631] S 5.4.2: Perform probabilistic reasoning using bottom-up probability computation.

[0632] Now, the embodiment of the present application uses the simplified d-DNNF circuit structure to perform probability calculation. Reviewing, the logical expression of the embodiment of the present application is: (A ∧ B) ∨ (¬A ∧ C).

[0633] Calculation steps:

[0634] 1. Calculate leaf node probability:

[0635] P(¬A) = 1 P(A) = 1 0.7 = 0.3;

[0636] 2. Calculate the probability of AND gate:

[0637] P(A ∧ B) = P(A) * P(B) = 0.7 * 0.6 = 0.42;

[0638] P(¬A ∧ C) = P(¬A) * P(C) = 0.3 * 0.5 = 0.15;

[0639] 3. Calculate the probability of the OR gate (use exclusive OR because both conditions cannot be true at the same time):

[0640] P((A ∧ B) ∨ (¬A ∧ C)) = P(A ∧ B) + P(¬A ∧ C) = 0.42 + 0.15 =0.57;

[0641] This result indicates that, based on the model and prior probability of the embodiment of the present application, there is a 57% probability that the embodiment of the present application will select the cutting scheme of (A and B) or (not A but C).

[0642] S 5.4.3: Based on the probabilistic reasoning results, select the optimal board splitting path combination.

[0643] According to the above calculation results, the following conclusions can be drawn from the embodiments of the present application:

[0644] 1. The most likely cut is to cut at positions A and B, with a probability of 0.42 (42%).

[0645] 2. The second best option is to cut at position C and not cut at A, with a probability of 0.15 (15%).

[0646] 3. Other possible combinations (such as cutting only A or cutting only B) have lower probabilities.

[0647] Based on these results, the following decisions can be made in the embodiments of the present application:

[0648] 1. Main recommendation: Cut at positions A and B. This is the optimal combination of panel splitting paths.

[0649] 2. Alternative plan: If cutting at A is not feasible, consider cutting at C.

[0650] This example shows how to use d-DNNF circuits for probabilistic reasoning to provide data support for PCB board splitting path optimization. The advantage of this method is that it can handle complex logical relationships while considering the uncertainty of different cutting positions. In this way, the embodiment of the present application can obtain an optimization solution that takes into account both physical constraints (expressed by logical relationships) and uncertainties (expressed by probabilities).

[0651] In the above example, Figure 4 and Figure 5 The following are the layout diagrams of the first PCB board splitting path (initial suggestion) and the second PCB board splitting path (after optimization).

[0652] in, Figure 4 Middle. First PCB board distribution path (initial suggestion):

[0653] It shows three possible cut lines: A, B, and C. All cut lines are dashed to indicate that they are preliminary suggestions and have not yet been finalized.

[0654] A is the vertical cutting line, located in the center of the PCB.

[0655] B is the horizontal cutting line, located in the center of the PCB.

[0656] C is another vertical cut line, located on the right side of the PCB.

[0657] Figure 5 The second PCB board path (after optimization):

[0658] It shows the optimized cutting plan based on the results of probabilistic reasoning.

[0659] The A and B cut lines become solid lines, indicating that they are the best choices (with a probability of 42%).

[0660] The C cut line remains dashed, indicating that it is an alternative (used when A is not feasible, with a probability of 15%).

[0661] The lines of A and B are thickened to emphasize that they are the main suggested cutting paths.

[0662] This visualization directly shows the results of the optimization process:

[0663] Several cutting options were considered in the initial stages.

[0664] After optimization, the main cutting paths (A and B) were identified, while the alternative (C) was retained.

[0665] The presentation of the cutting lines (solid vs dashed, line thickness) intuitively reflects the priority of each option.

[0666] This example is a great example of how to translate complex probabilistic reasoning results into clear visual guidance to aid decision making during PCB manufacturing. In this way, engineers can quickly understand the optimization algorithm's recommendations and make adjustments if necessary.

[0667] Through the above steps, the embodiment of the present application obtains a second PCB board splitting path optimized by the d-DNNF circuit. Compared with the first path, this path should have higher feasibility and efficiency after considering various constraints and optimization goals.

[0668] The method of this application realizes intelligent optimization of PCB depaneling paths by combining machine learning and logical reasoning technology. This method can not only handle complex PCB layouts, but also continuously improve depaneling strategies based on historical data and real-time feedback, providing an efficient and accurate depaneling solution for the PCB manufacturing industry. Embodiment 2

[0669] like Figure 6 As shown, the embodiment of the present application also provides a PCB board path automatic optimization system based on machine learning, including:

[0670] The collecting module 61 is used to collect PCB sub-board data;

[0671] A feature extraction module 62 is used to extract features from the PCB panel data using a feature engineering method;

[0672] A construction module 63 is used to construct and train a machine learning model, wherein the machine learning model is a hyperbolic space classification-aware continuous semantic segmentation model;

[0673] A generating module 64, configured to input the feature set of the PCB panel splitting data into the machine learning model to generate a first PCB panel splitting path;

[0674] The optimization module 65 is used to generate a d-DNNF circuit using a d-DNNF compiler, and optimize the first PCB board splitting path using the d-DNNF circuit to generate a second PCB board splitting path. Embodiment 3

[0675] The present application also provides a computer device, such as Figure 7 As shown, the computer device includes:

[0676] at least one processor; and,

[0677] a memory communicatively connected to the at least one processor; wherein,

[0678] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the above-mentioned automatic optimization method of PCB board sub-board paths based on machine learning.

[0679] An embodiment of the present application also provides a computer-readable storage medium, which stores computer instructions, and the computer instructions are used to enable a computer to execute the above-mentioned automatic optimization method of PCB board sub-path based on machine learning.

[0680] An embodiment of the present application also provides a computer program product, including computer instructions, characterized in that when the computer instructions are executed by a processor, the steps of the above-mentioned method for automatic optimization of PCB board sub-board paths based on machine learning are implemented.

[0681] Each module in the above-mentioned PCB board path automatic optimization system based on machine learning can be implemented in whole or in part through software, hardware and their combination. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the corresponding operations of each of the above modules.

[0682] In one embodiment, a computer device is also provided, which is the PCB board path automatic optimization system based on machine learning mentioned in the above method embodiment. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface.

[0683] Among them, the processor of the computer device is used to provide computing and control capabilities, and can be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, etc., but is not limited thereto. The processor may include one or more processors, for example, one or more central processing units (CPUs). When the processor is a CPU, the CPU may be a single-core CPU or a multi-core CPU. The processor may also include one or more dedicated processors, and the dedicated processor may include a GPU, an FPGA, etc., for accelerated processing. The processor is used to call the program code and data in the memory and execute the steps in the above method embodiment. For details, please refer to the description in the method embodiment, which will not be repeated here.

[0684] The memory of the computer device includes, but is not limited to, non-volatile storage media and internal memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM may be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium.

[0685] The input / output interface of the computer device is used to exchange information between the processor and external devices.

[0686] The communication interface of the computer device is used to communicate with an external terminal via a network connection.

[0687] When the computer program is executed by a processor, the above method is implemented.

[0688] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the division of each unit / module is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. The mutual coupling, direct coupling, or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of systems or units, which can be electrical, mechanical or other forms.

[0689] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0690] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable system. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a read-only memory (ROM), or a random access memory (RAM), or a magnetic medium, such as a floppy disk, a hard disk, a tape, a disk, or an optical medium, such as a digital versatile disc (DVD), or a semiconductor medium, such as a solid state disk (SSD), etc.

[0691] The system of the embodiments of the present disclosure can execute the method provided by the embodiments of the present disclosure, and the implementation principles are similar. The actions performed by each module in the system of each embodiment of the present disclosure correspond to the steps in the method of each embodiment of the present disclosure. For the detailed functional description of each module of the system, please refer to the description in the corresponding method shown in the previous text, which will not be repeated here.

[0692] The above is only an optional implementation method for some implementation scenarios of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present disclosure, other similar implementation methods based on the technical ideas of the present disclosure are also within the protection scope of the embodiments of the present disclosure.

[0693] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for automatic optimization of PCB board splitting paths based on machine learning, characterized in that: include: Collect PCB sub-board data; Using feature engineering methods to extract features from the PCB panel data; Constructing and training a machine learning model, wherein the machine learning model is a hyperbolic space classification-aware continuous semantic segmentation model; Inputting the feature set of the PCB panel splitting data into the machine learning model to generate a first PCB panel splitting path; Generate a d-DNNF circuit using a d-DNNF compiler, and optimize the first PCB board splitting path using the d-DNNF circuit to generate a second PCB board splitting path; Among them, a machine learning model is constructed and trained, and the machine learning model is a hyperbolic space classification-aware continuous semantic segmentation model, including: A hyperbolic space metric model is defined, wherein the hyperbolic space metric is a Poincare sphere model; Construct a hyperbolic spatial convolutional neural network architecture and back-propagation algorithm; Define a state space and an action space, wherein the state space is the PCB board state, and the action space is the PCB board separation operation; Designing a reward function based on building PCB depaneling quality evaluation indicators, wherein the indicators include depaneling accuracy, depaneling efficiency, and material utilization rate; Use historical PCB panel data for supervised learning pre-training, and use K-fold cross validation to evaluate the performance of the model; The method of generating a d-DNNF circuit by using a d-DNNF compiler and optimizing the first PCB board splitting path by using the d-DNNF circuit to generate a second PCB board splitting path includes: Convert the first PCB board splitting path into a Boolean expression; Inputting the Boolean expression into the d-DNNF compiler to generate a d-DNNF circuit; In the d-DNNF circuit, detecting and removing Tseitin variables and Tseitin artifacts to simplify the d-DNNF circuit; Performing probabilistic reasoning based on the simplified d-DNNF circuit to optimize the first PCB board splitting path to generate the second PCB board splitting path; Wherein, in the d-DNNF circuit, detecting and deleting Tseitin variables and Tseitin artifacts includes: Identifying Tseitin variables, wherein the Tseitin variables are auxiliary variables introduced by the markers during the conversion process of the d-DNNF compiler; traversing the d-DNNF circuit, identifying a subcircuit containing only Tseitin variables, and locating Tseitin artifacts in the subcircuit; Starting from the leaf nodes, Tseitin variables and Tseitin artifacts are deleted layer by layer. The Tseitin artifacts are circuit structures generated by the introduction of Tseitin variables.

2. The method according to claim 1, characterized in that The feature engineering method is used to extract features from the PCB panel data, including: The PCB panel data is subjected to feature classification and decomposed into an image feature subset, a numerical feature subset and a text feature subset; Calculate the marginal contribution of each feature in different feature subsets, and obtain the Shapley value of each feature based on the marginal contribution, wherein the Shapley value is used to characterize the importance of the feature; Based on the Shapley value of each feature, rank the importance of each feature; Through the alignment algorithm, the features of different modalities are mapped to a unified feature space.

3. The method according to claim 2, characterized in that Calculate the marginal contribution of each feature in different feature subsets, and based on the marginal contribution, obtain the Shapley value of each feature, including: Use convolutional neural networks to extract a subset of image features of PCB layouts; Obtain the numerical feature subset and text feature subset of PCB production parameters; For each feature, consider its marginal contribution in different feature subsets; The Shapley value of each feature is approximately calculated using permutation sampling.

4. The method according to claim 2, characterized in that: After mapping the features of different modalities to a unified feature space, the method further includes: In the feature space, principal component analysis (PCA) is used to reduce the dimensionality of high-dimensional features; LASSO regularization is applied, and the Shapley value of each feature is combined to screen out a feature set whose correlation is higher than a first threshold and whose importance is higher than a second threshold. The feature set is the feature set to be input into the machine learning model.

5. The method according to claim 1, characterized in that Inputting the feature set of the PCB panel splitting data into the machine learning model to generate a first PCB panel splitting path, including: Inputting the feature set of the PCB panel data into the hyperbolic space classification-aware continuous semantic segmentation model; Perform forward propagation to generate the first PCB board splitting path suggestion; Converting the first PCB depaneling path suggestion into actual depaneling path coordinates; A smoothing algorithm is applied to smooth the panel separation path to form the first PCB panel separation path.

6. The method according to claim 1, characterized in that Probabilistic reasoning is performed based on the simplified d-DNNF circuit to optimize the first PCB board separation path, including: Assigning prior probabilities to line segments of the first PCB board separation path; Perform probabilistic reasoning using bottom-up probability computation; Based on the probabilistic reasoning results, the optimal board partitioning path combination is selected.

7. A PCB board splitting path automatic optimization method system based on machine learning, characterized in that: include: Collection module, used to collect PCB sub-board data; A feature extraction module is used to extract features from the PCB panel data using a feature engineering method; A construction module is used to construct and train a machine learning model, wherein the machine learning model is a hyperbolic space classification-aware continuous semantic segmentation model; A generating module, used for inputting the feature set of the PCB panel data into the machine learning model to generate a first PCB panel path; An optimization module, used to generate a d-DNNF circuit using a d-DNNF compiler, and optimize the first PCB board splitting path using the d-DNNF circuit to generate a second PCB board splitting path; The construction module is used to construct and train a machine learning model, and the machine learning model is a hyperbolic space classification-aware continuous semantic segmentation model, including: A hyperbolic space metric model is defined, wherein the hyperbolic space metric is a Poincare sphere model; Construct a hyperbolic spatial convolutional neural network architecture and back-propagation algorithm; Define a state space and an action space, wherein the state space is the PCB board state, and the action space is the PCB board separation operation; Designing a reward function based on building PCB depaneling quality evaluation indicators, wherein the indicators include depaneling accuracy, depaneling efficiency, and material utilization rate; Use historical PCB panel data for supervised learning pre-training, and use K-fold cross validation to evaluate the performance of the model; The optimization module is used to generate a d-DNNF circuit using a d-DNNF compiler, and optimize the first PCB board splitting path using the d-DNNF circuit to generate a second PCB board splitting path, including: Convert the first PCB board splitting path into a Boolean expression; Inputting the Boolean expression into the d-DNNF compiler to generate a d-DNNF circuit; In the d-DNNF circuit, detecting and removing Tseitin variables and Tseitin artifacts to simplify the d-DNNF circuit; Performing probabilistic reasoning based on the simplified d-DNNF circuit to optimize the first PCB board splitting path to generate the second PCB board splitting path; Wherein, in the d-DNNF circuit, detecting and deleting Tseitin variables and Tseitin artifacts includes: Identifying Tseitin variables, wherein the Tseitin variables are auxiliary variables introduced by the markers during the conversion process of the d-DNNF compiler; traversing the d-DNNF circuit, identifying a subcircuit containing only Tseitin variables, and locating Tseitin artifacts in the subcircuit; Starting from the leaf nodes, Tseitin variables and Tseitin artifacts are deleted layer by layer. The Tseitin artifacts are circuit structures generated by the introduction of Tseitin variables.

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