Printed circuit board defect detection method and device based on cross-scale multi-aggregation

Abstract

The present invention relates to a printed circuit board defect detection method and device based on cross-scale multiple aggregation, and relates to the field of target detection. The method comprises: obtaining a printed circuit board defect image and performing preprocessing; using an improved YOLOv8 network to perform feature extraction and fusion, wherein the feature extraction network adopts CDA-net, and the network comprises an embedding layer module, a four-layer CDA module and an SPPF module, and can effectively extract multi-scale features; the feature fusion network adopts RGS-FPN to perform efficient multi-scale feature fusion; an anchor-free YOLOv8 detection head is used for target detection, and an Adam optimizer is used to train the model with a learning rate of 0.001; the preprocessed image is input into the trained model to obtain the defect detection result of the printed circuit board. The present invention improves the accuracy and efficiency of printed circuit board defect detection through deep learning technology, and is suitable for quality control in the manufacturing process of printed circuit boards.

Description

Technical Field

[0001] The present invention relates to the field of target detection, and in particular to a printed circuit board defect detection method based on cross-scale multiple aggregation. Background Art

[0002] Printed circuit boards (PCBs) are core components of electronic products, and their quality directly affects device performance and reliability. Various defects may occur during the production process, such as poor soldering, open circuits, short circuits, and component misalignment, which can lead to product failures and reduce user experience. Defect detection can not only improve product qualification rates and reduce rework and scrap rates, but also save production costs, improve production efficiency, meet strict industry standards, prevent potential safety risks, and promote technological progress.

[0003] Manual inspection relies on the operator's experience and judgment, which is slow and difficult to meet the needs of modern large-scale production. Human factors have a great impact, and long-term work can easily lead to fatigue, resulting in high rates of missed inspections and false inspections. A large number of well-trained personnel are required for inspection, which increases labor costs. The judgment standards of different operators may be inconsistent, resulting in volatility in the inspection results. Faced with complex PCB patterns and tiny defects, manual visual inspection capabilities are limited and it is difficult to ensure high accuracy.

[0004] By training a large amount of labeled data, the deep learning model can automatically extract features and classify them, significantly improving the accuracy of detection. The automated detection system can quickly process a large number of images, significantly improve the detection speed, and adapt to the needs of large-scale production. The detection results of the deep learning model are consistent and are not affected by human factors, ensuring the consistency and reliability of the detection. Although hardware and model training costs are required in the early stage, in the long run, the automated detection system reduces labor costs and improves production efficiency. The deep learning model can handle complex patterns and tiny defects, has strong adaptability, and can be applied to various PCB detection scenarios. The model can also continuously optimize the detection performance and adapt to new defect types through continuous learning and updating. Summary of the invention

[0005] In order to solve the above problems, the present invention proposes a printed circuit board defect detection method and device based on cross-scale multiple aggregation.

[0006] The specific plan is as follows:

[0007] On the one hand, a printed circuit board defect detection method based on cross-scale multi-aggregation includes the following steps:

[0008] S101, acquiring a printed circuit board defect image, and preprocessing the printed circuit board defect image to obtain a preprocessed printed circuit board defect image;

[0009] S102, using the YOLOv8 network to build a printed circuit board defect detection model; using the cross-stage partial dual aggregation network CDA-net as the feature extraction network of the YOLOv8 network; extracting feature information from the printed circuit board defect image through the CDA module in CDA-net, and outputting a feature map processed by the CDA module;

[0010] S103, using the residual gated separation feature pyramid network RGS-FPN as the feature fusion network of the YOLOv8 network, and performing multi-scale feature fusion on the feature map processed by the CDA module through the RGS module in the RGS-FPN to obtain a feature map processed by the RGS module;

[0011] S104, inputting the feature map processed by the RGS module into the anchor-free YOLOv8 detection head, and using a single-stage target detection algorithm to train the printed circuit board defect detection model to obtain a trained printed circuit board defect detection model;

[0012] S105, inputting the preprocessed printed circuit board image to be inspected into a trained printing defect detection model to obtain a defect detection result.

[0013] Furthermore, in S101 and S105, the preprocessing specifically includes:

[0014] The image is subjected to at least one of mosaic enhancement processing, mixed enhancement processing, random disturbance processing and color disturbance processing.

[0015] Further, in S102, the CDA-net includes an embedding layer module, a first layer CDA module, a second layer CDA module, a third layer CDA module, a fourth layer CDA module and an SPPF module connected in sequence;

[0016] The embedding layer module converts the size of the input PCB defect image into H×W×3 Adjust to

[0017] The first-level CDA module extracts The features of the image are downsampled to obtain the feature map

[0018] The second layer CDA module extracts The features of the image are downsampled to obtain the feature map

[0019] The third layer CDA module extracts The features of the image are downsampled to obtain the feature map

[0020] The fourth layer CDA module extracts The features of the image are downsampled to obtain the feature map

[0021] Wherein, H is the height of the input printed circuit board defect image, W is the width of the input printed circuit board defect image, and C is the number of channels of the input printed circuit board defect image;

[0022] The SPPF module uses spatial pyramid pooling to extract features on the 16C channel output by the fourth-layer CDA module to capture detailed information of the target object at different scales.

[0023] Further, the CDA module includes a feature extraction part and a downsampling part;

[0024] The feature extraction part, the calculation process is as follows:

[0025] X 1 = CBS(x);

[0026] X 2 =Chunk(x 1 );

[0027] X 3 =CBS(X 2 );

[0028] x 4 =add(GConv(CBS(x 2 )), PoConv(CBS(x 2 ))).

[0029] x 5 =concat(X 3 , x 4 ).

[0030] y=CB S(x 5 ).

[0031] Among them, concat() represents the dimension concatenation operation; add() represents the addition operation; PoConv() represents the Pointwise convolution operation; GConv() represents the group convolution operation; Chunk() represents the division of the feature map in the channel dimension; CBS() represents the convolution operation, batch normalization operation and silu activation function operation; x represents the input feature map; x 1 、x 2 、x 3 、x 4 and x 5represents the intermediate feature map; y represents the feature map of the final output;

[0032] The downsampling part is calculated as follows:

[0033] y 1 =CBS(y);

[0034] y 2 =concat(CBS(y 1 ), DWCBS(y 1 ));

[0035] y 3 =BN(PReLU(y 2 ));

[0036] y 4 =FC(FC(Avg pooling(y 3 )));

[0037] z=y 3 ×y 4 ;

[0038] Among them, BN() represents batch normalization operation, PReLU() represents activation function operation, DWCBS() represents depth separable convolution operation DWconv(), batch normalization operation and silu activation function operation, FC() represents full connection operation, Avg pooling() represents average pooling operation, y represents input feature map, y 1 ,y 2 ,y 3 ,y 4 , represents the intermediate feature map, and z represents the feature map of the final output.

[0039] Furthermore, in S103, the calculation process of multi-scale feature fusion by the RGS module in RGS-FPN is as follows:

[0040] D 1 =add(T 5 , T 6 );

[0041] D 2 =add(T 3 , T 2 );

[0042] D 3 =RGS(concat(T 2 , T 1 ));

[0043] D 4=RGS(concat(T 4 , P 4 ));

[0044] T 6 =RGS(concat(add(T 3 , T 2 ), P 1 ));

[0045] T 5 =CDA(add(T 3 , T 2 ), T 4 ,concat(add(T 3 , T 2 ), P 1 ));

[0046] T 4 =RGS(concat(T 2 , T 1 ));

[0047] T 3 =CDA(P 4 , P 2 , P 3 );

[0048] T 2 =RGS(concat(T 1 , P 2 , P 1 ));

[0049] T 1 =RGS(concat(P 4 ,P 2 ,P 3 ));

[0050] Among them, P 1 , P 2 , P 3 , P 4 is the input feature map, D 1 , D 2 , D 3 , D 4 is the output feature map, T 1 , T 2 , T 3 , T 4 , T 5 , T 6 is the intermediate feature map, RGS() indicates multi-scale feature fusion through the RGS module, and CDA() indicates extracting feature information of the feature map through the CDA module.

[0051] Furthermore, the RGS module divides the input feature map into multiple regions, each of which is set as a token. Each token generates a unique gating signal based on the features of its nearest neighbors, and achieves more efficient signal flow through residual separation. The formula is as follows:

[0052] W 1 =CBS(W);

[0053] W 2 =Chunk(W 1 );

[0054] W 3 =PConv(W 2 );

[0055] W 4 =add(W 3 ,linear(silu(DWconv(linear(W 3 ))))×linear(W 3 ));

[0056] g = concat(add(W 1 ,W 4 ),W 2 );

[0057] Among them, linear() means linear operation (linear activation), PConv() means partial convolution operation, Chunk() means dividing the feature map in the channel dimension, W means input feature map, W 1 , W 2 , W 3 , W 4 represents the intermediate feature map, and g represents the feature map of the final output.

[0058] Furthermore, in S104, during the training of the printed circuit board defect detection model, the Adam optimizer is used and the learning rate is set to 0.001.

[0059] On the other hand, printed circuit board defect detection based on cross-scale multi-aggregation includes:

[0060] An image preprocessing module is used to obtain a printed circuit board defect image, preprocess the printed circuit board defect image, and obtain a preprocessed printed circuit board defect image;

[0061] A feature extraction module is used to build a printed circuit board defect detection model using the YOLOv8 network; the cross-stage partial dual aggregation network CDA-net is used as the feature extraction network of the YOLOv8 network; the feature information in the printed circuit board defect image is extracted through the CDA module in CDA-net, and the feature map processed by the CDA module is output;

[0062] The feature fusion module is used to use the residual gated separation feature pyramid network RGS-FPN as the feature fusion network of the YOLOv8 network, and perform multi-scale feature fusion on the feature map processed by the CDA module through the RGS module in RGS-FPN to obtain the feature map processed by the RGS module;

[0063] The model training module is used to input the feature map processed by the RGS module into the anchor-free YOLOv8 detection head, and use the single-stage target detection algorithm to train the printed circuit board defect detection model to obtain a trained printed circuit board defect detection model;

[0064] The defect detection module is used to input the preprocessed printed circuit board image to be detected into the trained printing defect detection model to obtain the defect detection result.

[0065] The present invention adopts the above technical solution and has the following beneficial effects:

[0066] (1) Improved detection accuracy: By introducing the feature extraction network CDA-net based on the YOLOv8 network and the feature fusion network RGS-FPN for feature extraction and fusion, the accuracy of printed circuit board defect image detection is significantly improved;

[0067] (2) Enhanced model robustness: By using the cross-stage partial dual aggregation network (CDA-net) and the residual gated segregated feature pyramid network (RGS-FPN), the model can better handle features of different scales and improve the detection ability of complex patterns and tiny defects, especially for defects such as open circuits, short circuits, mouse bites, and stray defects;

[0068] (3) Improved detection speed: By using a single-stage target detection network for training, the model can process a large number of images more quickly and meet the needs of large-scale production. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Figure 1 A printed circuit board defect detection method based on cross-scale multi-aggregation according to an example of the present invention;

[0070] Figure 2 The CDA-net structure diagram of the present invention is an example;

[0071] Figure 3 It is a CDA structure diagram of an example of the present invention;

[0072] Figure 4 It is a structural diagram of RGS-FPN of an example of the present invention;

[0073] Figure 5 The RGS structure diagram of the present invention example;

[0074] Figure 6 It is a diagram showing the detection effect of six defect types of printed circuit boards according to an example of the present invention;

[0075] Figure 7 This is a structural block diagram of a printed circuit board defect detection device based on deep learning according to an embodiment of the present invention. DETAILED DESCRIPTION

[0076] The present invention is further described in detail below in conjunction with embodiments and drawings, but the embodiments of the present invention are not limited thereto.

[0077] like Figure 1 As shown, the present invention provides a printed circuit board defect detection method based on cross-scale multiple aggregation, which includes the following steps.

[0078] S101, acquiring a printed circuit board defect image, and preprocessing the printed circuit board defect image to obtain a preprocessed printed circuit board defect image.

[0079] Specifically, the preprocessing includes mosaic enhancement (Mosaic), mixed enhancement (Mixup), random perspective and color perturbation (HSV augment) on the defective image.

[0080] S102, using the YOLOv8 network to build a printed circuit board defect detection model; using the cross-stage partial dual aggregation network CDA-net as the feature extraction network of the YOLOv8 network; extracting feature information from the printed circuit board defect image through the CDA module in CDA-net, and outputting a feature map processed by the CDA module.

[0081] Specifically, Figure 2 As shown, the CDA-net includes an embedding layer module, a first layer CDA module, a second layer CDA module, a third layer CDA module, a fourth layer CDA module and an SPPF module which are connected in sequence;

[0082] The embedding layer module converts the size of the input PCB defect image into H×W×3 Adjust to

[0083] The first-level CDA module extracts The features of the image are downsampled to obtain the feature map

[0084] The second layer CDA module extracts The features of the image are downsampled to obtain the feature map

[0085] The third layer CDA module extracts The features of the image are downsampled to obtain the feature map

[0086] The fourth layer CDA module extracts The features of the image are downsampled to obtain the feature map

[0087] Wherein, H is the height of the input printed circuit board defect image, W is the width of the input printed circuit board defect image, and C is the number of channels of the input printed circuit board defect image;

[0088] The SPPF module uses spatial pyramid pooling to extract features on the 16C channel output by the fourth-layer CDA module to capture detailed information of the target object at different scales. Specifically, Figure 3 As shown, the CDA module includes a feature extraction part and a downsampling part;

[0089] The feature extraction part, the calculation process is as follows:

[0090] X 1 =CBS(x).

[0091] X 2 =Chunk(x 1 )

[0092] X 3 =CBS(x 2 ).

[0093] X 4 =add(GConv(CBS(x 2 )), PoConv(CBS(x 2 ))).

[0094] x 5 =concat(x 3 , X 4 ).

[0095] y=CBS(X 5 );

[0096] Among them, concat() represents the dimension concatenation operation; add() represents the addition operation; PoConv() represents the Pointwise convolution operation; GConv() represents the group convolution operation; Chunk() represents the division of the feature map in the channel dimension; CBS() represents the convolution operation, batch normalization operation and silu activation function operation; x represents the input feature map; x 1 、x 2 、x 3 、x 4 and x 5 represents the intermediate feature map; y represents the feature map of the final output;

[0097] Feature map x 1 The input feature map x is obtained by the CBS module, and then x 1 The channel number is divided into two halves, and one part of it passes through the CBS module to obtain x 3 The other part passes through the CBS module and is extracted by group convolution and Pointwise convolution in parallel, and then added to get x 4 , x 3 and x 4 Combine in the channel dimension to get x 5 , and finally x 5 The feature map y is obtained through the CBS module;

[0098] The downsampling part is calculated as follows:

[0099] y 1 =CBS(y);

[0100] y 2 =concat(CBS(y 1 ), DWCBS(y 1 ));

[0101] y 3 =BN(PReLU(y 2 ));

[0102] y 4 =FC(FC(Avg pooling(y 3 )));

[0103] z=y 3 ×y 4 ;

[0104] Among them, BN() represents batch normalization operation, PReLU() represents activation function operation, DWCBS() represents depth separable convolution operation DWconv(), batch normalization operation and silu activation function operation, FC() represents full connection operation, Avg pooling() represents average pooling operation, y represents input feature map, y 1 ,y 2 ,y 3 ,y 4 , represents the intermediate feature map, and z represents the feature map of the final output.

[0105] Feature map y 1 The input feature map y is obtained by the CBS module, y 1 The feature map y is obtained by passing through the 3×3CBS module and the 3×3DWCBS module in parallel and combining them in the channel dimension. 2 , feature map y 2 After batch normalization and PReLU activation function, we get y 3 , feature map y 3 After average pooling and two fully connected layers, we get y 4 , and finally 4 and 3 Multiply them to get the final output feature map z.

[0106] S103, using the residual gated separation feature pyramid network RGS-FPN as the feature fusion network of the YOLOv8 network, and performing multi-scale feature fusion on the feature map processed by the CDA module through the RGS module in the RGS-FPN to obtain the feature map processed by the RGS module.

[0107] like Figure 4 As shown, the calculation process of multi-scale feature fusion through the RGS module in RGS-FPN is as follows:

[0108] D 1 =add(T 5 , T 6 );

[0109] D 2 =add(T 3 , T 2 );

[0110] D 3 =RGS(concat(T 2 , T 1 ));

[0111] D 4=RGS(concat(T 4 , P 4 ));

[0112] T 6 =RGS(concat(add(T 3 , T 2 ), P 1 ));

[0113] T 5 =CDA(add(T 3 , T 2 ), T 4 ,concat(add(T 3 , T 2 ), P 1 ));

[0114] T 4 =RGS(concat(T 2 , T 1 ));

[0115] T 3 =CDA(P 4 , P 2 , P 3 );

[0116] T 2 =RGS(concat(T 1 , P 2 , P 1 ));

[0117] T 1 =RGS(concat(P 4 , P 2 , P 3 ));

[0118] Among them, P 1 , P 2 , P 3 , P 4 is the input feature map, D 1 , D 2 , D 3 , D 4 is the output feature map, T 1 , T 2 , T 3 , T 4 , T 5 , T 6 is the intermediate feature map, RGS() indicates multi-scale feature fusion through the RGS module, and CDA() indicates extracting feature information of the feature map through the CDA module.

[0119] The T 1 It is by P 2 , P 3 , P 4 After the dimension splicing operation and then through the RGS module;

[0120] The T 2 By T 1 , P 2 , P 1 After the dimension splicing operation and then through the RGS module;

[0121] The T 3 It is by P 4 , P 2 , P 3 Obtained through the CDA module;

[0122] The T 4 By T 1 , T 2 After the dimension splicing operation and then through the CDA module;

[0123] The T 5 By D 3 , T 2 and T 3 Add, after dimension splicing P 1 With T 2 and T 3 Added and then obtained by the CDA module;

[0124] The T 6 It is P after dimension splicing 1 With T 2 and T 3 Added and then obtained by the CDA module;

[0125] The D 1 By T 5 and T 6 Added together;

[0126] The D 2 By T 3 and T 2 Added together;

[0127] The D 3 By T 1 and T 2 After the dimension splicing operation and then through the RGS module;

[0128] The D 4 It is by P 4 and T 4It is obtained after the dimension splicing operation and then the RGS module.

[0129] Specifically, Figure 5 As shown, the RGS module divides the input feature map into multiple regions, each of which is set as a token. Each token generates a unique gating signal based on the features of its nearest neighbors, and achieves more efficient signal flow through residual separation. The formula is as follows:

[0130] W 1 =CBS(W);

[0131] W 2 =Chunk(W 1 );

[0132] W 3 =PConv(W 2 );

[0133] W 4 =add(W 3 ,linear(silu(DWconv(linear(W 3 ))))×linear(W 3 ));

[0134] g = concat(add(W 1 ,W 4 ),W 2 );

[0135] Among them, linear() means linear operation (linear activation), PConv() means partial convolution operation, Chunk() means dividing the feature map in the channel dimension, W means input feature map, W 1 , W 2 , W 3 , W 4 represents the intermediate feature map, and g represents the feature map of the final output.

[0136] The RGS module first transforms the shallow feature map W 1 Divide on the channel dimension to get W 2 , W 2 After partial convolution, feature extraction is completed efficiently to generate W 3 ; W 3 Processing is done in two parallel paths: In the first path, W 3 First, it passes through the linear layer, then through the depth-wise separable convolutional layer and the silu activation function; in the second path, W 3 Directly pass through the linear layer; multiply the results of the two paths and pass through the linear layer with W 3Add; this process will be repeated N times, and finally the output W is obtained 4 ; Finally, W 4 With W 1 After adding, and with W 2 Perform dimension splicing operation to obtain the final output feature map g.

[0137] S104, inputting the feature map processed by the RGS module into the anchor-free YOLOv8 detection head, using a single-stage target detection algorithm to train the printed circuit board defect detection model, and obtaining a trained printed circuit board defect detection model;

[0138] Specifically, during the training of the printed circuit board defect detection model, the Adam optimizer was used and the learning rate was set to 0.001.

[0139] S105, inputting the preprocessed printed circuit board defect image into a trained printing defect detection model to obtain a defect detection result.

[0140] The following is an ablation experiment on the printed circuit board defect detection model, and the printed circuit board detection effect is analyzed and counted to understand the performance advantages of the printed circuit board defect detection method. The results are shown in Table 1. All data in Table 1 are in percentage (%). CSPdarknet53 is the feature extraction network of YOLOv8, PAN-FPN is the feature fusion network of YOLOv8, CDA-net is a cross-stage partial dual aggregation network, and RGS-FPN is a residual gated separation feature pyramid network. Part of the printed circuit board defect map is input into the printed circuit board defect detection model for ablation experiments, as shown in Figure 6 As shown, including: Missing hole, Mouse bite, Open circuit, Short circuit, Spur, Spurious copper. Each colored box in the reasoning effect diagram indicates that the printed circuit board defect detection model (CSMA-detector) has identified a specific defect type.

[0141] Table 1 Comparison of module ablation experiment results

[0142]

[0143] As shown in Table 1, when CDA-net is added to the YOLOv8 baseline network alone, the mAP50 reaches 94.5% and the precision reaches 96.3%, which is 1.9% higher than before CDA-net is added and the precision is 1.2% higher.

[0144] As shown in Table 1, when CDA-net and RGS-FPN and their RGS modules are added to the YOLOv8 baseline network, the mAP50 reaches 95.6% and the precision reaches 97.1%. Compared with only CDA-net added to the YOLOv8 baseline network, the mAP50 is improved by 1.1% and the precision is improved by 0.8%. The above ablation experiments verify that the performance of the printed circuit board defect detection method proposed in the embodiment of the present application is superior.

[0145] like Figure 7 As shown, this embodiment also discloses a printed circuit board defect detection device based on cross-scale multi-aggregation, including:

[0146] An image preprocessing module 701 is used to obtain a printed circuit board defect image, and preprocess the printed circuit board defect image to obtain a preprocessed printed circuit board defect image;

[0147] The feature extraction module 702 is used to construct a printed circuit board defect detection model using the YOLOv8 network; use the cross-stage partial dual aggregation network CDA-net as the feature extraction network of the YOLOv8 network; extract feature information from the printed circuit board defect image through the CDA module in the CDA-net, and output a feature map processed by the CDA module;

[0148] A feature fusion module 703 is used to use the residual gated separation feature pyramid network RGS-FPN as a feature fusion network of the YOLOv8 network, and perform multi-scale feature fusion on the feature map processed by the CDA module through the RGS module in the RGS-FPN to obtain a feature map processed by the RGS module;

[0149] The model training module 704 is used to input the feature map processed by the RGS module into the anchor-free YOLOv8 detection head, and use the single-stage target detection algorithm to train the printed circuit board defect detection model to obtain a trained printed circuit board defect detection model;

[0150] The defect detection module 705 is used to input the preprocessed printed circuit board image to be detected into the trained printing defect detection model to obtain the defect detection result.

[0151] The specific implementation of printed circuit board defect detection based on cross-scale multiple aggregation is the same as the printed circuit board defect detection method based on cross-scale multiple aggregation, and will not be repeated in this embodiment.

[0152] Although the present invention has been specifically shown and described in conjunction with the preferred embodiments, it should be understood by those skilled in the art that various changes may be made to the present invention in form and details without departing from the spirit and scope of the present invention as defined by the appended claims, all of which are within the scope of protection of the present invention.

Claims

1. A printed circuit board defect detection method based on cross-scale multi-aggregation, characterized in that: The following steps are involved: S101, acquiring a printed circuit board defect image, and preprocessing the printed circuit board defect image to obtain a preprocessed printed circuit board defect image; S102, using the YOLOv8 network to build a printed circuit board defect detection model; using the cross-stage partial dual aggregation network CDA-net as the feature extraction network of the YOLOv8 network; extracting feature information from the printed circuit board defect image through the CDA module in CDA-net, and outputting a feature map processed by the CDA module; S103, using the residual gated separation feature pyramid network RGS-FPN as the feature fusion network of the YOLOv8 network, and performing multi-scale feature fusion on the feature map processed by the CDA module through the RGS module in the RGS-FPN to obtain a feature map processed by the RGS module; S104, inputting the feature map processed by the RGS module into the anchor-free YOLOv8 detection head, and using a single-stage target detection algorithm to train the printed circuit board defect detection model to obtain a trained printed circuit board defect detection model; S105, inputting the preprocessed printed circuit board image to be inspected into a trained printing defect detection model to obtain a defect detection result; The calculation process of multi-scale feature fusion through the RGS module in RGS-FPN is as follows: D1 = add(T5, T6); D2 = add(T3, T2); D3 = RGS(concat(T2,T1)); D4=RGS(concat(T 4, P4)); T6=RGS(concat(add(T3,T2),P1)); T5=CDA(add(T3,T2),T4,concat(add(T3,T2),P1)); T4 = RGS(concat(T2,T1)); T3=CDA(P4,P2,P3); T2 = RGS(concat(T1,P2,P1)); T1 = RGS(concat(P4,P2,P3)); Among them, concat() represents the dimension concatenation operation, add() represents the addition operation, P1, P2, P3, P4 are input feature maps, D1, D2, D3, D4 are output feature maps, T1, T2, T3, T4, T5, T6 are intermediate feature maps, RGS() represents multi-scale feature fusion through the RGS module, and CDA() represents the extraction of feature information of the feature map through the CDA module.

2. The printed circuit board defect detection method based on cross-scale multi-aggregation according to claim 1 is characterized in that: In S101 and S105, the preprocessing specifically includes: The image is subjected to at least one of mosaic enhancement processing, mixed enhancement processing, random disturbance processing and color disturbance processing.

3. The printed circuit board defect detection method based on cross-scale multi-aggregation according to claim 1 is characterized in that: In S102, the CDA-net includes an embedded layer module, a first layer CDA module, a second layer CDA module, a third layer CDA module, a fourth layer CDA module and an SPPF module connected in sequence; The embedding layer module converts the size of the input PCB defect image into H×W×3 Adjust to The first-level CDA module extracts The features of the image are downsampled to obtain the feature map The second layer CDA module extracts The features of the image are downsampled to obtain the feature map The third layer CDA module extracts The features of the image are downsampled to obtain the feature map The fourth layer CDA module extracts The features of the image are downsampled to obtain the feature map Wherein, H is the height of the input printed circuit board defect image, W is the width of the input printed circuit board defect image, and C is the number of channels of the input printed circuit board defect image; The SPPF module uses spatial pyramid pooling to extract features on the 16C channel output by the fourth-layer CDA module to capture detailed information of the target object at different scales.

4. The printed circuit board defect detection method based on cross-scale multi-aggregation according to claim 3 is characterized in that: The CDA module includes a feature extraction part and a downsampling part; The feature extraction part, the calculation process is as follows: x1=CBS(x); x2 = Chunk(x1); x3=CBS(x2); x4=add(GConv(CBS(x2)),PoConv(CBS(x2))); x5 = concat(x3,x4); y = CBS(x5); Among them, PoConv() represents Pointwise convolution operation; GConv() represents group convolution operation; Chunk() represents dividing the feature map in the channel dimension; CBS() represents convolution operation, batch normalization operation and silu activation function operation; x represents the input feature map; x1, x2, x3, x4 and x5 represent intermediate feature maps; y represents the final output feature map; The downsampling part is calculated as follows: y1=CBS(y); y2=concat(CBS(y1),DWCBS(y1)); y3=BN(PReLU(y2)); y4=FC(FC(Avg pooling(y3))); z=y3×y4; Among them, BN() represents batch normal batch normalization operation, PReLU() represents activation function operation, DWCBS() represents depth separable convolution operation DWconv(), batch normal batch normalization operation and silu activation function operation, FC() represents full connection operation, Avg pooling() represents average pooling operation, y represents input feature map, y1, y2, y3, y4 represent intermediate feature maps, and z represents the final output feature map.

5. The printed circuit board defect detection method based on cross-scale multi-aggregation according to claim 4 is characterized in that: The RGS module divides the input feature map into multiple regions, each of which is set as a token. Each token generates a unique gating signal based on the features of its nearest neighbors and achieves more efficient signal flow through residual separation. The formula is as follows: W1=CBS(W); W2 = Chunk(W1); W3 = PConv(W2); W4=add(W3,linear(silu(DWconv(linear(W3))))×linear(W3)); g = concat(add(W1,W4),W2); Among them, linear() means performing a linear operation, PConv() means performing a partial convolution operation, Chunk() means dividing the feature map in the channel dimension, W means the input feature map, W1, W2, W3, W4 mean the intermediate feature maps, and g means the final output feature map.

6. The printed circuit board defect detection method based on cross-scale multi-aggregation according to claim 1 is characterized in that: In S104, during the training of the printed circuit board defect detection model, the Adam optimizer is used and the learning rate is set to 0.

001.

7. A printed circuit board defect detection device based on cross-scale multi-aggregation, characterized in that: These include: An image preprocessing module is used to obtain a printed circuit board defect image, preprocess the printed circuit board defect image, and obtain a preprocessed printed circuit board defect image; A feature extraction module is used to build a printed circuit board defect detection model using the YOLOv8 network; the cross-stage partial dual aggregation network CDA-net is used as the feature extraction network of the YOLOv8 network; the feature information in the printed circuit board defect image is extracted through the CDA module in CDA-net, and the feature map processed by the CDA module is output; The feature fusion module is used to use the residual gated separation feature pyramid network RGS-FPN as the feature fusion network of the YOLOv8 network, and perform multi-scale feature fusion on the feature map processed by the CDA module through the RGS module in RGS-FPN to obtain the feature map processed by the RGS module; The model training module is used to input the feature map processed by the RGS module into the anchor-free YOLOv8 detection head, and use the single-stage target detection algorithm to train the printed circuit board defect detection model to obtain a trained printed circuit board defect detection model; A defect detection module is used to input the preprocessed printed circuit board image to be detected into a trained printing defect detection model to obtain a defect detection result; The calculation process of multi-scale feature fusion through the RGS module in RGS-FPN is as follows: D1 = add(T5, T6); D2 = add(T3, T2); D3 = RGS(concat(T2,T1)); D4=RGS(concat(T 4, P4)); T6=RGS(concat(add(T3,T2),P1)); T5=CDA(add(T3,T2),T4,concat(add(T3,T2),P1)); T4 = RGS(concat(T2,T1)); T3=CDA(P4,P2,P3); T2 = RGS(concat(T1,P2,P1)); T1 = RGS(concat(P4,P2,P3)); Among them, concat() represents the dimension concatenation operation, add() represents the addition operation, P1, P2, P3, P4 are input feature maps, D1, D2, D3, D4 are output feature maps, T1, T2, T3, T4, T5, T6 are intermediate feature maps, RGS() represents multi-scale feature fusion through the RGS module, and CDA() represents the extraction of feature information of the feature map through the CDA module.

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