High electron mobility transistor and method for manufacturing the same

Abstract

The embodiments of the present application relate to a high electron mobility transistor and a method for preparing the same, and belong to the field of semiconductor technology; wherein the transistor comprises: a substrate; a heterojunction structure located on the substrate, the heterojunction structure comprising a channel layer and a barrier layer stacked in sequence in a direction away from the substrate, and a two-dimensional electron gas channel is formed in a region of at least part of the channel layer close to the barrier layer; a source structure, a drain structure and a gate structure located on the heterojunction structure; wherein the drain structure comprises a drain connection structure and a drain electrode stacked in sequence in a direction away from the channel layer, and a two-dimensional hole gas channel is formed in a region of at least part of the channel layer close to the drain connection structure; in this way, the current density is effectively improved, and ultimately the device performance is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a high electron mobility transistor and a method for preparing the same. Background Art

[0002] High Electron Mobility Transistor (HEMT) is a field effect transistor based on the high mobility characteristics of the two-dimensional electron gas (2DEG) in the heterojunction. It has high electron mobility under low temperature and low electric field, and can achieve high-speed and low-noise operation.

[0003] However, in conventional HEMT devices, both the source and drain terminals are N-type ohmic contacts, and the entire device conducts electricity using two-dimensional electron gas as the single effective carrier. This single effective carrier conduction method has the problem of low current density. How to achieve current expansion has become a technical problem that this field is committed to solving. Summary of the invention

[0004] In view of this, embodiments of the present application provide a high electron mobility transistor and a method for manufacturing the same in order to solve at least one problem existing in the background technology.

[0005] In a first aspect, an embodiment of the present application provides a high electron mobility transistor, comprising:

[0006] substrate;

[0007] a heterojunction structure located on the substrate, the heterojunction structure comprising a channel layer and a barrier layer stacked in sequence in a direction away from the substrate, a two-dimensional electron gas channel being formed in at least a portion of the channel layer in a region close to the barrier layer;

[0008] A source structure, a drain structure and a gate structure located on the heterojunction structure;

[0009] The drain structure includes a drain connection structure and a drain electrode stacked in sequence in a direction away from the channel layer, and a two-dimensional hole gas channel is formed in at least a portion of the channel layer in a region close to the drain connection structure.

[0010] In combination with the first aspect of the present application, in an optional implementation manner, the material of the drain connection structure includes at least one of the following: AlN, AlN-based alloy, InN, and InN-based alloy.

[0011] In combination with the first aspect of the present application, in an optional implementation, the material of the drain connection structure includes at least one of the following: AlN, InN, InAlN, AlScN, InScN, InAlScN, InAlGaN.

[0012] In combination with the first aspect of the present application, in an optional implementation manner, the material of the drain connection structure is doped with P-type ions.

[0013] In combination with the first aspect of the present application, in an optional embodiment, the drain structure also includes a P-type material layer, and the P-type material layer is stacked between the drain connection structure and the drain electrode; the material of the P-type material layer includes at least one of the following: V2O5, Cu2O, NiO, SnO, MoO3, WO3, and P-type GaN.

[0014] In combination with the first aspect of the present application, in an optional implementation, the thickness of the drain connection structure increases along a direction from the source structure to the drain structure.

[0015] In combination with the first aspect of the present application, in an optional implementation, the barrier layer includes an opening exposing the channel layer, and the drain connection structure is at least partially located in the opening to contact the channel layer; or,

[0016] The channel layer includes a main body portion located between the lower surface of the barrier layer and the substrate and a protrusion portion extending from the main body portion in a direction away from the substrate. The lower surface of the barrier layer is a surface of the barrier layer close to the substrate. The protrusion portion is not covered by the barrier layer, and the drain connection structure is in contact with the protrusion portion.

[0017] In a second aspect, an embodiment of the present application provides a method for preparing a high electron mobility transistor, the method comprising:

[0018] providing a substrate;

[0019] forming a heterojunction structure on the substrate, wherein the heterojunction structure comprises a channel layer and a barrier layer formed in sequence, wherein at least a portion of the channel layer near the barrier layer is used to form a two-dimensional electron gas channel;

[0020] forming a source structure, a drain structure and a gate structure on the heterojunction structure;

[0021] Wherein, forming the drain structure comprises:

[0022] forming a drain connection structure on the heterojunction structure, so that a two-dimensional hole gas channel is formed in at least a portion of the channel layer in a region close to the drain connection structure;

[0023] A drain electrode is formed on the drain connection structure.

[0024] In conjunction with the second aspect of the present application, in an optional implementation manner, the material of the drain connection structure includes at least one of the following: AlN, AlN-based alloy, InN, and InN-based alloy.

[0025] In combination with the second aspect of the present application, in an optional implementation, the material of the drain connection structure includes at least one of the following: AlN, InN, InAlN, AlScN, InScN, InAlScN, InAlGaN.

[0026] In conjunction with the second aspect of the present application, in an optional implementation manner, the material of the drain connection structure is doped with P-type ions.

[0027] In conjunction with the second aspect of the present application, in an optional implementation, forming the drain structure further comprises: after forming the drain connection structure on the heterojunction structure, forming a P-type material layer on the drain connection structure, the material of the P-type material layer comprising at least one of the following: V2O5, Cu2O, NiO, SnO, MoO3, WO3, P-type GaN;

[0028] A drain electrode is formed on the drain connection structure, specifically: a drain electrode is formed on the P-type material layer.

[0029] In combination with the second aspect of the present application, in an optional implementation, the thickness of the drain connection structure increases along a direction from the source structure to the drain structure.

[0030] In conjunction with the second aspect of the present application, in an optional embodiment, forming a heterojunction structure on the substrate includes: forming a channel layer on the substrate; forming a barrier layer on the channel layer; removing part of the barrier layer to form an opening exposing the channel layer; forming a drain connection structure on the heterojunction structure, including: forming the drain connection structure at least partially located in the opening to contact the channel layer; or,

[0031] A heterojunction structure is formed on the substrate, comprising: forming a channel layer on the substrate, the channel layer comprising a main body and a protrusion extending from the main body in a direction away from the substrate; forming a barrier layer covering the main body on the channel layer; and forming a drain connection structure on the heterojunction structure, comprising: forming a drain connection structure in contact with the protrusion.

[0032] The high electron mobility transistor and the preparation method thereof provided in the embodiments of the present application form a two-dimensional hole gas channel in at least a portion of the channel layer near the drain connection structure by setting a drain connection structure; thus, the carrier channel of the high electron mobility transistor includes not only a two-dimensional electron gas channel, but also a two-dimensional hole gas channel. The two-dimensional hole gas channel and the two-dimensional electron gas channel form an electron-hole recombination current, which can effectively increase the current density and realize current expansion, thereby improving device performance.

[0033] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0035] Figure 1 A schematic cross-sectional structure diagram of a high electron mobility transistor provided in one embodiment of the present application;

[0036] Figure 2 A schematic cross-sectional structure diagram of a high electron mobility transistor provided in another embodiment of the present application;

[0037] Figure 3 A schematic cross-sectional structure diagram of a high electron mobility transistor provided in yet another embodiment of the present application;

[0038] Figure 4 A schematic cross-sectional structure diagram of a high electron mobility transistor provided in yet another embodiment of the present application;

[0039] Figure 5 A schematic diagram of a process for preparing a high electron mobility transistor provided in an embodiment of the present application;

[0040] Figures 6 to 19 for Figure 1 The cross-sectional structure diagram of the high electron mobility transistor during the preparation process in the illustrated embodiment.

[0041] Description of reference numerals:

[0042] 100, substrate; 110, nucleation layer; 120, buffer layer; 130, heterojunction structure; 131, channel layer; 132, barrier layer; 133, two-dimensional electron gas channel; 134, two-dimensional hole gas channel; 140, P-type gallium nitride layer; 150, drain connection structure; 155, P-type material layer; 160, first passivation layer; 175, source ohmic contact layer; 176, drain ohmic contact layer; 171, source electrode; 172, drain electrode; 173, gate electrode; 180, interlayer dielectric layer; 191, source conductive plug; 192, drain conductive plug; 193, gate conductive plug; 211, source conductive layer; 212, drain conductive layer; 213, gate conductive layer; 220, second passivation layer; 231, source structure; 232, drain structure; 233, gate structure. DETAILED DESCRIPTION

[0043] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0044] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0045] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0046] When an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below may be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0047] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. In addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0048] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0049] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0050] The present application embodiment provides a high electron mobility transistor, please refer to Figures 1 to 3 The high electron mobility transistor includes: a substrate 100; a heterojunction structure 130 located on the substrate 100, the heterojunction structure 130 includes a channel layer 131 and a barrier layer 132 stacked in sequence in a direction away from the substrate 100, and a two-dimensional electron gas channel 133 is formed in a region of the channel layer 131 at least partially close to the barrier layer 132; a source structure 231, a drain structure 232 and a gate structure 233 located on the heterojunction structure 130; wherein the drain structure 232 includes a drain connection structure 150 and a drain electrode 172 stacked in sequence in a direction away from the channel layer 131, and a two-dimensional hole gas channel 134 is formed in a region of the channel layer 131 at least partially close to the drain connection structure 150.

[0051] It can be understood that the carrier channel of the high electron mobility transistor provided in the embodiment of the present application includes not only a two-dimensional electron gas channel 133, but also a two-dimensional hole gas channel 134, that is, a dual carrier channel is formed; the two-dimensional hole gas channel 134 and the two-dimensional electron gas channel 133 form an electron-hole recombination current, which can effectively increase the current density, realize the expansion of the current, and then improve the current capacity of the chip and improve the device performance. Among them, "chip" refers to an integrated circuit containing a high electron mobility transistor; "device" refers to a high electron mobility transistor or a package containing a high electron mobility transistor.

[0052] In the embodiment of the present application, the material of the substrate 100 may be any suitable material known to those skilled in the art, such as a silicon (Si) substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, or a sapphire substrate.

[0053] The substrate 100 may specifically be a growth substrate, and the heterojunction structure 130 may be an epitaxial layer formed on the growth substrate by using an epitaxial growth process.

[0054] In order to make the channel layer 131 have better crystal quality, a nucleation layer 110 and a buffer layer 120 may be formed between the substrate 100 and the heterojunction structure 130 (specifically, the substrate 100 and the channel layer 131); wherein the nucleation layer 110 is located between the substrate 100 and the buffer layer 120. In addition, the substrate 100 may also include other epitaxial layers, which are not specifically limited in the present application.

[0055] The material of the channel layer 131 may be an N-group alloy material, including but not limited to GaN, AlGaN, InGaN, InAlGaN, InAlScN, AlScN, InScN, etc. Further, the channel layer 131 may be an undoped material layer (e.g., an undoped GaN layer), so that at least the portion of the channel layer 131 below the two-dimensional electron gas presents a high resistance.

[0056] The material of the barrier layer 132 includes any material that can form a two-dimensional electron gas channel with the channel layer 131. Specifically, the material of the barrier layer 132 can also be an N-group alloy material, such as a gallium nitride-based alloy, specifically, for example, one or more of AlGaN, AlScN, InAlGaN and the like. Further, the material of the barrier layer 132 can be an undoped material (e.g., an undoped AlGaN layer); or, the barrier layer 132 can also be an N-doped material layer (e.g., an N-type doped AlGaN layer), so as to facilitate inducing a higher density of two-dimensional electron gas.

[0057] As an optional specific implementation, the material of the channel layer 131 may include gallium nitride; and the material of the barrier layer 132 may include a gallium nitride-based alloy.

[0058] A two-dimensional electron gas channel 133 is formed in at least a portion of the channel layer 131 in a region close to the barrier layer 132. Specifically, the band gap width of the barrier layer 132 is greater than the band gap width of the channel layer 131, so that electrons in the wide-gap barrier layer 132 and electrons on the surface of the barrier layer 132 overflow and move to the interface of the channel layer 131 close to the barrier layer 132 and are confined in a potential well formed at the interface, thereby forming a two-dimensional electron gas (2DEG).

[0059] The region in the channel layer 131 where the two-dimensional electron gas channel 133 is formed may specifically be: a region of the channel layer 131 close to the barrier layer 132 and whose projection in a direction perpendicular to the plane of the substrate 100 is located between the source structure 231 and the gate structure 233 and between the drain structure 232 and the gate structure 233 .

[0060] The material of the drain connection structure 150 includes any material that can form a two-dimensional hole gas channel with the channel layer 131. Specifically, the material of the drain connection structure 150 can be an N-group alloy material, including at least one of the following: AlN, AlN-based alloy, InN, InN-based alloy. As some optional embodiments, the material of the drain connection structure 150 includes at least one of the following: AlN, InN, InAlN, AlScN, InScN, InAlScN, InAlGaN. In addition to AlN and InN, the above materials also include AlN-based alloy materials and InN-based alloy materials, and are mainly alloys with IIIA and IIIB group elements. It can be understood that the piezoelectric polarization ability of the material is improved by alloying with IIIA and IIIB group elements. Specifically, the channel layer 131 (such as a gallium nitride layer) itself will produce spontaneous polarization in the direction of the substrate 100, so it is necessary to make the material of the drain connection structure 150 have a strong piezoelectric polarization ability in the opposite direction to improve the intensity of the two-dimensional hole gas generated on the surface of the channel layer. It should be noted that the embodiment of the present application does not exclude the situation where the material of the drain connection structure 150 and the material of the channel layer 131 are both selected from AlScN, InScN, InAlScN, InAlGaN and are selected the same, and for this case, the atomic ratio of each metal element in the material of the drain connection structure 150 is controlled to be different from the atomic ratio of each metal element in the material of the channel layer 131 to achieve the formation of a two-dimensional hole gas channel 134.

[0061] Next, the formation process and principle of two-dimensional hole gas (2DHG) are described by taking the case that the material of the channel layer 131 includes gallium nitride-based material and the material of the drain connection structure 150 includes aluminum nitride and / or aluminum nitride-based alloy as an example. Specifically, there are differences in the energy band structure between aluminum nitride and / or aluminum nitride-based alloy and gallium nitride material, and there is a joint effect of polarization effect and quantum confinement effect; in particular, due to the piezoelectric polarization phenomenon between aluminum nitride and / or aluminum nitride-based alloy and gallium nitride material, by controlling the atomic ratio of each element of aluminum nitride and / or aluminum nitride-based alloy, the piezoelectric polarization direction generated is opposite to the spontaneous polarization direction of gallium nitride; when the piezoelectric polarization effect is stronger than the spontaneous polarization effect of gallium nitride, 2DHG will be formed at gallium nitride and aluminum nitride and / or aluminum nitride-based alloy. The energy band difference at the heterojunction will cause 2DHG to be confined in the potential well at the interface.

[0062] A two-dimensional hole gas channel 134 is formed in at least a portion of the channel layer 131 near the drain connection structure 150 . Specifically, a two-dimensional hole gas channel 134 is formed in a region of the channel layer 131 near the drain connection structure 150 and overlapping with the drain connection structure 150 in the thickness direction of the channel layer 131 .

[0063] In some embodiments, the material of the drain connection structure 150 includes an aluminum nitride-based alloy. Thus, the type and content of other metal elements (such as In, Ga, etc.) in the aluminum nitride-based alloy can be adjusted to adjust the materials of the drain connection structure 150 and the channel layer 131 located below the drain connection structure 150 (specifically, the piezoelectric polarization of GaN and the corresponding spontaneous polarization) to better form the two-dimensional hole gas channel 134.

[0064] Furthermore, the aluminum nitride-based alloy includes InAlN and / or InAlGaN. The addition of the metal element In can make the drain connection structure 150 have a stronger polarization ability away from the substrate 100, thereby achieving a better deployment effect and increasing the strength of 2DHG generated on the surface of the channel layer 131.

[0065] In some embodiments, in order to increase the 2DHG concentration, the material of the drain connection structure 150 is doped with P-type ions, such as magnesium (Mg) ions. Specifically, the material of the drain connection structure 150 may include P-type AlN, or may include P-type aluminum nitride-based alloys. It should be noted that in addition to Mg ions, the embodiments of the present application do not exclude the case of doping with other IIA and / or IIB group ions. By ion doping, the material of the drain connection structure 150 is made P-type, which helps to avoid the depletion of N-type electrons and holes and increase the hole concentration.

[0066] The drain connection structure 150 can be formed by a deposition process commonly used in the art, such as molecular beam epitaxy (MBE), atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), etc., and the present application does not make any specific limitation on this.

[0067] Please continue to refer to Figures 1 to 3 In some embodiments, the barrier layer 132 includes an opening exposing the channel layer 131, and the drain connection structure 150 is at least partially located in the opening to contact the channel layer 131. It can be understood that the drain connection structure 150 is in contact with the channel layer 131, that is, the aluminum nitride and / or aluminum nitride-based alloy material is in contact with the gallium nitride material, thereby directly forming an AlN-GaN heterojunction structure.

[0068] Furthermore, the drain connection structure 150 may extend from the opening to above the barrier layer 132, so that the drain connection structure 150 may also include a portion located on the barrier layer 132. In this way, the portion of the drain connection structure 150 located on the barrier layer 132 may balance the electric field pile-up phenomenon and increase the withstand voltage capability of the device.

[0069] Next, please refer to Figure 2 . Figure 2 The embodiment shown and Figure 1 The difference between the embodiment in the embodiment is that the drain structure 232 also includes a P-type material layer 155, which is stacked between the drain connection structure 150 and the drain electrode 172; the material of the P-type material layer 155 includes at least one of the following: V2O5, Cu2O, NiO, SnO, MoO3, WO3, and P-type GaN. In this way, by setting the P-type material layer 155 in the drain structure 232, and the P-type material layer 155 has hole carriers, when the device is turned on, the drain end is a high voltage, and the holes in the P-type material layer 155 will undergo hole-electron recombination with the electrons in the two-dimensional electron gas channel 133, thereby further increasing the carrier channel, so that the current is further strengthened, and ultimately improving the device performance.

[0070] As a specific example, the P-type material layer 155 can completely cover the upper surface of the drain connection structure 150, so that the projection of the P-type material layer 155 and the projection of the drain connection structure 150 overlap in a direction perpendicular to the plane of the substrate 100. However, the present application is not limited thereto, and the P-type material layer 155 and the drain connection structure 150 can also be arranged in a staggered manner according to actual needs to achieve flexible adjustment of the current.

[0071] Next, please refer to Figure 3 . Figure 3 The embodiment shown and Figure 1 The difference between the embodiment in the embodiment is that the thickness of the drain connection structure 150 increases along the direction from the source structure 231 to the drain structure 232. In this way, the drain connection structure 150 is thinner on the side close to the source structure 231 (that is, the side close to the gate structure 233), and the influence on the two-dimensional electron gas channel 133 is smaller; the drain connection structure 150 is thicker on the side away from the source structure 231 (that is, the side away from the gate structure 233), and the two-dimensional hole gas channel 134 formed has more holes; thus, a transition is formed between the two-dimensional electron gas channel 133 and the two-dimensional hole gas channel 134, so that the channel electric field distribution in the drain end region is more uniform, and the device performance is further improved.

[0072] Furthermore, in order to better achieve the channel electric field distribution condition for the drain end region, the thickness difference between the end of the drain connection structure 150 away from the source structure 231 and the end close to the source structure 231 is between 10nm and 100nm; along the direction parallel to the plane where the substrate 100 is located, the distance between the end of the drain connection structure 150 away from the source structure 231 and the end close to the source structure 231 is 1%-20% of the distance between the drain and the gate. The distance between the drain and the gate refers to the distance between the drain connection structure 150 and the P-type gallium nitride layer 140.

[0073] It should also be noted that Figure 2 The technical features in the illustrated embodiment can be Figure 3 The technical features in the illustrated embodiments are combined arbitrarily. Specifically, for example, in some embodiments, the thickness of the drain connection structure 150 increases along the direction from the source structure 231 to the drain structure 232; and the drain structure 232 further includes a P-type material layer 155, which is stacked on the drain connection structure 150 with increased thickness.

[0074] Next, please refer to Figure 4 . Figure 4 The embodiment shown and Figure 1 The main difference between the embodiments is that the channel layer 131 includes a main body portion located between the lower surface of the barrier layer 132 and the substrate 100 and a protrusion portion extending from the main body portion in a direction away from the substrate 100, the lower surface of the barrier layer 132 is the surface of the barrier layer 132 on the side close to the substrate 100, the protrusion portion is not covered by the barrier layer 132, and the drain connection structure 150 is in contact with the protrusion portion.

[0075] It should be noted that although Figures 1 to 4 , the drain connection structure 150 is shown to be in contact with the channel layer 131, but the present application does not exclude the case where the drain connection structure 150 is not in direct contact with the channel layer 131 (for example, it is located on the barrier layer 132). Those skilled in the art can adopt various deformations to set the drain connection structure 150 without departing from the improved concept of the present application, so as to induce a two-dimensional hole gas channel 134 in the channel layer 131.

[0076] It should also be noted that Figure 4 The technical features in the embodiment shown can obviously also be used with Figure 2 and Figure 3The technical features in the illustrated embodiments are combined arbitrarily. Specifically, for example, in some embodiments, on the basis of the drain connection structure 150 being in contact with the protrusion, the thickness of the drain connection structure 150 increases along the direction from the source structure 231 to the drain structure 232; and the drain structure 232 further includes a P-type material layer 155, and the P-type material layer 155 is stacked on the drain connection structure 150 with increased thickness.

[0077] The present application also provides a method for preparing a high electron mobility transistor. Figure 5 , the method comprising:

[0078] Step S01, providing a substrate;

[0079] Step S02, forming a heterojunction structure on a substrate, the heterojunction structure comprising a channel layer and a barrier layer formed in sequence, at least a portion of the channel layer near the barrier layer is used to form a two-dimensional electron gas channel;

[0080] Step S03, forming a source structure, a drain structure and a gate structure on the heterojunction structure; wherein forming the drain structure includes: forming a drain connection structure on the heterojunction structure so that a two-dimensional hole gas channel is formed in at least a portion of the channel layer in an area close to the drain connection structure; and forming a drain electrode on the drain connection structure.

[0081] It can be understood that the method for preparing a high electron mobility transistor provided in the embodiment of the present application forms a two-dimensional hole gas channel in the channel layer by setting a drain connection structure at the drain end; the two-dimensional hole gas channel and the two-dimensional electron gas channel form an electron-hole recombination current, which can effectively increase the current density and achieve current expansion, thereby improving the current capacity of the chip and improving device performance.

[0082] Next, we will combine Figures 6 to 19 , the high electron mobility transistor and the preparation method thereof provided in the embodiments of the present application are further described in detail.

[0083] First, please refer to Figure 6 A substrate 100 is provided. The substrate 100 may specifically be a silicon (Si) substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, or a sapphire substrate.

[0084] Next, epitaxial growth is performed on the substrate 100 . Specifically, a channel layer 131 is formed on the substrate 100 ; and a barrier layer 132 is formed on the channel layer 131 .

[0085] Optionally, before growing the channel layer 131 , the nucleation layer 110 and the buffer layer 120 may be sequentially formed on the substrate 100 . Then, the channel layer 131 and the barrier layer 132 may be sequentially formed on the substrate 100 .

[0086] As an optional specific implementation, the material of the channel layer 131 includes gallium nitride, and the material of the barrier layer 132 includes a gallium nitride-based alloy. The channel layer 131 and the barrier layer 132 together form a heterojunction structure 130, thereby inducing a two-dimensional electron gas in a region of the channel layer 131 at least partially close to the barrier layer 132.

[0087] Please continue to refer to Figure 6 In the actual preparation process, a P-type gallium nitride layer 140 can also be formed on the barrier layer 132 to prepare a P-type gallium nitride high electron mobility transistor. Figure 1 It is understood that by arranging the P-type gallium nitride layer 140 at the gate end, the P-type gallium nitride layer can deplete the two-dimensional electron gas channel 133 under the gate, so that the two-dimensional electron gas channel 133 is disconnected in the area under the gate, so that only when the turn-on voltage is applied to the gate, the transistor is turned on and the source and drain can be connected, thereby forming a normally closed transistor. However, it should be understood that the present application is not limited to this, and the improved concept of the present application can obviously also be applied to other types of high electron mobility transistors.

[0088] in this way, Figure 6 The cross-sectional structure of an epitaxial wafer used to form a high electron mobility transistor is shown.

[0089] Next, please refer to Figure 7 The P-type gallium nitride layer 140 is patterned; specifically, a portion of the P-type gallium nitride layer 140 is removed so that the remaining P-type gallium nitride layer 140 is located within the predetermined gate formation region. The removal of a portion of the P-type gallium nitride layer 140 can be achieved by using a photolithography-etching process well known in the art, which will not be discussed in detail here.

[0090] The two-dimensional electron gas channel 133 is disconnected in the region below the P-type gallium nitride layer 140 .

[0091] Next, please refer to Figure 8 In some optional embodiments, a portion of the barrier layer 132 is removed to form an opening exposing the channel layer 131 ; thereby defining a pattern of the drain region through the opening.

[0092] In actual preparation, the removal of part of the barrier layer 132 can obviously be achieved by using a photolithography-etching process well known in the art.

[0093] Next, please refer to Fig. 9 and Fig.10 A drain connection structure 150 is formed on the heterojunction structure 130 .

[0094] In the actual preparation process, a layer of material of the drain connection structure 150 may be deposited first (see Fig. 9); then through a patterning process (specifically, for example, a photolithography-etching process), a drain connection structure 150 is formed in a predetermined area (please refer to Fig.10 ).

[0095] In the embodiment where the barrier layer 132 includes an opening exposing the channel layer 131, the drain connection structure 150 is formed at least partially in the opening to contact the channel layer 131. In addition, the drain connection structure 150 may further include a portion covering the barrier layer 132.

[0096] The material of the drain connection structure 150 includes any material that can form a two-dimensional hole gas channel with the channel layer 131. Specifically, the material of the drain connection structure 150 can be an N-group alloy material, for example, one or more of AlN, InN, InAlN, AlScN, InScN, and InAlScN. In addition to AlN and InN, the above-mentioned materials also include AlN-based alloy materials and InN-based alloy materials, and are mainly alloys with IIIA and IIIB group elements. It can be understood that the piezoelectric polarization ability of the material is improved by alloying with IIIA and IIIB group elements. Specifically, the channel layer 131 (such as a gallium nitride layer) itself will produce spontaneous polarization in the direction of the substrate 100, so it is necessary to make the material of the drain connection structure 150 have a strong piezoelectric polarization ability in the opposite direction to improve the intensity of the two-dimensional hole gas generated on the surface of the channel layer.

[0097] As an optional specific embodiment, the material of the channel layer 131 includes a gallium nitride-based material; the material of the drain connection structure 150 includes aluminum nitride and / or an aluminum nitride-based alloy, so that a two-dimensional hole gas channel 134 is formed in at least a portion of the channel layer 131 in an area close to the drain connection structure 150.

[0098] Optionally, the aluminum nitride-based alloy includes InAlN and / or InAlGaN. The addition of the metal element In can make the drain connection structure 150 have a stronger polarization ability away from the substrate 100, thereby achieving a better deployment effect and increasing the strength of 2DHG generated on the surface of the channel layer 131.

[0099] Optionally, in order to increase the 2DHG concentration, the material of the drain connection structure 150 is doped with P-type ions, such as magnesium (Mg) ions. Specifically, the material of the drain connection structure 150 may include P-type AlN, or may include P-type aluminum nitride-based alloys, etc. It should be noted that, in addition to Mg ions, the embodiments of the present application do not exclude the case of doping with other IIA and / or IIB group ions. By ion doping, the material of the drain connection structure 150 is made P-type, which helps to avoid the depletion of N-type electrons and holes and increase the hole concentration.

[0100] Next, please refer to Fig.11The first passivation layer 160 is formed. In actual preparation, step etching may be further performed to define the active region of the device. The first passivation layer 160 is patterned to form openings in the first passivation layer 160 to expose the source region and the drain region.

[0101] Next, please refer to Fig.12 A source ohmic contact layer 175 and a drain ohmic contact layer 176 are respectively formed in the opening of the first passivation layer 160 , thereby reducing the contact resistance between the metal material and the semiconductor material.

[0102] Next, please refer to Fig.13 The opening of the first passivation layer 160 is filled with a metal material to form a source electrode 171 and a drain electrode 172 , respectively.

[0103] Next, please refer to Fig.14 The first passivation layer 160 is patterned again to form an opening in the first passivation layer 160 that exposes the gate region; specifically, an opening that exposes the P-type gallium nitride layer 140 is formed.

[0104] Next, please refer to Fig.15 The opening of the first passivation layer 160 exposing the P-type gallium nitride layer 140 is filled with a metal material to prepare the gate electrode 173 .

[0105] Next, please refer to Fig.16 An interlayer dielectric layer 180 is formed, and the interlayer dielectric layer (Inter Metal Dielectric, IMD) covers the surface of the entire structure.

[0106] Next, please refer to Fig.17 Contact holes are formed in the interlayer dielectric layer 180 to expose the source electrode 171 , the drain electrode 172 , and the gate electrode 173 , respectively, and metal materials are filled in the contact holes to form a source conductive plug 191 , a drain conductive plug 192 , and a gate conductive plug 193 , respectively.

[0107] Next, please refer to Fig.18 A source conductive layer 211, a drain conductive layer 212 and a gate conductive layer 213 are formed; wherein the source conductive layer 211 is conductively connected to the source electrode 171 through the source conductive plug 191, the drain conductive layer 212 is conductively connected to the drain electrode 172 through the drain conductive plug 192, and the gate conductive layer 213 is conductively connected to the gate electrode 173 through the gate conductive plug 193.

[0108] In actual preparation, a conductive layer covering the interlayer dielectric layer 180 may be formed first, and then the conductive layer may be patterned to form a source conductive layer 211 , a drain conductive layer 212 , and a gate conductive layer 213 that are insulated and isolated from each other.

[0109] Next, please refer to Fig.19 A second passivation layer 220 is formed, and the second passivation layer 220 covers the surface of the structure formed in the previous process, and has openings that expose the source conductive layer 211, the drain conductive layer 212, and the gate conductive layer 213 respectively.

[0110] In actual preparation, a second passivation layer 220 covering the surface of the structure formed in the previous process may be formed first, and then the second passivation layer 220 may be patterned to form openings that expose the source conductive layer 211 , the drain conductive layer 212 and the gate conductive layer 213 , respectively.

[0111] Finally, the back side of the substrate 100 may be thinned to form a structure as shown in FIG. Figure 1 .

[0112] It should be noted that Figures 6 to 19 Only to form Figure 1 The cross-sectional structure of the high electron mobility transistor in the manufacturing process in the illustrated embodiment is shown as an example.

[0113] In order to form Figure 2 In the high electron mobility transistor structure in the embodiment shown, the above method may also include: after forming the drain connection structure 150 on the heterojunction structure 130, forming a P-type material layer 155 on the drain connection structure 150; next, forming a drain electrode 172 on the drain connection structure 150, specifically: forming the drain electrode 172 on the P-type material layer 155.

[0114] In addition, in order to form Figure 3 In the embodiment shown, the high electron mobility transistor structure can be Fig. 9 As shown, after a material layer of the drain connection structure 150 is deposited, the material layer is subjected to multiple photolithography-etching processes to form a drain connection structure 150 with increasing thickness along a direction from the source structure 231 to the drain structure 232 .

[0115] In order to form Figure 4 The high electron mobility transistor structure in the embodiment shown is Figure 6Differently, after providing the substrate 100, a channel layer 131 is formed on the substrate 100, and the channel layer 131 includes a main body and a protrusion extending from the main body in a direction away from the substrate 100; a barrier layer 132 covering the main body is formed on the channel layer 131. In the actual preparation process, a thick channel layer 131 can be formed first, and then a portion of the channel layer 131 is removed by a patterning process (specifically, for example, a photolithography-etching process) to form a recessed area in the channel layer 131; thereby, the preset formation position of the barrier layer 132 is defined by the recessed area. The portion of the channel layer 131 located below the bottom surface of the recessed area is the main body, and the portion located beside the recessed area that is not removed is the protrusion. The barrier layer 132 is formed to not cover the protrusion of the channel layer 131. Further, the upper surface of the barrier layer 132 can be flush with the upper surface of the protrusion. Next, in the step of forming the drain connection structure 150 , the drain connection structure 150 is formed on the protrusion and in contact with the protrusion. It can be understood that the drain connection structure 150 can also be partially located on the barrier layer 132 .

[0116] In addition, the material layer of the drain connection structure 150 may be subjected to multiple photolithography-etching processes to form the drain connection structure 150 with increasing thickness along the direction from the source structure 231 to the drain structure 232 .

[0117] It should be noted that the high electron mobility transistor embodiment provided in the present application and the high electron mobility transistor preparation method embodiment belong to the same concept; the various technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict. However, it should be further noted that the high electron mobility transistor provided in the embodiment of the present application, the combination of its various technical features can already solve the technical problem to be solved by the present application; therefore, the high electron mobility transistor provided in the embodiment of the present application may not be limited by the high electron mobility transistor preparation method provided in the embodiment of the present application, and any high electron mobility transistor prepared by the preparation method that can form the high electron mobility transistor structure provided in the embodiment of the present application is within the scope of protection of the present application.

[0118] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes may also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may also be combined arbitrarily to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A high electron mobility transistor, characterized in that: include: substrate; a heterojunction structure located on the substrate, the heterojunction structure comprising a channel layer and a barrier layer stacked in sequence in a direction away from the substrate, a two-dimensional electron gas channel being formed in at least a portion of the channel layer in a region close to the barrier layer; A source structure, a drain structure and a gate structure located on the heterojunction structure; The drain structure includes a drain connection structure and a drain electrode stacked in sequence in a direction away from the channel layer, and a two-dimensional hole gas channel is formed in at least a portion of the channel layer in a region close to the drain connection structure.

2. The high electron mobility transistor according to claim 1, characterized in that: The material of the drain connection structure includes at least one of the following: AlN, AlN-based alloy, InN, and InN-based alloy.

3. The high electron mobility transistor according to claim 1, characterized in that: The material of the drain connection structure includes at least one of the following: AlN, InN, InAlN, AlScN, InScN, InAlScN, and InAlGaN.

4. The high electron mobility transistor according to any one of claims 1 to 3, characterized in that: The material of the drain connection structure is doped with P-type ions.

5. The high electron mobility transistor according to claim 1, characterized in that: The drain structure also includes a P-type material layer, which is stacked between the drain connection structure and the drain electrode; the material of the P-type material layer includes at least one of the following: V2O5, Cu2O, NiO, SnO, MoO3, WO3, and P-type GaN.

6. The high electron mobility transistor according to claim 1, characterized in that: The thickness of the drain connection structure increases along a direction from the source structure to the drain structure.

7. The high electron mobility transistor according to claim 1, characterized in that: The barrier layer comprises an opening exposing the channel layer, and the drain connection structure is at least partially located in the opening to contact the channel layer; or, The channel layer includes a main body portion located between the lower surface of the barrier layer and the substrate and a protrusion portion extending from the main body portion in a direction away from the substrate. The lower surface of the barrier layer is a surface of the barrier layer close to the substrate. The protrusion portion is not covered by the barrier layer, and the drain connection structure is in contact with the protrusion portion.

8. A method for preparing a high electron mobility transistor, characterized in that: The method comprises: providing a substrate; forming a heterojunction structure on the substrate, wherein the heterojunction structure comprises a channel layer and a barrier layer formed in sequence, wherein at least a portion of the channel layer near the barrier layer is used to form a two-dimensional electron gas channel; forming a source structure, a drain structure and a gate structure on the heterojunction structure; Wherein, forming the drain structure comprises: forming a drain connection structure on the heterojunction structure, so that a two-dimensional hole gas channel is formed in at least a portion of the channel layer in a region close to the drain connection structure; A drain electrode is formed on the drain connection structure.

9. The method for preparing a high electron mobility transistor according to claim 8, characterized in that: The material of the drain connection structure includes at least one of the following: AlN, AlN-based alloy, InN, and InN-based alloy.

10. The method for preparing a high electron mobility transistor according to claim 8, characterized in that: The material of the drain connection structure includes at least one of the following: AlN, InN, InAlN, AlScN, InScN, InAlScN, and InAlGaN.

11. The method for preparing a high electron mobility transistor according to any one of claims 8 to 10, characterized in that: The material of the drain connection structure is doped with P-type ions.

12. The method for preparing a high electron mobility transistor according to claim 8, characterized in that: Forming the drain structure further comprises: after forming the drain connection structure on the heterojunction structure, forming a P-type material layer on the drain connection structure, wherein the material of the P-type material layer comprises at least one of the following: V2O5, Cu2O, NiO, SnO, MoO3, WO3, and P-type GaN; A drain electrode is formed on the drain connection structure, specifically: a drain electrode is formed on the P-type material layer.

13. The method for preparing a high electron mobility transistor according to claim 8, characterized in that: The thickness of the drain connection structure increases along a direction from the source structure to the drain structure.

14. The method for preparing a high electron mobility transistor according to claim 8, characterized in that: Forming a heterojunction structure on the substrate, comprising: forming a channel layer on the substrate; forming a barrier layer on the channel layer; removing part of the barrier layer to form an opening exposing the channel layer; forming a drain connection structure on the heterojunction structure, comprising: forming the drain connection structure at least partially located in the opening to contact the channel layer; or, A heterojunction structure is formed on the substrate, comprising: forming a channel layer on the substrate, the channel layer comprising a main body and a protrusion extending from the main body in a direction away from the substrate; forming a barrier layer covering the main body on the channel layer; and forming a drain connection structure on the heterojunction structure, comprising: forming a drain connection structure in contact with the protrusion.

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