Circuit for enhancing input power supply ripple suppression capability and low voltage drop linear regulator

Abstract

The embodiment of the present disclosure provides a circuit and a low voltage dropout linear regulator for enhancing the ripple suppression capability of the input power supply. The circuit for enhancing the ripple suppression capability of the input power supply includes: a resistor-type buffer, a ripple detection circuit, and a super source follower, wherein the resistor-type buffer receives the error output signal of the error amplifier of the low voltage dropout linear regulator, and transmits the error output signal with equal amplitude to the input end of the super source follower; the ripple detection circuit converts the change of the input power supply into a first current through a first resistor, and obtains a feedforward current through a current mirror to couple the feedforward current to the output end of the resistor-type buffer and the input end of the super source follower; the super source follower reduces the impedance of the output end of the super source follower by increasing the equivalent transconductance of the transistor, and couples the output end of the super source follower to the power tube of the LDO to drive the power tube. The problem of the existing technology occupying a large area, having a poor actual application effect, and limiting the size of the power tube is solved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of power supply technology, and in particular, to a circuit and a low voltage dropout linear regulator for enhancing the input power supply ripple suppression capability. Background Art

[0002] Input power supply ripple suppression is to suppress the noise of the input power supply. In low voltage drop linear regulators, the power supply rejection ratio (PSR) is usually used to measure the suppression capability. The power supply rejection ratio is defined as the ratio of the output voltage change caused by the input voltage change to the input voltage change, that is, PSR = dVout / dVin, usually expressed in dB, that is, PSR dB =20log(dVout / dVin), the smaller the ratio, the better. The smaller the PSR, the stronger the low voltage drop linear regulator's ability to suppress input power supply noise, the higher the power supply noise suppression performance, and the smaller the output voltage fluctuation.

[0003] like Figure 1 As shown in FIG. 1 , a circuit diagram of a low-dropout linear regulator LDO is shown, including an error amplifier EA, a power tube M, and a feedback network. It can utilize closed-loop negative feedback technology to collect the signal on the output voltage Vout through the feedback network, process it through the error amplifier EA, and adjust the gate voltage of the power tube M, thereby suppressing the influence of the input voltage Vin ripple noise and load changes on the output voltage Vout and stabilizing the output voltage Vout. Figure 1 It can be seen that the LDO circuit can suppress the ripple of the input power supply Vin through the feedback network, but in actual applications, the low voltage drop linear regulator LDO is often used as the post-stage regulator of the switching power supply (such as BUCK, BOOST) circuit, and is widely used, such as consumer electronics such as home appliances and mobile communication equipment; industrial electronics such as server memory and motor drive control; automotive electronics such as vehicle-mounted millimeter-wave radar and vehicle-mounted cameras. Therefore, it is very meaningful to further enhance the input voltage suppression capability of the LDO, especially the power supply noise suppression capability in the frequency range of 100kHz~5MHz.

[0004] There are five ways to deal with the noise of the input power supply of the low-dropout linear regulator: 1) The input power supply noise is transmitted to the reference voltage Vref, affecting the output voltage through the error amplifier and the power tube; 2) The input power supply noise is transmitted to the gate of the power tube through the error amplifier, affecting the output voltage; 3) The input power supply noise affects the output voltage through the transconductance of the power tube; 4) The input power supply noise affects the output voltage through the Rout of the power tube; 5) The input power supply noise affects the output voltage through the capacitance between the gate and source and between the gate and drain of the power tube; There are many ways to enhance the input ripple suppression capability in the prior art, including connecting a low-pass filter with a very low cutoff frequency in series between the reference voltage and the input of the error amplifier; increasing the loop bandwidth of the low-dropout linear regulator, and enhancing the input power supply ripple suppression performance of the linear regulator through the effect of the overall loop; using NMOS instead of PMOS as the power tube; adding a common source and common gate device between the power tube and the output voltage; adding an additional feedforward ripple injection circuit to make the source and gate voltage difference of the PMOS power tube not change with the input voltage, etc.

[0005] Among them, the method of adding an additional feedforward ripple injection circuit is more widely used, and the current mode feedforward ripple injection technology is more commonly used than the voltage mode feedforward ripple injection technology due to its simple structure. Figure 2 As shown, it is an exemplary circuit diagram of an existing method of enhancing the input power suppression capability of LDO through current mode feedforward ripple injection. The specific working principle is: the resistance RF, the capacitor CF, and the operational amplifier A1 are turned on to make the voltage at point A not change with the input power supply Vin. When the input power supply Vin changes, the source voltage of M6 changes, and the gate and drain voltages remain unchanged, so that the change of the input power supply Vin is converted into current through the transconductance of M6 and flows through M1. Then, the feedforward current is obtained through the current mirror formed by M1, M2, M3, and M4 and injected into the source of M7, that is, point C, so that the change amplitude of the voltage at point C is equal to the change amplitude of the input power supply Vin, so that the source and gate voltage difference of the power tube M9 does not change with the input voltage Vin. The inventor applied Figure 2 When using the current mode feedforward ripple injection method in the circuit, at least the following problems are found: 1) The VBIAS voltage needs to be independent of the input power supply Vin, so RF needs to be a large resistor greater than 100 megohms, which will occupy a large area; 2) The matching degree between M6 and M7 directly determines the effect of the circuit on the power supply ripple suppression capability. Both M6 and M7 are P-type MOS tubes, and the matching effect is not good in actual semiconductor process manufacturing, which will affect the effect of the circuit in actual applications; 3) The circuit can only use the ordinary PMOS source follower composed of M7 and M8 to drive the gate of the subsequent PMOS power tube M9, which limits the size of the PMOS power tube M9 and limits its application range. Summary of the invention

[0006] The embodiments described herein provide a circuit and a low voltage dropout linear regulator for enhancing the input power ripple suppression capability, in order to solve at least one problem existing in the circuit structure of the above-mentioned existing current mode feedforward ripple injection method for enhancing the input power suppression capability of the LDO.

[0007] According to a first aspect of the present disclosure, a circuit for enhancing the ripple suppression capability of an input power supply is provided, wherein the input power supply is an input power supply in a low voltage difference linear regulator, and the circuit comprises: a resistor-type buffer, a ripple detection circuit, and a super source follower, wherein the resistor-type buffer is configured to receive an error output signal of an error amplifier of the low voltage difference linear regulator, and transmit the error output signal with equal amplitude to an input end of the super source follower through a voltage-to-current circuit and a current-to-voltage circuit; the ripple detection circuit is configured to convert a change of the input power supply into a first current through a first resistor, and obtain a feedforward current through a current mirror to couple the feedforward current to an output end of the resistor-type buffer and an input end of the super source follower, wherein the feedforward current is a current reflecting the change of the input power supply; and the super source follower is configured to reduce the impedance of the output end of the super source follower by increasing the equivalent transconductance of a first transistor and a second transistor, and couple the output end of the super source follower to a control electrode of a power tube in the low voltage difference linear regulator to drive the power tube.

[0008] Optionally, the resistor-type buffer includes: the voltage-to-current circuit, the first current mirror, and the current-to-voltage circuit, wherein the voltage-to-current circuit is configured to transmit the error output signal with equal amplitude to the first node through the first operational amplifier, and convert the voltage of the first node into a second current through the second resistor; the first current mirror is configured to copy the second current and transmit it to the second node; the current-to-voltage circuit is configured to convert the copied second current into a voltage through the third resistor and output it from the second node, and the second node is the output end of the resistor-type buffer.

[0009] Optionally, the ripple detection circuit includes: an acquisition module and a conversion module, wherein the acquisition module is configured to couple one end of the first resistor to the input power supply, keep the voltage at the other end of the first resistor unchanged through a second operational amplifier, and convert the change of the input power supply into the first current through the first resistor when the input power supply changes; and the conversion module is configured to convert the first current into the feedforward current through a second current mirror and a third current mirror.

[0010] Optionally, the super source follower includes: a main circuit and a bias signal generating circuit, wherein the main circuit includes at least the first transistor and the second transistor, and the control electrode and the first electrode of the first transistor are configured as the input and output ends of the super source follower respectively, and the impedance of the output end of the super source follower is reduced by the negative feedback of the second transistor; the bias signal generating circuit is configured to provide a bias current to the main circuit.

[0011] Optionally, the voltage-to-current circuit includes: the first operational amplifier, a third transistor, and the second resistor, wherein the positive input terminal of the first operational amplifier is coupled to the error output signal, the negative input terminal of the first operational amplifier is respectively coupled to the first electrode of the third transistor and one end of the second resistor, and the output terminal of the first operational amplifier is coupled to the control electrode of the third transistor; the second electrode of the third transistor is coupled to the first current mirror; the other end of the second resistor is coupled to the ground terminal; the first current mirror includes: a fourth transistor and a fifth transistor, wherein the control electrode of the fourth transistor is respectively coupled to the second electrode of the fourth transistor, the voltage-to-current circuit, and the control electrode of the fifth transistor, the first electrode of the fourth transistor and the first electrode of the fifth transistor are both coupled to the input power supply, and the second electrode of the fifth transistor is coupled to the current-to-voltage circuit; the current-to-voltage circuit includes the third resistor, wherein one end of the third resistor is respectively coupled to the first current mirror, the input end of the super source follower, and the feed-forward current as the output end of the resistance-type buffer, and the other end of the third resistor is coupled to the ground terminal.

[0012] Optionally, the resistor-type buffer further includes: a phase adjustment circuit configured to adjust the phase of the output end of the resistor-type buffer to be consistent with the input power supply according to the first capacitor and the second capacitor.

[0013] Optionally, the phase adjustment circuit includes: the first capacitor, the second capacitor, a sixth transistor, and a seventh transistor, wherein one end of the first capacitor is coupled to the input power supply, and the other end of the first capacitor is coupled to the second electrode of the sixth transistor; one end of the second capacitor is coupled to the ground, and the other end of the second capacitor is coupled to the second electrode of the seventh transistor; the control electrode of the sixth transistor is coupled to a first phase adjustment selection signal, and the first electrode of the sixth transistor is respectively coupled to the control electrode of the fifth transistor and the first electrode of the seventh transistor, and the first phase adjustment selection signal is a signal for selecting the first capacitor to be connected to the control electrode of the fifth transistor; the control electrode of the seventh transistor is coupled to a second phase adjustment selection signal, and the second phase adjustment selection signal is a signal for selecting the second capacitor to be connected to the control electrode of the fifth transistor.

[0014] Optionally, the acquisition module includes: the first resistor, the second operational amplifier, the fourth resistor, the MOS tube equivalent resistor, the first current source, the third capacitor, and the eighth transistor, wherein the other end of the first resistor is respectively coupled to the negative input end of the second operational amplifier and the first electrode of the eighth transistor; the positive input end of the second operational amplifier is respectively coupled to one end of the MOS tube equivalent resistor and one end of the third capacitor; the other end of the MOS tube equivalent resistor is respectively coupled to one end of the fourth resistor and one end of the first current source; the other end of the third capacitor and the other end of the first current source are both coupled to the ground; the other end of the fourth resistor is coupled to the input power supply; the second electrode of the eighth transistor is coupled to the conversion module, and the The second electrode of the eighth transistor outputs the first current; the conversion module includes the second current mirror composed of a ninth transistor and a tenth transistor, and the third current mirror composed of an eleventh transistor and a twelfth transistor, wherein the control electrode of the ninth transistor is respectively coupled to the control electrode of the tenth transistor and the second electrode of the ninth transistor, the first electrode of the ninth transistor and the first electrode of the tenth transistor are both coupled to the ground terminal, the second electrode of the tenth transistor is respectively coupled to the control electrode of the eleventh transistor, the second electrode of the eleventh transistor, and the control electrode of the twelfth transistor, the first electrode of the eleventh transistor and the first electrode of the twelfth transistor are both coupled to the input power supply, and the second electrode of the twelfth transistor outputs the feedforward current.

[0015] Optionally, the main circuit includes: the first transistor, the second transistor, the thirteenth transistor, and the fourteenth transistor, wherein the first electrode of the first transistor is also coupled to the second electrode of the thirteenth transistor and the second electrode of the second transistor, the second electrode of the first transistor is respectively coupled to the control electrode of the second transistor and the second electrode of the fourteenth transistor, the first electrode of the second transistor and the first electrode of the fourteenth transistor are both coupled to the ground terminal, the first electrode of the thirteenth transistor is coupled to the input power supply, and the control electrode of the thirteenth transistor and the control electrode of the fourteenth transistor are both coupled to the bias signal generating circuit; the bias signal generating circuit includes a second current source and fifteen to seventeen transistors, wherein one end of the second current source is coupled to the input power supply, and the other end of the second current source is respectively coupled to the control electrode of the fifteenth transistor, the second electrode of the fifteenth transistor, the control electrode of the sixteenth transistor, and the control electrode of the fourteenth transistor in the main circuit, the first electrode of the fifteenth transistor and the first electrode of the sixteenth transistor are both coupled to the ground terminal, the second electrode of the sixteenth transistor is respectively coupled to the second electrode of the seventeenth transistor, the control electrode of the seventeenth transistor, and the control electrode of the thirteenth transistor in the main circuit, and the first electrode of the seventeenth transistor is coupled to the input power supply.

[0016] Optionally, the MOS tube equivalent resistance includes a third current source, an eighteenth transistor, and a nineteenth transistor, wherein one end of the third current source is coupled to the ground end, the other end of the third current source is respectively coupled to the second pole of the eighteenth transistor, the control pole of the eighteenth transistor, and the control pole of the nineteenth transistor, the first pole of the eighteenth transistor is coupled to the second pole of the nineteenth transistor, the first pole of the nineteenth transistor serves as one end of the MOS tube equivalent resistance, and the first pole of the eighteenth transistor serves as the other end of the MOS tube equivalent resistance.

[0017] According to a second aspect of the present disclosure, a low voltage dropout linear regulator is provided, and the low voltage dropout linear regulator includes the circuit for enhancing the input power ripple suppression capability as described in any one of the first aspects above.

[0018] In the circuit for enhancing the input power supply ripple suppression capability and the low voltage difference linear regulator of the disclosed embodiments, a resistive buffer is added between the error amplifier and the super source follower, thereby changing the overall architecture of the circuit. This change enables the feedforward current output by the ripple detection circuit to be coupled to the input end of the super source follower instead of the output end, so there is no need for equivalent transconductance matching between the ripple detection circuit and the super source follower. Therefore, the ripple detection circuit can be combined with the super source follower, thereby enabling the use of large-sized power tubes. In addition, the ripple detection circuit itself is also improved, so that the effect of improving the power supply ripple suppression capability is changed from being determined by the matching of the MOS tube to being determined by the matching of the resistor. In the integrated circuit, the matching degree of the resistor is much better than the matching length of the MOS tube, thereby improving the effect in practical applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:

[0020] Figure 1 A schematic diagram of a circuit of an existing low dropout linear regulator LDO is shown;

[0021] Figure 2 An exemplary circuit diagram of enhancing the input power rejection capability of an LDO by current-mode feed-forward ripple injection is shown;

[0022] Figure 3 A schematic block diagram of a circuit for enhancing input power supply ripple suppression capability according to an embodiment of the present disclosure is shown;

[0023] Figure 4 An exemplary circuit diagram of a resistor-type buffer in an embodiment of the present disclosure is shown;

[0024] Figure 5 An exemplary circuit diagram of a ripple detection circuit in an embodiment of the present disclosure is shown;

[0025] Figure 6 An exemplary circuit diagram of an equivalent resistance of a MOS tube in an embodiment of the present disclosure is shown;

[0026] Figure 7 An exemplary block diagram of a super source follower according to an embodiment of the present disclosure is shown;

[0027] Figure 8 An exemplary circuit diagram of another resistor-type buffer according to an embodiment of the present disclosure is shown;

[0028] Elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the specification and the relevant technology, and will not be interpreted in an idealized or overly formal form unless otherwise clearly defined herein. As used herein, statements that two or more parts are "connected" or "coupled" together should refer to these parts being directly combined together or combined through one or more intermediate components. In addition, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0031] In all embodiments of the present disclosure, since the source and drain of a metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle end of the MOS transistor is referred to as a control electrode, and the remaining two ends of the MOS transistor are referred to as a first electrode and a second electrode, respectively. In addition, for the convenience of unified expression, in the context, the base of a bipolar transistor (BJT) is referred to as a control electrode, the emitter of the BJT is referred to as a first electrode, and the collector of the BJT is referred to as a second electrode. In addition, terms such as "first" and "second" are only used to distinguish one component (or a portion of a component) from another component (or another portion of a component).

[0032] In order to solve the problems of the existing current mode feedforward ripple injection method to enhance the input power supply suppression capability of the LDO, such as large occupied area, poor practical application effect, and limited size of the PMOS power tube, a new circuit structure for enhancing the input power supply ripple suppression capability is proposed. The circuit for enhancing the input power supply ripple suppression capability of the disclosed embodiment is also a current mode feedforward ripple injection method. It can be combined with a super source follower or other source followers with enhanced driving capability to drive the power tube gate, thereby improving the applicability to large-size power tube LDOs; in addition, the improvement effect of the input power supply ripple suppression performance is directly related to the matching degree of the resistor rather than the matching degree of the MOS tube, and the practicality is improved; at the same time, the MOS tube is used as an equivalent resistor to replace the large resistor in the prior art, which plays a role in saving area. The circuit for enhancing the input power supply ripple suppression capability disclosed in the present invention is described in detail below.

[0033] Figure 3 The schematic block diagram of the circuit 100 for enhancing the ripple suppression capability of the input power supply according to the embodiment of the present disclosure is shown, wherein the input power supply is the input power supply in the low voltage drop linear regulator LDO, and the circuit 100 for enhancing the ripple suppression capability of the input power supply is also a part of the low voltage drop linear regulator LDO. Figure 3 , other modules in the LDO are also shown, including the error amplifier EA, the power tube M0, the feedback network, the compensation network, and the load network coupled to the LDO. Figure 3 As shown, the circuit 100 for enhancing the input power ripple suppression capability includes: a resistor buffer 110 , a ripple detection circuit 120 , and a super source follower 130 .

[0034] Among them, the resistor-type buffer 110 is respectively coupled to the error amplifier EA, the compensation network, the ripple detection circuit 120, and the super source follower 130. The resistor-type buffer 110 is configured to receive the error output signal VE of the error amplifier EA of the low voltage difference linear regulator, and transmit the error output signal VE with equal amplitude to the input end of the super source follower 130 through the voltage-to-current circuit and the current-to-voltage circuit. In the embodiment of the present disclosure, the resistor-type buffer 110 can transmit the received error output signal VE with equal amplitude to the output end of the resistor-type buffer 110, and change the impedance of the small signal of the input and output ends to the ground (ground end). The addition of the resistor-type buffer 110 can make the feedforward current If of the ripple detection circuit 120 flow into the output end of the resistor-type buffer 110, that is, the input end of the super source follower 130, so there is no need for the ripple detection circuit 120 to match the equivalent transconductance of the super source follower 130, so the super source follower 130 can be used. Figure 2 In the prior art, the feedforward current is directly fed into the output of the common source follower composed of M7 and M8. Figure 2 To achieve good results, M6 and M7 need to be well matched to make the transconductance of M6 and M7 equal. Figure 2 The ordinary source follower in the structure is replaced by the super source follower 130, then Figure 2 The transconductance of M6 in the circuit cannot be equal to the equivalent transconductance of the super source follower 130, and a good effect cannot be obtained. Figure 2 The circuit structure does not support the use of the super source follower 130. In addition, the resistor buffer 110 does not change the amplitude of the error output signal VE and therefore has no effect on the subsequent circuits. In practical applications, the speed of the resistor buffer 110 can be made fast enough to ensure that the amplitude and phase of VE are not changed, thereby ensuring that there is no effect on the subsequent circuits.

[0035] The ripple detection circuit 120 is coupled to the resistor buffer 110 and the super source follower 130 respectively. The ripple detection circuit 120 is configured to convert the change of the input power supply Vin into a first current through a first resistor, and obtain a feed-forward current If through a current mirror, so as to couple the feed-forward current If to the output end of the resistor buffer 110 and the input end of the super source follower 130. The feed-forward current If is a current reflecting the change of the input power supply Vin. In the embodiment of the present disclosure, the ripple detection circuit 120 converts the change of the input power supply Vin into a current through a first resistor, instead of Figure 2 The MOS tube M6 converts the change of the input power Vin into current. Figure 2 The purpose of replacing the first resistor is to change the improvement effect of the power supply ripple suppression capability determined by the matching degree of M6 and M7 in the prior art to the improvement effect of the power supply ripple suppression capability determined by the matching degree of the resistor. Figure 2 Compared with the embodiment of the present invention, although the feed-forward current If is not directly applied to the control electrode of the power tube M0, but acts on the control electrode of the power tube M0 after passing through the super source follower 130, the equivalent transconductance of the super source follower 130 in the embodiment of the present disclosure can be set large enough to make its gain 1, so it does not affect the accurate transmission of the change of the input power supply Vin.

[0036] The super source follower 130 is coupled to the resistor buffer 110, the ripple detection circuit 120, and the power tube M0 respectively. The super source follower 130 is configured to reduce the impedance of the output end of the super source follower 130 by increasing the equivalent transconductance of the first transistor and the second transistor, and couple the output end of the super source follower 130 to the control electrode of the power tube M0 in the low voltage difference linear regulator to drive the power tube M0. The super source follower 130 is used in the embodiment of the present disclosure in order to act on a larger size of the power tube M0. The super source follower 130 in the embodiment of the present disclosure is a transconductance enhanced source follower, which mainly reduces the impedance of the small signal at the output end of the super source follower 130 by increasing the transconductance of the transistor in the main circuit of the super source follower 130, so that it can drive a larger area of ​​the power tube M0. Among them, the first transistor and the second transistor are the transistors in the main circuit. In the embodiment of the present disclosure, the circuit structure of the super source follower is not limited, as long as the super source follower that meets the configuration requirements mentioned above is sufficient.

[0037] From the above description, it can be seen that in the circuit for enhancing the input power ripple suppression capability of the embodiment of the present disclosure, a resistor buffer 110 is added between the error amplifier EA of the LDO and the super source follower 130, which changes the overall architecture of the circuit. This change enables the feedforward current If output by the ripple detection circuit 120 to be coupled to the input end of the super source follower 130 instead of the output end, so there is no need for equivalent transconductance matching between the ripple detection circuit 120 and the super source follower 130, so it can be combined with the super source follower 130, so that the LDO can use a large-sized power tube M0; in addition, the ripple detection circuit 120 itself is also improved, so that the effect of improving the power supply ripple suppression capability is changed from being determined by the matching of the MOS tube to being determined by the matching of the resistor. In the integrated circuit, the matching degree of the resistor is much better than the matching degree of the MOS tube, thereby improving the effect in practical applications.

[0038] Further, such as Figure 4As shown, the resistor-type buffer 110 includes: a voltage-to-current circuit 111, a first current mirror 112, and a current-to-voltage circuit 113, wherein the voltage-to-current circuit 111 is configured to transmit the error output signal VE with equal amplitude to the first node A through the first operational amplifier A1, and convert the voltage of the first node A into a second current I2 through the second resistor R2; the first current mirror 112 is configured to copy the second current I2 and transmit it to the second node B; the current-to-voltage circuit 113 is configured to convert the copied second current I2 into a voltage through the third resistor R3 and output it from the second node B, and the second node B is the output end of the resistor-type buffer 110.

[0039] Further, such as Figure 4 As shown, the voltage-to-current circuit 111 includes: a first operational amplifier A1, a third transistor M3, and a second resistor R2, wherein the positive input terminal of the first operational amplifier A1 is coupled to the error output signal VE, the negative input terminal of the first operational amplifier A1 is coupled to the first electrode of the third transistor M3 and one end of the second resistor R2 respectively, and the output terminal of the first operational amplifier A1 is coupled to the control electrode of the third transistor M3; the second electrode of the third transistor M3 is coupled to the first current mirror 112; the other end of the second resistor R2 is coupled to the ground; the first current mirror 112 includes: a fourth transistor M4 and a fifth transistor M5, wherein The control electrode of the fourth transistor M4 is respectively coupled to the second electrode of the fourth transistor M4, the voltage-to-current circuit 111, and the control electrode of the fifth transistor M5. The first electrode of the fourth transistor M4 and the first electrode of the fifth transistor M5 are both coupled to the input power supply Vin. The second electrode of the fifth transistor M5 is coupled to the current-to-voltage circuit 113. The current-to-voltage circuit 113 includes a third resistor R3, wherein one end of the third resistor R3 is respectively coupled to the first current mirror 112, the input end of the super source follower 130, and the feed-forward current If as the output end of the resistance-type buffer 110, and the other end of the third resistor R3 is coupled to the ground end.

[0040] Further, such as Figure 5 As shown, the ripple detection circuit 120 includes: an acquisition module 121 and a conversion module 122, wherein the acquisition module 121 is configured to couple one end of the first resistor R1 to the input power supply Vin, keep the voltage at the other end of the first resistor R1 constant through the second operational amplifier A2, and convert its change through the first resistor R1 when the input power supply Vin changes; the conversion module 122 is configured to convert the first current I1 into a feedforward current If through a second current mirror 1221 and a third current mirror 1222.

[0041] Further, such as Figure 5As shown, the acquisition module 121 includes: a first resistor R1, a second operational amplifier A2, a fourth resistor R4, a MOS tube equivalent resistor 1211, a first current source Is1, a third capacitor C3, and an eighth transistor M8, wherein the other end of the first resistor R1 is respectively coupled to the negative input end of the second operational amplifier A2 and the first electrode of the eighth transistor M8; the positive input end of the second operational amplifier A2 is respectively coupled to one end of the MOS tube equivalent resistor 1211 and one end of the third capacitor C3; the other end of the MOS tube equivalent resistor 1211 is respectively coupled to one end of the fourth resistor R4 and one end of the first current source Is1; the other end of the third capacitor C3 and the other end of the first current source Is1 are both coupled to the ground end; the other end of the fourth resistor R4 is coupled to the input power supply Vin; the second electrode of the eighth transistor M8 is coupled to the conversion module 122, and the eighth transistor The second electrode of the transistor M8 outputs the first current I1; the conversion module 122 includes a second current mirror 1221 composed of a ninth transistor M9 and a tenth transistor M10, and a third current mirror 1222 composed of an eleventh transistor M11 and a twelfth transistor M12, wherein the control electrode of the ninth transistor M9 is respectively coupled to the control electrode of the tenth transistor M10 and the second electrode of the ninth transistor M9, the first electrode of the ninth transistor M9 and the first electrode of the tenth transistor M10 are both coupled to the ground terminal, the second electrode of the tenth transistor M10 is respectively coupled to the control electrode of the eleventh transistor M11, the second electrode of the eleventh transistor M11, and the control electrode of the twelfth transistor M12, the first electrode of the eleventh transistor M11 and the first electrode of the twelfth transistor M12 are both coupled to the input power supply Vin, and the second electrode of the twelfth transistor M12 outputs the feed-forward current If. Figure 5 In the embodiment, bias voltage VB is provided by R4 and Is1, and bias voltage VB is stabilized by MOS tube equivalent resistor 1211 and third capacitor C3. A2 makes the voltage at the other end of R1 (point C) not change with the change of Vin. Therefore, when Vin changes, the voltage at one end of R1 changes, but the voltage at the other end of R1 remains unchanged, so that the change of Vin is converted into the first current I1 through R1. I1 flows through M9, and the feedforward current If is obtained through two current mirrors formed by M9, M10, M11 and M12.

[0042] Figure 5 The MOS tube equivalent resistance 1211 in the figure is the equivalent resistance formed by the MOS tube. Figure 2 Compared with the large resistor RF in the chip, the chip area can be greatly reduced. Figure 6As shown, this embodiment provides an exemplary circuit diagram of a MOS tube equivalent resistor 1211, which includes: a third current source Is3, an eighteenth transistor M18, and a nineteenth transistor M19, wherein one end of the third current source Is3 is coupled to the ground end, the other end of the third current source Is3 is respectively coupled to the second electrode of the eighteenth transistor M18, the control electrode of the eighteenth transistor M18, and the control electrode of the nineteenth transistor M19, the first electrode of the eighteenth transistor M18 is coupled to the second electrode of the nineteenth transistor M19, the first electrode of the nineteenth transistor M19 serves as one end of the MOS tube equivalent resistor 1211 (i.e., the output end of the MOS tube equivalent resistor 1211), and the first electrode of the eighteenth transistor M18 serves as the other end of the MOS tube equivalent resistor 1211 (i.e., the input end of the MOS tube equivalent resistor 1211).

[0043] Further, such as Figure 7 As shown, the super source follower 130 includes: a main circuit 131 and a bias signal generating circuit 132, wherein the main circuit 131 includes at least a first transistor M1 and a second transistor M2, and is configured such that the control electrode and the first electrode of the first transistor M1 are respectively used as the input terminal and the output terminal of the super source follower 130, and the impedance of the output terminal of the super source follower 130 is reduced by the negative feedback of the second transistor M2; the bias signal generating circuit 132 is configured to provide a bias current to the main circuit 131.

[0044] Further, such as Figure 7As shown, the main circuit 131 includes: a first transistor M1, a second transistor M2, a thirteenth transistor M13, and a fourteenth transistor M14, wherein the first electrode of the first transistor M1 is also coupled to the second electrode of the thirteenth transistor M13 and the second electrode of the second transistor M2, the second electrode of the first transistor M1 is respectively coupled to the control electrode of the second transistor M2 and the second electrode of the fourteenth transistor M14, the first electrode of the second transistor M2 and the first electrode of the fourteenth transistor M14 are both coupled to the ground terminal, the first electrode of the thirteenth transistor M13 is coupled to the input power supply Vin, the control electrode of the thirteenth transistor M13 and the control electrode of the fourteenth transistor M14 are both coupled to the bias signal generating circuit 132; the bias signal generating circuit 132 includes the first Two current sources Is2 and fifteen to seventeen transistors, wherein one end of the second current source Is2 is coupled to the input power supply Vin, and the other end of the second current source Is2 is respectively coupled to the control electrode of the fifteenth transistor M15, the second electrode of the fifteenth transistor M15, the control electrode of the sixteenth transistor M16, and the control electrode of the fourteenth transistor M14 in the main circuit 131, the first electrode of the fifteenth transistor M15 and the first electrode of the sixteenth transistor M16 are both coupled to the ground terminal, the second electrode of the sixteenth transistor M16 is respectively coupled to the second electrode of the seventeenth transistor M17, the control electrode of the seventeenth transistor M17, and the control electrode of the thirteenth transistor M13 in the main circuit 131, and the first electrode of the seventeenth transistor M17 is coupled to the input power supply Vin. Figure 7 In the embodiment, Is2 provides bias current to the main circuit 131 through M13 and M14 through the replication of current mirrors M15, M16, M14, M17 and M13; M2 is coupled to the output end of the super source follower 130, and the impedance of the output end of the super source follower 130 is reduced through negative feedback, wherein M2 can be a bipolar transistor or an NMOS transistor ( Figure 7 not shown).

[0045] Combine the following Figure 3-7The principle of the circuit 100 for enhancing the input power supply ripple suppression capability in the embodiment of the present disclosure is explained: when Vin changes, the change of Vin is converted into the first current I1 through R1, and then the feedforward current If is obtained through M9, M10, M11, and M12 and injected into the B node. The voltage signal at point B acts on the power tube M0 through the super source follower 130, so that the voltage difference between the first pole (source) and the control pole (gate) of the power tube M0 does not change with the change of Vin. Among them, the improvement effect of the power supply ripple suppression capability is determined by the matching degree of R1 and R3. In order not to affect the improvement effect of the power supply ripple suppression capability, R1 and R3 need to be strictly matched, that is, R1 and R3 are composed of basic resistance units with exactly the same length and width and adjacent physical positions in series or parallel connection on the layout, and the number of basic resistance units constituting R1 and R3 is proportional. In addition, strict matching is also to reduce random deviations in the integrated circuit manufacturing process. In addition, the current mirrors M9, M10, M11, and M12 also need to be strictly matched, that is, the four crystals (MOS tubes) M9, M10, M11, and M12 are composed of MOS tube basic units with exactly the same length and width on the layout and adjacent to each other in physical positions, which are connected in series or in parallel, and the number of MOS tube basic units constituting M9, M10, M11, and M12 is proportional.

[0046] Furthermore, the feedforward current If is injected into the output terminal of the resistor buffer 110, so the improvement effect of the suppression capability of the input power supply Vin is not only related to the size of the feedforward current If (the influence of the size of the feedforward current If can be controlled by the strict matching of R1 and R3), but also directly related to the phase of the feedforward current If. Because, Figure 5 In the ripple detection circuit 120 in the embodiment, in the process of obtaining the feedforward current If through R1, M8, M9, M10, M11, and M12, the path is affected by parasitic capacitance, which may cause the phase lag of the feedforward current If relative to the input power supply Vin, thereby causing the gate voltage and source voltage transmitted to the power tube M0 to have a phase lag, that is, the change of the gate voltage of the power tube M0 cannot keep up with the change of the source voltage of the power tube M0, and the gate-source voltage difference of the power tube M0 changes. In order to solve the above-mentioned phase lag problem, the embodiment of the present disclosure also provides another circuit structure of the resistor-type buffer 110, which is similar to Figure 4 Compared with the resistor-type buffer 110 in FIG. 1 , a phase adjustment circuit 114 is added, which is configured to adjust the phase of the output end of the resistor-type buffer 110 to be consistent with the input power supply Vin according to the first capacitor C1 and the second capacitor C2. Figure 8As shown, the phase adjustment circuit 114 includes: a first capacitor C1, a second capacitor C2, a sixth transistor M6, and a seventh transistor M7, wherein one end of the first capacitor C1 is coupled to the input power supply Vin, and the other end of the first capacitor C1 is coupled to the second electrode of the sixth transistor M6; one end of the second capacitor C2 is coupled to the ground end, and the other end of the second capacitor C2 is coupled to the second electrode of the seventh transistor M7; the control electrode of the sixth transistor M6 is coupled to the first phase adjustment selection signal S1, and the first electrode of the sixth transistor M6 is respectively coupled to the control electrode of the fifth transistor M5 and the first electrode of the seventh transistor M7, and the first phase adjustment selection signal S1 is a signal for selecting the first capacitor C1 to be connected to the control electrode of the fifth transistor M5; the control electrode of the seventh transistor M7 is coupled to the second phase adjustment selection signal S2, and the second phase adjustment selection signal S2 is a signal for selecting the second capacitor C2 to be connected to the control electrode of the fifth transistor M5.

[0047] Figure 8 The principle of the phase adjustment circuit 114 is as follows: M6 and M7 are switch tubes, and S1 and S2 are used to select whether C1 or C2 is connected to the control electrode of M5. Specifically, when it is detected that the feedforward current If has a phase lag relative to the input power supply Vin, it means that the voltage at point B has a phase lag relative to the input power supply Vin. At this time, M7 needs to be turned on and C2 is connected to the control electrode of M5. In this way, when Vin changes (that is, the voltage of the first electrode of M5 changes), the control electrode voltage of M5 cannot keep up with the change of the source electrode (first electrode) voltage of M5 due to the effect of C2 (the control electrode voltage of M5 lags behind the input power supply Vin in phase), so the drain electrode (second electrode) current of M5 will produce a change in phase that is approximately the same as the input power supply Vin to compensate for the phase lag of the feedforward current If, so that the phase of the voltage at point B is closer to the phase of the input power supply Vin, thereby improving the circuit effect. However, C2 cannot be too large, because if the drain current of M5 changes too much with the input power supply Vin, it will eventually cause the gate signal of M0 to change too much, which will cause the gate-source voltage of M0 to change, producing the opposite effect. If it is detected that the feedforward current If has no phase lag relative to the input power supply Vin, that is, the drain current of M5 is not needed to compensate for the phase of the feedforward current If, then M6 is turned on to connect C1 to the control electrode of M5. At this time, when the input power supply Vin changes, the coupling effect of C1 makes the gate-source voltage of M5 more stable, and the change of the drain current of M5 is also smaller. In addition, it should be noted that the capacitance of C1 and C2 is related to the size of M4, M5, and Figure 5 The size of M9, M10, M11, and M12 is related to the size of M4, M5, M9, M10, M11, and M12. The larger the size of M4, M5, M9, M10, M11, and M12, the larger the capacitance of C1 and C2. Preferably, in practical applications, the capacitance of C1 and C2 is less than 500fF.

[0048] The embodiment of the present disclosure further provides a low voltage dropout linear regulator, the low voltage dropout linear regulator at least comprises the circuit 100 for enhancing the input power supply ripple suppression capability in the above implementation, such as Figure 3 As shown, the low voltage drop linear regulator also includes an error amplifier EA, a compensation network, a feedback network, and a power tube M0. The low voltage drop linear regulator in the embodiment of the present disclosure can greatly improve the ripple suppression effect because it suppresses the ripple of the input power supply through a circuit that enhances the ripple suppression capability of the input power supply, and can also use a larger size power tube.

[0049] In summary, the circuit for enhancing the input power supply ripple suppression capability in the embodiment of the present disclosure can be combined with a super source follower to drive the power tube gate, thereby improving the applicability to large-size power tube LDOs; it can improve the application effect of the circuit for enhancing the input power supply ripple suppression capability in practical applications; and it can also save chip area.

[0050] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is placed after a group of terms, "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0051] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present disclosure can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

[0052] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A circuit for enhancing the ripple suppression capability of an input power supply, wherein the input power supply is an input power supply in a low voltage drop linear regulator, characterized in that: The circuit includes: a resistor buffer, a ripple detection circuit, and a super source follower. Wherein, the resistor-type buffer is configured to receive the error output signal of the error amplifier of the low voltage drop linear regulator, and transmit the error output signal with equal amplitude to the input end of the super source follower through a voltage-to-current circuit and a current-to-voltage circuit; The ripple detection circuit is configured to convert the change of the input power supply into a first current through a first resistor, and obtain a feed-forward current through a current mirror to couple the feed-forward current to the output end of the resistor buffer and the input end of the super source follower, wherein the feed-forward current is a current reflecting the change of the input power supply; The super source follower is configured to reduce the impedance of the output end of the super source follower by increasing the equivalent transconductance of the first transistor and the second transistor, and couple the output end of the super source follower to the control electrode of the power tube in the low voltage difference linear regulator to drive the power tube; The resistor-type buffer includes: the voltage-to-current circuit, the first current mirror, and the current-to-voltage circuit, wherein the voltage-to-current circuit is configured to transmit the error output signal with equal amplitude to the first node through the first operational amplifier, and convert the voltage of the first node into a second current through the second resistor; the first current mirror is configured to copy the second current and transmit it to the second node; the current-to-voltage circuit is configured to convert the copied second current into a voltage through the third resistor and output it from the second node, and the second node is the output end of the resistor-type buffer.

2. The circuit for enhancing the input power ripple suppression capability according to claim 1, characterized in that: The ripple detection circuit includes: an acquisition module and a conversion module. The acquisition module is configured to couple one end of the first resistor to the input power supply, keep the voltage at the other end of the first resistor constant through the second operational amplifier, and convert the change of the input power supply into the first current through the first resistor when the input power supply changes; The conversion module is configured to convert the first current into the feedforward current through a second current mirror and a third current mirror.

3. The circuit for enhancing the input power supply ripple suppression capability according to claim 1, characterized in that: The super source follower comprises: a main circuit, a bias signal generating circuit, Wherein, the main circuit at least includes the first transistor and the second transistor, and is configured such that the control electrode and the first electrode of the first transistor are respectively used as the input end and the output end of the super source follower, and the impedance of the output end of the super source follower is reduced by the negative feedback of the second transistor; The bias signal generating circuit is configured to provide a bias current to the main circuit.

4. The circuit for enhancing the input power ripple suppression capability according to claim 1, characterized in that: The voltage-to-current circuit comprises: the first operational amplifier, the third transistor, and the second resistor, wherein the positive input terminal of the first operational amplifier is coupled to the error output signal, the negative input terminal of the first operational amplifier is respectively coupled to the first electrode of the third transistor and one end of the second resistor, the output terminal of the first operational amplifier is coupled to the control electrode of the third transistor; the second electrode of the third transistor is coupled to the first current mirror; the other end of the second resistor is coupled to the ground terminal; The first current mirror comprises: a fourth transistor and a fifth transistor, wherein a control electrode of the fourth transistor is respectively coupled to a second electrode of the fourth transistor, the voltage-to-current circuit, and a control electrode of the fifth transistor, a first electrode of the fourth transistor and a first electrode of the fifth transistor are both coupled to the input power supply, and a second electrode of the fifth transistor is coupled to the current-to-voltage circuit; The current-to-voltage circuit includes the third resistor, wherein one end of the third resistor serves as the output end of the resistor-type buffer and is respectively coupled to the first current mirror, the input end of the super source follower, and the feed-forward current, and the other end of the third resistor is coupled to the ground end.

5. The circuit for enhancing the input power ripple suppression capability according to claim 4, characterized in that: The resistor-type buffer further includes: a phase adjustment circuit configured to adjust the phase of the output end of the resistor-type buffer to be consistent with the input power supply according to the first capacitor and the second capacitor.

6. The circuit for enhancing the input power ripple suppression capability according to claim 5, characterized in that: The phase adjustment circuit includes: the first capacitor, the second capacitor, a sixth transistor, and a seventh transistor. Wherein, one end of the first capacitor is coupled to the input power supply, and the other end of the first capacitor is coupled to the second electrode of the sixth transistor; One end of the second capacitor is coupled to the ground, and the other end of the second capacitor is coupled to the second electrode of the seventh transistor; The control electrode of the sixth transistor is coupled to a first phase adjustment selection signal, the first electrode of the sixth transistor is respectively coupled to the control electrode of the fifth transistor and the first electrode of the seventh transistor, and the first phase adjustment selection signal is a signal for selecting the first capacitor to be connected to the control electrode of the fifth transistor; The control electrode of the seventh transistor is coupled to a second phase adjustment selection signal, and the second phase adjustment selection signal is a signal for selecting the second capacitor to be connected to the control electrode of the fifth transistor.

7. The circuit for enhancing the input power ripple suppression capability according to claim 2, characterized in that: The acquisition module includes: the first resistor, the second operational amplifier, the fourth resistor, the MOS tube equivalent resistor, the first current source, the third capacitor, and the eighth transistor, wherein the other end of the first resistor is respectively coupled to the negative input end of the second operational amplifier and the first electrode of the eighth transistor; the positive input end of the second operational amplifier is respectively coupled to one end of the MOS tube equivalent resistor and one end of the third capacitor; the other end of the MOS tube equivalent resistor is respectively coupled to one end of the fourth resistor and one end of the first current source; the other end of the third capacitor and the other end of the first current source are both coupled to the ground end; the other end of the fourth resistor is coupled to the input power supply; the second electrode of the eighth transistor is coupled to the conversion module, and the second electrode of the eighth transistor outputs the first current; The conversion module includes the second current mirror composed of a ninth transistor and a tenth transistor, and the third current mirror composed of an eleventh transistor and a twelfth transistor, wherein the control electrode of the ninth transistor is respectively coupled to the control electrode of the tenth transistor and the second electrode of the ninth transistor, the first electrode of the ninth transistor and the first electrode of the tenth transistor are both coupled to the ground terminal, the second electrode of the tenth transistor is respectively coupled to the control electrode of the eleventh transistor, the second electrode of the eleventh transistor, and the control electrode of the twelfth transistor, the first electrode of the eleventh transistor and the first electrode of the twelfth transistor are both coupled to the input power supply, and the second electrode of the twelfth transistor outputs the feedforward current.

8. The circuit for enhancing the input power ripple suppression capability according to claim 3, characterized in that: The main circuit comprises: the first transistor, the second transistor, the thirteenth transistor, and the fourteenth transistor, wherein the first electrode of the first transistor is also coupled to the second electrode of the thirteenth transistor and the second electrode of the second transistor, the second electrode of the first transistor is respectively coupled to the control electrode of the second transistor and the second electrode of the fourteenth transistor, the first electrode of the second transistor and the first electrode of the fourteenth transistor are both coupled to the ground terminal, the first electrode of the thirteenth transistor is coupled to the input power supply, and the control electrode of the thirteenth transistor and the control electrode of the fourteenth transistor are both coupled to the bias signal generating circuit; The bias signal generating circuit includes a second current source and fifteen to seventeen transistors, wherein one end of the second current source is coupled to the input power supply, and the other end of the second current source is respectively coupled to the control electrode of the fifteenth transistor, the second electrode of the fifteenth transistor, the control electrode of the sixteenth transistor, and the control electrode of the fourteenth transistor in the main circuit, the first electrode of the fifteenth transistor and the first electrode of the sixteenth transistor are both coupled to the ground terminal, the second electrode of the sixteenth transistor is respectively coupled to the second electrode of the seventeenth transistor, the control electrode of the seventeenth transistor, and the control electrode of the thirteenth transistor in the main circuit, and the first electrode of the seventeenth transistor is coupled to the input power supply.

9. A low voltage dropout linear regulator, characterized in that: The low voltage dropout linear regulator comprises the circuit for enhancing the input power ripple suppression capability according to any one of claims 1 to 8.

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