Receiver and communication interface

Abstract

The present invention discloses a receiver and a communication interface. The receiver is applied to the communication interface; the receiver includes a comparison unit, a first logic output unit, a second logic output unit and a failure protection unit; the comparison unit is used to output a first comparison signal and a second comparison signal according to a differential signal, the first comparison signal is valid when the differential signal is greater than a first threshold, and the second comparison signal is invalid when the differential signal is less than a second threshold; the first logic output unit is used to maintain the level state of the previous stage when the level states of the first comparison signal and the second comparison signal are different, the failure protection unit is used to output a valid failure protection signal when the first comparison signal is invalid and the second comparison signal is valid, and the second logic output unit is used to output a valid receiving signal when at least one of the logic signal and the failure protection signal output by the first logic output unit is valid. The anti-interference ability of the receiver can be improved, and the failure protection of the receiver can be realized at the same time.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of communications, and in particular to a receiver and a communication interface. Background Art

[0002] The communication interface includes a driver and at least one receiver, and the signal can be transmitted from the driver to the receiver through a differential bus. During the signal transmission process, the signal is easily subject to various external interferences or damage on the transmission path. The output state of the receiver is uncertain, and it is easy to receive data errors. To avoid this problem, it is usually necessary to make the hysteresis of the receiver's receiving threshold large enough to improve the anti-interference ability. In addition, the receiver must also have a failure protection function to characterize the abnormal open or short circuit state of the differential bus network. In the prior art, the anti-interference ability and failure protection function of the receiver have certain limitations and cannot meet the needs of the receiver. Summary of the invention

[0003] The present invention provides a receiver and a communication interface to improve the anti-interference capability and failure protection function of the receiver and enhance the performance of the receiver.

[0004] In a first aspect, an embodiment of the present invention provides a receiver, which is applied to a communication interface; the receiver includes a comparison unit, a first logic output unit, a second logic output unit and a failure protection unit;

[0005] The input end of the comparison unit is used to input a differential signal, the output end of the comparison unit is connected to the input end of the first logic output unit and the input end of the failure protection unit, the output end of the first logic output unit is connected to the first input end of the second logic output unit, the output end of the failure protection unit is connected to the second input end of the second logic output unit, and the output end of the second logic output unit serves as the output end of the receiver; the comparison unit includes a first threshold value and a second threshold value, the first threshold value is greater than 0 and less than the highest threshold value of the communication protocol, and the second threshold value is less than 0 and greater than the lowest threshold value of the communication protocol; the comparison unit is used to output a first comparison signal and a second comparison signal according to the differential signal, the first comparison signal is valid when the differential signal is greater than the first threshold value, and the second comparison signal is invalid when the differential signal is less than the second threshold value; the first logic output unit is used to maintain the level state of the previous stage when the level states of the first comparison signal and the second comparison signal are different, the failure protection unit is used to output a valid failure protection signal when the first comparison signal is invalid and the second comparison signal is valid, and the second logic output unit is used to output a valid receiving signal when at least one of the logic signal output by the first logic output unit and the failure protection signal is valid.

[0006] Optionally, the comparison unit includes a first comparator and a second comparator;

[0007] The positive end of the first comparator and the positive end of the second comparator serve as the positive input end of the comparison unit, the negative end of the first comparator and the negative end of the second comparator serve as the negative input end of the comparison unit, the output end of the first comparator is connected to the first input end of the first logic output unit and the first input end of the failure protection unit, the output end of the second comparator is connected to the second input end of the first logic output unit and the second input end of the failure protection unit, the first comparator is used to output the first comparison signal, and the second comparator is used to output the second comparison signal; wherein, the threshold of the first comparator is the first threshold of the comparison unit, and the threshold of the second comparator is the second threshold of the comparison unit.

[0008] Optionally, the absolute values ​​of the first threshold and the second threshold are equal.

[0009] Optionally, the failure protection unit includes a first inverter and an AND gate;

[0010] The input end of the first inverter is used to input the first comparison signal, the output end of the first inverter is connected to the first input end of the AND gate, the second input end of the AND gate is used to input the second comparison signal, and the output end of the AND gate is connected to the second input end of the second logic output unit.

[0011] Optionally, the failure protection unit further includes a delay module;

[0012] The output end of the AND gate is connected to the second input end of the second logic output unit through the delay module, and the delay module is used to delay the signal output by the AND gate to form the fail-safe signal.

[0013] Optionally, the first logic output unit includes a second inverter and a latch;

[0014] The input end of the second inverter is used to input the second comparison signal, the first input end of the latch is used to input the first comparison signal, the output end of the second inverter is connected to the second input end of the latch, and the output end of the latch is connected to the first input end of the second logic output unit.

[0015] Optionally, the latch includes a first NOR gate and a second NOR gate;

[0016] The first input end of the first NOR gate is used to input the first comparison signal, the second input end of the first NOR gate is connected to the output end of the second NOR gate and serves as the output end of the latch; the output end of the first NOR gate is connected to the first input end of the second NOR gate, and the second input end of the second NOR gate is connected to the output end of the second inverter.

[0017] Optionally, the second logic output unit includes an OR gate;

[0018] The first input end of the OR gate is connected to the output end of the first logic output unit, the second input end of the OR gate is connected to the output end of the failure protection unit, and the output end of the OR gate serves as the output end of the receiver.

[0019] In a second aspect, an embodiment of the present invention further provides a communication interface, comprising a driver and at least one receiver as described in the first aspect; the driver is connected to the receiver via a differential bus.

[0020] Optionally, when the communication interface includes multiple receivers, the structures of different receivers are the same.

[0021] The technical solution of the embodiment of the present invention can increase the hysteresis voltage of the receiver and improve the anti-interference ability of the receiver by setting the first threshold of the comparison unit to be greater than 0 and the second threshold to be less than 0. Moreover, when the voltage of the differential signal is less than the first threshold and greater than the second threshold, the failure protection unit can output a valid failure protection signal according to the first comparison signal and the second comparison signal, and the second logic output unit can output a high-level receiving signal according to the valid failure protection signal, that is, the receiver outputs a valid receiving signal when the voltage of the differential signal is less than the first threshold and greater than the second threshold, so that the output uncertainty state of the receiver can be converted into a high-level receiving signal output by the receiver through the failure protection unit, avoiding the output uncertainty state of the receiver. At the same time, it can avoid setting an additional resistor on the differential bus, reduce the load on the differential bus, and improve the driving ability of the driver connected to the receiver. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the structure of a communication interface provided for related technologies;

[0023] Figure 2 A schematic diagram of the structure of a receiver provided by an embodiment of the present invention;

[0024] Figure 3 A logic diagram of input signals and output signals of a receiver provided by an embodiment of the present invention;

[0025] Figure 4A schematic diagram of a threshold value of a differential signal defined by a communication protocol of an RS485 interface provided in an embodiment of the present invention;

[0026] Figure 5 A schematic diagram of the logic output level of a receiver in an RS485 interface provided by an embodiment of the present invention;

[0027] Figure 6 A schematic diagram of logic output levels of a receiver in an RS485 interface under interference provided by an embodiment of the present invention;

[0028] Figure 7 A schematic diagram of the structure of another receiver provided by an embodiment of the present invention;

[0029] Figure 8 A schematic diagram of the structure of another receiver provided by an embodiment of the present invention;

[0030] Fig. 9 A logic diagram of different signals of a receiver provided by an embodiment of the present invention;

[0031] Fig.10 A schematic diagram of the structure of another receiver provided by an embodiment of the present invention;

[0032] Fig.11 A schematic diagram of the structure of another receiver provided by an embodiment of the present invention;

[0033] Fig.12 A schematic diagram of the structure of a communication interface provided by an embodiment of the present invention;

[0034] Fig.13 A schematic diagram of the structure of another communication interface provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0036] Figure 1 A schematic diagram of a communication interface structure provided for related technologies. Figure 1As shown, the driver D1 and the receiver R1 are connected via a differential bus. A pull-up resistor Rfs1 is provided on the input path A1 of the positive differential signal of the differential bus, a pull-down resistor Rfs2 is provided on the input path B1 of the negative differential signal of the differential bus, and a voltage-dividing resistor Rt is connected between the input path A1 of the positive differential signal and the input path B1 of the negative differential signal of the differential bus. When the driver D1 is turned off, the voltage between the power supply terminal Vcc and the fixed potential terminal V1 is divided by the pull-up resistor Rfs1, the voltage-dividing resistor Rt and the pull-down resistor Rfs2, so that the voltage difference between the two ends of the voltage-dividing resistor Rt is greater than the differential bus voltage corresponding to the logic high defined by the communication protocol, so that the receiver R1 outputs a logic high signal, avoiding the phenomenon that the output state of the receiver R1 is uncertain when the driver D1 is turned off. When an abnormal short circuit occurs in the differential bus, the voltage between the input path A1 of the positive differential signal and the input path B1 of the negative differential signal of the differential bus is still equal to 0, and the receiver R1 cannot achieve failure protection at this time. Moreover, the additional pull-up resistor Rfs1 , the voltage-dividing resistor Rt, and the pull-down resistor Rfs2 increase the load of the differential bus and reduce the driving capability of the driver D1 .

[0037] In some related technologies, the threshold corresponding to the logic high of the receiver R1 can also be set to be less than 0. At this time, when the driver D1 is turned off or the differential bus is abnormally short-circuited, the voltage between the input path A1 of the positive differential signal of the differential bus and the input path B1 of the negative differential signal is equal to 0, which is greater than the threshold corresponding to the logic high of the receiver R1, so that the receiver R1 outputs a logic high signal, avoiding the output state uncertainty of the receiver R1 when the driver D1 is turned off or the differential bus is abnormally short-circuited. Since the threshold corresponding to the logic high of the receiver R1 is less than 0, the threshold corresponding to the logic high of the receiver R1 can only be limited between 0 and the voltage corresponding to the logic low defined by the communication protocol, which reduces the hysteresis voltage of the receiver R1 and reduces the anti-interference ability of the receiver R1. Exemplarily, when the communication interface is a serial communication standard (Recommended Standard 485, RS485) interface, the highest threshold defined by the communication protocol is 200mV and the lowest threshold is -200mV. At this time, the threshold corresponding to the logic high of the receiver R1 can be set to -100mV, and the threshold corresponding to the logic low can be set to -120mV. When the driver D1 is turned off or the differential bus is abnormally short-circuited, a high-level receiving signal can be output to avoid the uncertainty of the output state of the receiver R1. At this time, the hysteresis voltage of the receiver R1 is -100mV-(-120mV)=20mV, and the hysteresis voltage of the receiver R1 is relatively small, which reduces the anti-interference ability of the receiver R1.

[0038] In view of the above technical problems, an embodiment of the present invention provides a receiver, which is applied to a communication interface. In the embodiment of the present invention, a high level is effective and a low level is invalid. Figure 2 A schematic diagram of the structure of a receiver provided by an embodiment of the present invention, Figure 3 A logic diagram of input signals and output signals of a receiver provided by an embodiment of the present invention. Among them, out1 is a timing diagram of a first comparison signal, out2 is a timing diagram of a second comparison signal, ab is a timing diagram of a differential signal input to the receiver, and r is a timing diagram of a signal output by the receiver. Figure 2 and Figure 3 As shown, the receiver includes a comparison unit 10, a first logic output unit 20, a second logic output unit 30 and a failure protection unit 40; the input end of the comparison unit 10 is used to input a differential signal, the output end of the comparison unit 10 is connected to the input end of the first logic output unit 20 and the input end of the failure protection unit 40, the output end of the first logic output unit 20 is connected to the first input end of the second logic output unit 30, the output end of the failure protection unit 40 is connected to the second input end of the second logic output unit 30, and the output end of the second logic output unit 30 serves as the output end R of the receiver; the comparison unit 10 includes a first threshold value Vth+ and a second threshold value Vth-, the first threshold value Vth+ is greater than 0 and less than the highest threshold value of the communication protocol, and the second threshold value Vth- is less than 0 and greater than the communication protocol. The comparison unit 10 is used to output a first comparison signal out1 and a second comparison signal out2 according to the differential signal, the first comparison signal out1 is valid when the differential signal is greater than the first threshold value Vth+, and the second comparison signal out2 is invalid when the differential signal is less than the second threshold value Vth-; the first logic output unit 20 is used to maintain the level state of the previous stage when the level states of the first comparison signal out1 and the second comparison signal out2 are different, the failure protection unit 40 is used to output a valid failure protection signal when the first comparison signal out1 is invalid and the second comparison signal out2 is valid, and the second logic output unit 30 is used to output a valid reception signal when at least one of the logic signal and the failure protection signal output by the first logic output unit 20 is valid.

[0039] Specifically, the differential signal can be transmitted by a differential bus. Figure 2It is exemplarily shown in the figure that the comparison unit 10 includes a positive input terminal V+ and a negative input terminal V-. The positive input terminal V+ of the comparison unit 10 can be the positive input terminal of the receiver, which is connected to the positive output terminal of the driver through a data transmission signal line of the differential bus. The negative input terminal V- of the comparison unit 10 can be the negative input terminal of the receiver, which is connected to the negative output terminal of the driver through another data transmission signal line of the differential bus. When the receiver is applied to different communication interfaces, different communication interfaces have different communication protocols. Different communication protocols have different definitions of the threshold of the differential signal transmitted on the differential bus. Among them, the differential signal is the difference between the voltages on the two data transmission signal lines of the differential bus. Exemplarily, when the communication interface is an RS485 interface, Figure 4 A schematic diagram of a threshold value of a differential signal defined in a communication protocol of an RS485 interface provided in an embodiment of the present invention. Figure 5 The following is a schematic diagram of the logic output level of a receiver in an RS485 interface provided by an embodiment of the present invention. Wherein, a is the voltage timing diagram of the positive voltage signal in the differential signal, b is the voltage timing diagram of the negative voltage signal in the differential signal, ab is the timing diagram of the differential signal input to the receiver, and r is the signal timing diagram of the receiver output. Figure 4 and Figure 5 As shown, when the voltage of the differential signal of the differential bus is greater than the highest threshold 200mV defined by the communication protocol of the RS485 interface, the receiver outputs a logic high signal 1. When the voltage of the differential signal of the differential bus is less than the lowest threshold -200mV defined by the communication protocol of the RS485 interface, the receiver outputs a low signal 0. In other embodiments, the communication interface can also be an RS422 interface, a low-voltage differential signal (LVDS) interface, and a multi-point low-voltage differential signal (MLVDS) interface, etc., which are not limited here.

[0040] The comparison unit 10 has a first threshold value Vth+ and a second threshold value Vth-, the first threshold value Vth+ is the positive threshold voltage of the comparison unit 10, and the first threshold value Vth+ can be set according to the threshold voltage corresponding to the logic high defined by the communication protocol, that is, according to the highest threshold setting of the communication protocol, as the positive input threshold of the receiver. The first threshold value Vth+ is greater than 0 and less than the highest threshold of the communication protocol. The second threshold value Vth- is the negative threshold voltage of the comparison unit 10, and the second threshold value Vth- can be set according to the threshold voltage corresponding to the logic low defined by the communication protocol, that is, according to the lowest threshold setting of the communication protocol, as the negative input threshold of the receiver. The second threshold value Vth- is less than 0 and greater than the lowest threshold of the communication protocol. By setting the first threshold value Vth+ of the comparison unit 10 to be greater than 0 and less than the highest threshold of the communication protocol, and the second threshold value Vth- to be less than 0 and greater than the lowest threshold of the communication protocol, the hysteresis voltage of the receiver can be ensured to be relatively large, thereby improving the anti-interference ability of the receiver. Wherein, the hysteresis voltage is the difference between the first threshold value Vth+ and the second threshold value Vth- of the receiver. For example, the first threshold Vth+=120mV, the second threshold Vth-=-120mV, then the hysteresis voltage of the receiver is Vhys=120–(-120)=240mV. Compared with the hysteresis voltage range in the related art, it is doubled, thereby improving the anti-interference ability of the receiver. For example, when the communication interface is an RS485 interface, Figure 6 The following is a schematic diagram of the logic output level of a receiver in an RS485 interface under interference provided by an embodiment of the present invention. Wherein, ab is a timing diagram of the differential signal input to the receiver, and r is a timing diagram of the signal output by the receiver. Figure 6 As shown, under the influence of interference, the jitter amplitude of the differential signal exceeds the range of the first threshold Vth+ and the second threshold Vth- of the receiver, and the receiver will respond by outputting an erroneous received signal. Figure 6 In the interference stage t0, under the effect of interference, the voltage of the differential signal changes from less than the second threshold Vth- to greater than the first threshold Vth+, and the received signal of the receiver changes from a low level to an erroneous high level. By setting the range of the first threshold Vth+ and the second threshold Vth- to be relatively large, that is, the hysteresis voltage of the receiver is relatively large, the anti-interference ability of the receiver can be improved.

[0041] In the first stage t1, when the voltage of the differential signal is less than the second threshold value Vth-, the first comparison signal out1 and the second comparison signal out2 of the comparison unit 10 are both low level. The logic signal output by the first logic output unit 20 according to the first comparison signal out1 and the second comparison signal out2 is low level. At the same time, the failure protection signal output by the failure protection unit 40 according to the first comparison signal out1 and the second comparison signal out2 is low level. At this time, the second logic output unit 30 outputs a low level receiving signal according to the logic signal and the failure protection signal. That is, the receiver outputs an invalid receiving signal when the voltage of the differential signal is less than the second threshold value Vth-.

[0042] In the second stage t2, when the voltage of the differential signal is less than the first threshold value Vth+ and greater than the second threshold value Vth-, the first comparison signal out1 of the comparison unit 10 is low level, and the second comparison signal out2 is high level. The state of the logic signal output by the first logic output unit 20 is determined according to the state of the previous stage. The failure protection unit 40 outputs a high level failure protection signal according to the first comparison signal out1 and the second comparison signal out2, that is, the failure protection signal is valid. The second logic output unit 30 can output a high level receiving signal according to the valid failure protection signal, that is, the receiver outputs a valid receiving signal when the voltage of the differential signal is less than the first threshold value Vth+ and greater than the second threshold value Vth-, so that the output uncertainty state of the receiver can be converted into a high level receiving signal output by the receiver through the failure protection unit 40, avoiding the output uncertainty state of the receiver. At the same time, it can avoid setting an additional resistor on the differential bus, reduce the load on the differential bus, avoid the potential offset phenomenon caused by the resistor, and improve the driving ability of the driver connected to the corresponding receiver.

[0043] In the third stage t3, when the voltage of the differential signal is greater than the first threshold value Vth+, the first comparison signal out1 and the second comparison signal out2 of the comparison unit 10 are both high level. The first logic output unit 20 can output a high level logic signal according to the first comparison signal out1 and the second comparison signal out2. At this time, the second logic output unit 30 outputs a high level signal according to the logic signal, and the receiver outputs a valid reception signal when the voltage of the differential signal is greater than the first threshold value Vth+.

[0044] In addition, the first logic output unit 20 maintains the level state of the previous stage when the level states of the first comparison signal out1 and the second comparison signal out2 are different. Figure 3, in the second stage t2, when the first comparison signal out1 is at a low level, the second comparison signal out2 is at a high level, and the level state of the first logic output unit 20 in the previous stage is at a low level, the first logic output unit 20 will maintain the state of the previous stage and output a low level signal. At this time, the failure protection signal output by the failure protection unit 40 according to the first comparison signal out1 and the second comparison signal out2 is at a high level, and the rising edge of the failure protection signal jumping from a low level to a high level lags behind the rising edge of the second comparison signal out2. At this time, the second logic output unit 40 can output a high level receiving signal according to the high level failure protection signal. In the fourth stage t4, the first logic output unit 20 will maintain the state of the previous stage and output a high level signal, and at the same time, the failure protection unit 40 can output a high level failure protection signal according to the first comparison signal out1 and the second comparison signal out2, and at this time, the second logic output unit 40 can output a high level receiving signal according to the high level logic signal and the high level failure protection signal.

[0045] The technical solution of this embodiment can increase the hysteresis voltage of the receiver and improve the anti-interference ability of the receiver by setting the first threshold of the comparison unit to be greater than 0 and the second threshold to be less than 0. Moreover, when the voltage of the differential signal is less than the first threshold and greater than the second threshold, the failure protection unit can output a valid failure protection signal according to the first comparison signal and the second comparison signal, and the second logic output unit can output a high-level receiving signal according to the valid failure protection signal, that is, the receiver outputs a valid receiving signal when the voltage of the differential signal is less than the first threshold and greater than the second threshold, so that the output uncertainty state of the receiver can be converted into a high-level receiving signal output by the receiver through the failure protection unit, avoiding the output uncertainty state of the receiver. At the same time, it can avoid setting additional resistors on the differential bus, reduce the load on the differential bus, and improve the driving ability of the driver connected to the receiver.

[0046] Figure 7 A schematic diagram of the structure of another receiver provided by an embodiment of the present invention, such as Figure 7As shown, the comparison unit 10 includes a first comparator Comp1 and a second comparator Comp2; the positive terminal 1+ of the first comparator Comp1 and the positive terminal 2+ of the second comparator Comp2 serve as the positive input terminal V+ of the comparison unit 10, the negative terminal 1- of the first comparator Comp1 and the negative terminal 2- of the second comparator Comp2 serve as the negative input terminal V- of the comparison unit 10, the output terminal OUT1 of the first comparator Comp1 is connected to the first input terminal of the first logic output unit 20 and the first input terminal of the failure protection unit 40, the output terminal OUT2 of the second comparator Comp2 is connected to the second input terminal of the first logic output unit 20 and the second input terminal of the failure protection unit 40, the first comparator Comp1 is used to output a first comparison signal out1, and the second comparator Comp2 is used to output a second comparison signal out2; wherein, the threshold of the first comparator Comp1 is the first threshold value Vth+ of the comparison unit 10, and the threshold of the second comparator Comp2 is the second threshold value Vth- of the comparison unit 10.

[0047] Specifically, the first comparator Comp1 and the second comparator Comp2 both have a comparison function. When the differential signal is greater than the threshold of the first comparator Comp1, the differential signal is also greater than the threshold of the second comparator Comp2. The first comparator Comp1 outputs a high-level signal, and the second comparator Comp2 outputs a high-level signal. That is, the first comparison signal out1 and the second comparison signal out2 are both high-level. At this time, the first logic output unit 20 outputs a high-level logic signal according to the first comparison signal out1 and the second comparison signal out2, and the second logic output unit outputs a high-level receiving signal according to the high-level logic signal. When the differential signal is less than the threshold of the first comparator Comp1 and greater than the threshold of the second comparator Comp2, the first comparator Comp1 outputs a low-level signal, and the second comparator Comp2 outputs a high-level signal. That is, the first comparison signal out1 is low-level, and the second comparison signal out2 is high-level. At this time, the first logic output unit 20 maintains the level state of the previous stage. The failure protection unit 40 can output a high-level failure protection signal according to the first comparison signal out1 and the second comparison signal out2, and the second logic output unit outputs a high-level receiving signal according to the high-level failure protection signal. When the differential signal is less than the threshold of the second comparator Comp2, the first comparator Comp1 outputs a low level signal, and the second comparator Comp2 outputs a low level signal. That is, the first comparison signal out1 and the second comparison signal out2 are both low level. At this time, the first logic output unit 20 outputs a low level logic signal according to the first comparison signal out1 and the second comparison signal out2, and the failure protection signal output by the failure protection unit 40 according to the first comparison signal out1 and the second comparison signal out2 is low level. The second logic output unit outputs a low level receiving signal according to the low level logic signal and the low level failure protection signal.

[0048] In some embodiments, the absolute values ​​of the first threshold Vth+ and the second threshold Vth- are equal.

[0049] Specifically, when the absolute values ​​of the first threshold value Vth+ and the second threshold value Vth- are equal, the values ​​of the first threshold value Vth+ and the second threshold value Vth- are symmetrical about 0. During the operation of the receiver, a first difference between a positive voltage signal in a differential signal provided by the differential bus and the first threshold value Vth+ and a second difference between a negative voltage signal in a differential signal provided by the differential bus and the second threshold value Vth- are symmetrical about 0, so that the delay of the receiving signal output by the receiver at the rising edge and the delay at the falling edge can be symmetrical about 0, thereby improving the consistency of the delay of the receiving signal when flipping, thereby improving the signal transmission rate of the receiver.

[0050] Figure 8 A schematic diagram of the structure of another receiver provided by an embodiment of the present invention, such as Figure 8 As shown, the failure protection unit 40 includes a first inverter INV1 and an AND gate AND; the input end of the first inverter INV1 is used to input the first comparison signal out1, the output end of the first inverter INV1 is connected to the first input end of the AND gate AND, the second input end of the AND gate AND is used to input the second comparison signal out2, and the output end of the AND gate AND is connected to the second input end of the second logic output unit 30.

[0051] Specifically, when the first comparison signal out1 and the second comparison signal out2 are both at low levels, the first inverter INV1 inputs a low level signal and outputs a high level signal. At the same time, the second comparison signal out2 is at a low level, and the AND gate AND outputs a low level signal to the second logic output unit 30. The receiving signal output by the second logic output unit 30 is determined according to the logic signal output by the first logic output unit 20. At this time, the failure protection unit 40 does not affect the receiving signal and does not perform failure protection on the receiver.

[0052] When the first comparison signal out1 is at a low level and the second comparison signal out2 is at a high level, the first inverter INV1 inputs a low level signal and outputs a high level signal. At the same time, the second comparison signal out2 is at a high level, and the AND gate AND outputs a high level signal to the second logic output unit 30, and the second logic output unit 30 outputs a high level receiving signal according to the high level signal. Thus, the output uncertainty state of the receiver can be converted into a high level receiving signal through the fail-safe unit 40, thereby avoiding the output uncertainty state of the receiver.

[0053] When the first comparison signal out1 and the second comparison signal out2 are both at high levels, the first inverter INV1 inputs a high-level signal and outputs a low-level signal. At the same time, the second comparison signal out2 is at a high level, and the AND gate AND outputs a low-level signal to the second logic output unit 30. The receiving signal output by the second logic output unit 30 is determined according to the logic signal output by the first logic output unit 20. At this time, the failure protection unit 40 does not affect the receiving signal and does not perform failure protection on the receiver.

[0054] It can be seen that the fail-safe unit 40 can perform fail-safe operation on the receiver when the first comparison signal out1 is at a low level and the second comparison signal out2 is at a high level, while avoiding affecting the normal operation of the receiver.

[0055] Continue to refer Figure 8 The failure protection unit 40 also includes a delay module Timer; the output end of the AND gate AND is connected to the second input end of the second logic output unit 30 through the delay module Timer, and the delay module Timer is used to delay the signal output by the AND gate AND to form a failure protection signal.

[0056] Specifically, the delay module Timer has a delay function. When the first comparison signal out1 is at a low level and the second comparison signal out2 is at a high level, the high level signal output by the AND gate AND can start the delay module Timer to start timing, until the delay module Timer times to a preset time, the signal output by the delay module Timer jumps from a low level to a high level, so that the failure protection unit 40 can output a high-level failure protection signal to perform failure protection on the receiver. By outputting a high-level failure protection signal after the delay module Timer maintains the state of the first comparison signal out1 being at a low level and the second comparison signal out2 being at a high level for a preset time, the influence of interference on the receiver can be reduced and the stability of the receiver can be improved.

[0057] Fig. 9 A logic diagram of different signals of a receiver provided by an embodiment of the present invention. Wherein, ab is a timing diagram of a differential signal input to the receiver, out1 is a timing diagram of a first comparison signal, out2 is a timing diagram of a second comparison signal, en_timer is an input signal of a delay module Timer, timeout is an output signal of the delay module Timer, r is a timing diagram of a signal output by the receiver, and t' is a preset time. Fig. 9As shown, in the second stage t2, the voltage of the differential signal is less than the first threshold value Vth+ and greater than the second threshold value Vth-, the first comparison signal out1 is low level, the second comparison signal out2 is high level, and the AND gate AND outputs a high level signal, that is, the input signal en_timer of the delay module Timer is high level. The delay module Timer starts timing, and when the delay module Timer times to the preset time t', the output signal timeout of the delay module Timer jumps from low level to high level, and is output to the second input end of the second logic output unit 30 as a failure protection signal. At this time, the second logic output unit 30 outputs a high level receiving signal according to the high level failure protection signal, avoiding the uncertain output state of the receiver. In the fourth stage t4, the voltage of the differential signal is less than the first threshold value Vth+ and greater than the second threshold value Vth-, the first comparison signal out1 is low level, the second comparison signal out2 is high level, and the input signal en_timer of the delay module Timer is high level. The delay module Timer starts timing, and the time of the fourth stage t4 is less than the preset time t'. That is, when the delay module Timer timing is less than the preset time t', the second comparison signal out2 jumps from a high level to a low level to proceed to the next stage, the input signal en_timer of the delay module Timer jumps to a low level, and the delay module Timer stops timing. At this time, the output signal timeout of the delay module Timer is a low level. At the same time, the first logic output unit 20 maintains the state of the previous stage, and the output logic signal is a high level. The second logic output unit 30 outputs a high-level receiving signal according to the high-level logic signal. In the fifth stage t5, the first comparison signal out1 is a low level, the second comparison signal out2 is a high level, and the input signal en_timer of the delay module Timer is a high level. The delay module Timer starts timing. When the delay module Timer timing is less than the preset time t', the first comparison signal out1 jumps to a high level, the input signal en_timer of the delay module Timer jumps to a low level, and the delay module Timer stops timing. At this time, the output signal timeout of the delay module Timer is a low level. At the same time, the first logic output unit 20 outputs a high-level logic signal according to the first comparison signal out1 and the second comparison signal out2. The second logic output unit 30 outputs a high-level receiving signal according to the high-level logic signal.

[0058] Fig.10 A schematic diagram of the structure of another receiver provided by an embodiment of the present invention, such as Fig.10As shown, the first logic output unit 20 includes a second inverter INV2 and a latch S1; the input end of the second inverter INV2 is used to input the second comparison signal out2, the first input end of the latch S1 is used to input the first comparison signal out1, the output end of the second inverter INV2 is connected to the second input end of the latch S1, and the output end of the latch S1 is connected to the first input end of the second logic output unit 30.

[0059] Specifically, the latch S1 can output the first comparison signal out1 when the level states of the first comparison signal out1 inputted at the first input terminal and the second comparison signal out2 inputted at the second input terminal are the same. And the first comparison signal out1 is latched when the level states of the first comparison signal out1 and the second comparison signal out2 are different. The signal outputted by the latch S1 is used as the logic signal outputted by the first logic output unit 20. When the first comparison signal out1 and the second comparison signal out2 are both low level, the latch S1 outputs the low level of the first comparison signal out1. When the first comparison signal out1 is low level and the second comparison signal out2 is high level, the latch S1 outputs the level state of the previous stage, which can be high level or low level. When the first comparison signal out1 and the second comparison signal out2 are both high level, the latch S1 outputs the high level signal of the first comparison signal out1.

[0060] In some embodiments, Fig.11 A schematic diagram of the structure of another receiver provided by an embodiment of the present invention, such as Fig.11 As shown, the latch S1 includes a first NOR gate NOR1 and a second NOR gate NOR2; the first input end of the first NOR gate NOR1 is used to input the first comparison signal out1, the second input end of the first NOR gate NOR1 is connected to the output end of the second NOR gate NOR2, and serves as the output end of the latch S1; the output end of the first NOR gate NOR1 is connected to the first input end of the second NOR gate NOR2, and the second input end of the second NOR gate NOR2 is connected to the output end of the second inverter INV2.

[0061] Specifically, when the first comparison signal out1 and the second comparison signal out2 are both at low levels, the second inverter INV2 outputs a high level signal. The second NOR gate NOR2 outputs a low level signal according to the high level signal output by the second inverter INV2, that is, the latch S1 outputs a low level signal. When the first comparison signal out1 is at a low level and the second comparison signal out2 is at a high level, the second inverter INV2 outputs a low level signal. The first NOR gate NOR1 outputs a high level signal according to the low level signal output by the second NOR gate NOR2 in the previous stage, and the second NOR gate NOR2 outputs a low level signal according to the high level signal output by the first NOR gate NOR1, maintaining the low level signal of the previous stage, that is, the latch S1 maintains the output of the low level signal. In addition, when the second NOR gate NOR2 outputs a high level signal in the previous stage, the first NOR gate NOR1 outputs a low level signal according to the high level signal output by the second NOR gate NOR2 in the previous stage, and the second NOR gate NOR2 outputs a high level signal according to the low level signal output by the first NOR gate NOR1 and the low level signal output by the second inverter INV2, maintaining the high level signal in the previous stage, that is, the latch S1 maintains the output of the high level signal. When the first comparison signal out1 and the second comparison signal out2 are both high levels, the first NOR gate NOR1 outputs a low level signal according to the first comparison signal out1, and the second inverter INV2 outputs a low level signal. The second NOR gate NOR2 outputs a high level signal according to the low level signal output by the first NOR gate NOR1 and the low level signal output by the second inverter INV2, that is, the latch S1 outputs a high level signal.

[0062] Continue to refer Fig.11 The second logic output unit 30 includes an OR gate OR; a first input end of the OR gate OR is connected to the output end of the first logic output unit 20, a second input end of the OR gate OR is connected to the output end of the failure protection unit 40, and an output end of the OR gate OR serves as an output end R of the receiver.

[0063] Specifically, when at least one of the logic signal input to the first input terminal of the OR gate OR and the fail-safe signal input to the second input terminal is a high-level signal, the OR gate OR can output a high-level signal, that is, the receiver outputs a high-level receiving signal. When the level state of the logic signal is uncertain, the fail-safe signal can be set to a high-level signal, so that the OR gate OR outputs a high-level signal according to the fail-safe signal, thereby achieving failure protection of the receiver.

[0064] The embodiment of the present invention also provides a communication interface. Fig.12 A schematic diagram of the structure of a communication interface provided by an embodiment of the present invention. Fig.12As shown, the communication interface includes a driver Driver and a receiver Receiver provided by any embodiment of the present invention; the driver Driver is connected to the receiver Receiver via a differential bus DTL.

[0065] Specifically, Fig.12 The communication interface includes a receiver Receiver as exemplified in the figure. The positive output terminal OUT+ of the driver Driver is connected to the positive input terminal IN+ of the receiver Receiver through a transmission line of the differential bus DTL, and the negative output terminal OUT- of the driver Driver is connected to the negative input terminal IN- of the receiver Receiver through another transmission line of the differential bus DTL. The signal provided by the driver Driver is output to the receiver Receiver through the differential bus DTL to realize the communication of the communication interface. Since the receiver Receiver is the receiver provided by any embodiment of the present invention, it has the same beneficial effects as the receiver provided by any embodiment of the present invention, which will not be repeated here.

[0066] Fig.13 A schematic diagram of another communication interface provided by an embodiment of the present invention. Fig.13 As shown, when the communication interface includes multiple receivers, the structures of different receivers are the same.

[0067] Specifically, Fig.13 The communication interface shown in the example includes three receivers. The different receivers Receivers can be receivers provided by any embodiment of the present invention, so that each receiver Receiver can achieve failure protection on the basis of improving anti-interference capability.

[0068] Continue to refer Fig.12 and Fig.13 A terminal resistor Rc can be connected between the positive input terminal IN+ and the negative input terminal IN- of the receiver. The terminal resistor Rc can perform impedance matching with the driver Driver, reduce the reflection of the differential signal, and improve the transmission quality of the signal on the differential bus DTL.

[0069] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A receiver, characterized in that: The receiver is applied to a communication interface; the receiver comprises a comparison unit, a first logic output unit, a second logic output unit and a failure protection unit; The input end of the comparison unit is used to input a differential signal, the output end of the comparison unit is connected to the input end of the first logic output unit and the input end of the failure protection unit, the output end of the first logic output unit is connected to the first input end of the second logic output unit, the output end of the failure protection unit is connected to the second input end of the second logic output unit, and the output end of the second logic output unit serves as the output end of the receiver; the comparison unit includes a first threshold value and a second threshold value, the first threshold value is greater than 0 and less than the highest threshold value of the communication protocol, and the second threshold value is less than 0 and greater than the lowest threshold value of the communication protocol; The comparison unit is used to output a first comparison signal and a second comparison signal according to the differential signal, the first comparison signal is valid when the differential signal is greater than the first threshold, and the second comparison signal is invalid when the differential signal is less than the second threshold; the first logic output unit is used to maintain the level state of the previous stage when the level states of the first comparison signal and the second comparison signal are different, the failure protection unit is used to output a valid failure protection signal when the first comparison signal is invalid and the second comparison signal is valid, and the second logic output unit is used to output a valid reception signal when at least one of the logic signal output by the first logic output unit and the failure protection signal is valid; wherein, the first comparison signal, the second comparison signal, the failure protection signal and the reception signal are at a high level when they are valid, and at a low level when they are invalid; The fail-safe unit comprises a first inverter and an AND gate; The input end of the first inverter is used to input the first comparison signal, the output end of the first inverter is connected to the first input end of the AND gate, the second input end of the AND gate is used to input the second comparison signal, and the output end of the AND gate is connected to the second input end of the second logic output unit; The failure protection unit also includes a delay module; The output end of the AND gate is connected to the second input end of the second logic output unit through the delay module, and the delay module is used to delay the signal output by the AND gate to form the fail-safe signal; The first logic output unit includes a second inverter and a latch; The input end of the second inverter is used to input the second comparison signal, the first input end of the latch is used to input the first comparison signal, the output end of the second inverter is connected to the second input end of the latch, and the output end of the latch is connected to the first input end of the second logic output unit; The second logic output unit comprises an OR gate; The first input end of the OR gate is connected to the output end of the first logic output unit, the second input end of the OR gate is connected to the output end of the failure protection unit, and the output end of the OR gate serves as the output end of the receiver.

2. The receiver according to claim 1, characterized in that The comparison unit includes a first comparator and a second comparator; The positive end of the first comparator and the positive end of the second comparator serve as the positive input end of the comparison unit, the negative end of the first comparator and the negative end of the second comparator serve as the negative input end of the comparison unit, the output end of the first comparator is connected to the first input end of the first logic output unit and the first input end of the failure protection unit, the output end of the second comparator is connected to the second input end of the first logic output unit and the second input end of the failure protection unit, the first comparator is used to output the first comparison signal, and the second comparator is used to output the second comparison signal; wherein, the threshold of the first comparator is the first threshold of the comparison unit, and the threshold of the second comparator is the second threshold of the comparison unit.

3. The receiver according to claim 2, characterized in that The absolute values ​​of the first threshold and the second threshold are equal.

4. The receiver according to claim 1, characterized in that The latch comprises a first NOR gate and a second NOR gate; The first input end of the first NOR gate is used to input the first comparison signal, the second input end of the first NOR gate is connected to the output end of the second NOR gate and serves as the output end of the latch; the output end of the first NOR gate is connected to the first input end of the second NOR gate, and the second input end of the second NOR gate is connected to the output end of the second inverter.

5. A communication interface, characterized in that: It comprises a driver and at least one receiver according to any one of claims 1 to 4; the driver is connected to the receiver via a differential bus.

6. The communication interface according to claim 5, characterized in that: When the communication interface includes a plurality of the receivers, the structures of different receivers are the same.

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