Data transmission method, device, storage medium and computer equipment

Abstract

The embodiments of the present application provide a data transmission method, apparatus, storage medium and computer equipment, which obtain a transmission instruction for a first processor that is not configured on the same computing board to transmit processed data to a second processor; determine a first target computing board networking chip from a computing board networking chip that has a first communication link established with the first processor; determine a target switching board networking chip from a switching board networking chip that has a second communication link established with the first target computing board networking chip; determine a second target computing board networking chip that has a second communication link established with the target switching board networking chip and a first communication link established with the second processor; establish a data transmission path based on the first target computing board networking chip, any target switching board networking chip and the second target computing board networking chip, and transmit the processed data through the data transmission path, establish a flexible data transmission path through different networking chips, and improve data transmission efficiency.

Description

Technical Field

[0001] The present application relates to the field of data transmission, and in particular to a data transmission method, device, storage medium and computer equipment. Background Art

[0002] With the rapid progress and widespread application of artificial intelligence (AI) technology, large AI models have emerged. AI large models often need to be trained in large-scale parallel on large graphics processing unit (GPU) clusters. However, when many GPUs work together to process tasks in parallel, GPUs need to closely exchange a large amount of intermediate data to ensure the accuracy of the calculation results.

[0003] In the related technology, data is transmitted between GPUs through collective communication hardware (RDMA Over HCCS, ROH) with remote direct memory access (RDMA).

[0004] However, when there is data that has not been transmitted between GPUs and new processed data needs to be transmitted, it is necessary to wait until the current data transmission is completed before the new processed data can be transmitted. This results in slow data transmission efficiency in scenarios where the data transmission pressure is high. Therefore, it is urgent to provide a data transmission method to solve the above technical problems. Summary of the invention

[0005] The main purpose of the present application is to provide a data transmission method, device, storage medium and computer equipment, which can flexibly select a data transmission path, avoid data blocking and improve data transmission efficiency.

[0006] In a first aspect, an embodiment of the present application provides a data transmission method, which is applied to a computer device, wherein the computer device includes at least one computing framework, the computing framework includes at least two computing boards and at least one switching board orthogonally connected to each of the computing boards, wherein each computing board is configured with at least two computing board networking chips, and at least two processors that establish a first communication link with each computing board networking chip, each switching board is configured with at least two switching board networking chips, and each computing board networking chip establishes a second communication link with each switching board networking chip, including:

[0007] Obtaining a transmission instruction for transmitting processing data from the first processor to the second processor;

[0008] When the first processor and the second processor are not configured on the same computing board, determining a first target computing board networking chip from computing board networking chips that have established a first communication link with the first processor;

[0009] Determine a target switch board networking chip from the switch board networking chips that have established a second communication link with the first target computing board networking chip;

[0010] Determine a second target computing board networking chip from computing board networking chips that have established a second communication link with the target switching board networking chip and have established a first communication link with the second processor;

[0011] A data transmission path is established based on the first target computing board networking chip, any target switching board networking chip and the second target computing board networking chip, and the processed data is transmitted from the first processor to the second processor through the data transmission path.

[0012] In a second aspect, an embodiment of the present application provides a data transmission device, which is applied to a computer device, wherein the computer device includes at least one computing framework, the computing framework includes at least two computing boards and at least one switching board orthogonally connected to each computing board, wherein each computing board is configured with at least two computing board networking chips, and at least two processors that establish a first communication link with each computing board networking chip, each of the switching boards is configured with at least two switching board networking chips, and each of the computing board networking chips establishes a second communication link with each of the switching board networking chips, including:

[0013] An acquisition unit, used to acquire a transmission instruction from the first processor to transmit processing data to the second processor;

[0014] A first determining unit is used to determine a first target computing board networking chip from computing board networking chips that have established a first communication link with the first processor when the first processor and the second processor are not configured on the same computing board;

[0015] A second determining unit is used to determine a target switching board networking chip from the switching board networking chips that have established a second communication link with the first target computing board networking chip;

[0016] A third determining unit is used to determine a second target computing board networking chip from the computing board networking chips that have established a second communication link with the target switching board networking chip and have established a first communication link with the second processor;

[0017] An establishing unit is used to establish a data transmission path based on the first target computing board networking chip, any of the target switching board networking chips and the second target computing board networking chip, and transmit the processed data from the first processor to the second processor through the data transmission path.

[0018] In a third aspect, an embodiment of the present application provides a storage medium, wherein the computer-readable storage medium stores a plurality of instructions, which are suitable for loading by a processor to execute any of the above data transmission methods.

[0019] In a fourth aspect, an embodiment of the present application provides a heating device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above data transmission methods when executing the computer program.

[0020] In an embodiment of the present application, when a first processor and a second processor perform data transmission across computing boards, a data transmission path is established based on determining a first target computing board networking chip from among the computing board networking chips that have established a first communication link with the first processor, a target switching board networking chip determined from among the switching board networking chips that have established a second communication link with the first target computing board networking chip, and a second target computing board networking chip determined from among the computing board networking chips that have established a second communication link with the target switching board networking chip and have established a first communication link with the second processor, so as to transmit processed data from the first processor to the second processor through the data transmission path. Compared with the related art in which each data transmission needs to wait for the completion of the previous data transmission before transmission can be performed, the embodiment of the present application can establish a flexible data transmission path through different networking chip combinations each time data transmission is performed, thereby avoiding data blocking and improving data transmission efficiency.

[0021] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by practicing the present disclosure. The purpose and other advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 A schematic diagram of the composition structure of a computer device provided in an embodiment of the present application.

[0024] Figure 2 A schematic diagram of the architecture of a computer device provided in an embodiment of the present application.

[0025] Figure 3 A schematic diagram of the orthogonal connection between a computing board and a switching board provided in an embodiment of the present application.

[0026] Figure 4 A flowchart of a data transmission method provided in an embodiment of the present application.

[0027] Figure 5 Another flowchart of the data transmission method provided in an embodiment of the present application.

[0028] Figure 6 Another flowchart of the data transmission method provided in an embodiment of the present application.

[0029] Figure 7 Another flowchart of the data transmission method provided in an embodiment of the present application.

[0030] Figure 8 Another schematic diagram of the architecture of a computer device provided in an embodiment of the present application.

[0031] Fig. 9 A schematic diagram of the structure of a data transmission device provided in an embodiment of the present application.

[0032] Fig.10 A schematic diagram of the structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0034] It should be noted that in some processes described in the specification, claims and the above-mentioned drawings, multiple steps appearing in a specific order are included, but it should be clearly understood that these steps may not be executed in the order in which they appear in this document or may be executed in parallel. The step numbers are only used to distinguish different steps, and the numbers themselves do not represent any execution order. In addition, descriptions such as "first", "second" or "target" in this document are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0035] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0036] Artificial Intelligence (AI) is an important part of the intelligent discipline, attempting to understand the essence of intelligence and produce a new intelligent machine that can respond in a similar way to human intelligence. Artificial Intelligence is a very broad science, including robotics, speech recognition, image recognition, natural language processing, expert systems, machine learning, computer vision, etc.

[0037] Central Processing Unit (CPU), CPU is the computing and control core of the computer system and the final execution unit for information processing and program running.

[0038] Graphics Processing Unit (GPU), also known as display core, visual processor, display chip, is a microprocessor that specializes in performing image and graphics related calculations on personal computers, workstations, game consoles and some mobile devices (such as tablets, smart phones, etc.).

[0039] Neural network processing unit (NPU) is a processor specially used for network application data packets, and is good at processing massive multimedia data such as videos and images. NPU is a hardware accelerator specially designed for AI and machine learning tasks. Compared with traditional CPUs and GPUs, NPU is optimized for the complex calculations required by deep learning algorithms, which can make AI tasks such as natural language processing and image analysis run more efficiently.

[0040] Remote Direct Memory Access (RDMA) is a computer network technology that allows network devices (such as network cards, storage devices, etc.) to directly access host memory without CPU intervention. This technology can improve data transmission efficiency and reduce latency, and is suitable for high-performance computing, large-scale data centers and other demanding network environments.

[0041] Huawei Collective Communication Server (HCCS) is a high-performance computing solution designed to provide efficient data communication and collective operation support. HCCS is mainly used to build large-scale supercomputer systems to support collective communication operations in parallel computing tasks, such as broadcasting and reduction. This solution has the characteristics of high reliability, high performance and high efficiency, and can meet the needs of large-scale data processing, scientific computing and other high-performance computing fields. With HCCS, users can achieve efficient data transmission and communication, and improve overall computing performance and efficiency.

[0042] RDMA Over HCCS (ROH) is a network adapter or network card that supports RDMA technology. RDMA is a communication technology used in data centers and high-performance computing. It allows servers to directly access the memory of other servers without going through the CPU, thereby achieving efficient data transmission and communication.

[0043] Goal: With the rapid advancement and widespread application of AI technology, most AI models are based on pre-trained large models. These large models use deep learning technology to integrate the distribution and characteristics of data into a neural network with a huge number of parameters based on a large amount of data, and build pre-trained large models with ultra-large-scale parameters and ultra-high precision. AI models often have a huge number of parameters, which have now grown to trillions. Therefore, training AI models requires huge computing power support and requires large-scale parallel training on large GPU (Graphics Processing Unit) clusters. However, when many GPUs work together to process tasks in parallel, a large amount of intermediate data needs to be exchanged closely between GPUs to ensure the accuracy of the calculation results, which poses a huge challenge to the network performance (including bandwidth and latency) between GPUs.

[0044] However, traditional AI models are built based on the traditional fat-tree structure networking in computer devices, which is a single-plane networking. Due to the low bandwidth of single-plane networking, the transmission efficiency of data between processors (such as data transmission between CPU and GPU, data transmission between CPU and CPU, data transmission between GPU and GPU, data transmission between CPU and NPU, and data transmission between NPU and NPU) is low and cannot meet the needs of large model training.

[0045] In order to solve the above problems, the embodiment of the present application proposes to establish a first communication link between each computer networking chip and each processor inside each computing board, and configure at least two switching board networking chips on each switching board to establish a second communication link between each switching board networking chip and each computer networking chip inside each computing board, so that when data is transmitted between processors, a specific data transmission path is established through different networking chips to improve data transmission efficiency. Please continue to refer to the following specific embodiments for details.

[0046] See also Figure 1 , Figure 1 It is a schematic diagram of the composition structure of the computer device provided in the embodiment of the present application.

[0047] Among them, the intelligent computing system architecture is mainly composed of three parts of hardware communication connection, namely, the computing cabinet 100, the network cabinet 200 and the storage cabinet 300, among which the computing cabinet 100 and the network cabinet 200 are communication connected, the network cabinet 200 and the storage cabinet 300 are communication connected, and the computing cabinet 100 and the storage cabinet 300 are communication connected through the network cabinet 200.

[0048] The computing cabinet 100 includes at least one computing frame 110, and the computing frame 110 includes multiple computing boards 101, and the computing boards 101 include multiple computing board networking chips, multiple neural network processors and multiple central processing units. The multiple neural network processors and multiple central processing units in each computing board 101 are connected to each other through multiple computing board networking chips to form a first computing network layer. The multiple computing board networking chips are connected to each other through multiple switch board networking chips to form a second computing network layer.

[0049] The storage cabinet 300 and the network cabinet 200, the storage cabinet 300 is used to provide the storage space required in the artificial intelligence model training process, and the network cabinet 200 is used to realize the data interaction between the computing cabinet 100 and the storage cabinet 300.

[0050] The first computing network layer and the second computing network layer constitute a computing network, which is used for data transmission during the training of the artificial intelligence model. The computing network can be specifically formed by a fat tree network topology structure, wherein the first computing network layer and the second computing network layer are specifically different network layers in the fat tree network topology structure.

[0051] In this way, when processors in the same computing board perform data transmission, data transmission can be achieved through the first computing network layer; when processors in different computing boards perform data transmission, data transmission can be achieved through the first computing network layer combined with the second computing network layer.

[0052] It should be noted that Figure 1The scenario diagram of the data transmission system shown is merely an example. The data transmission system and scenario described in the embodiment of the present application are intended to more clearly illustrate the technical solution of the embodiment of the present application, and do not constitute a limitation on the technical solution provided in the embodiment of the present application. A person of ordinary skill in the art can appreciate that with the evolution of data transmission and the emergence of new business scenarios, the technical solution provided in the embodiment of the present application is equally applicable to similar technical problems.

[0053] For details, please refer to Figure 2 , Figure 2 The computer device provided in the embodiment of the present application is a schematic diagram of the architecture. The computer device includes at least one computing framework, and the computing framework includes at least two computing boards (e.g. Figure 2 computing boards 1 to N in the figure), and at least one switching board (e.g. Figure 2 The switch board 1 to the switch board P in the computing board are configured with at least two computing board networking chips (for example Figure 2 The computing board networking chip 1 to the computing board networking chip K in the computing board networking chip, and establish a first communication link with each computing board networking chip (for example Figure 2 At least two processors (eg, Figure 2 Each switch board is configured with at least two switch board networking chips (for example, Figure 2 The switch board networking chip 1 to the switch board networking chip M in the computing board networking chip establish a second communication link with each of the switch board networking chips (for example Figure 2 The communication link between the computing board networking chip 1 of the computing board 1 and the switching board networking chip 1 of the switching board 1).

[0054] Among them, the computing board networking chip and the switch board networking chip are HCCS networking chips, the computing board networking chip is HCCS-L1, and the switch board networking chip is HCCS-L2. The HCCS-L1 on the computing board and the processor form a super-node L1 layer network, which is used to build a super-node architecture and realize a non-blocking super-node network plane for multiple processors in a computing framework. HCCS-L2 is responsible for further connecting the L1 networks of multiple processors in the computing frame into a super-node network to achieve non-convergence communication capabilities.

[0055] For details, please refer to Figure 3 , Figure 3A schematic diagram of orthogonal connection between a computing board and a switching board provided in an embodiment of the present application. In which, each computing board is arranged in sequence in the vertical direction, and each switching board is arranged in sequence in the horizontal direction. In addition, a management board can be arranged in the computing framework, and the management board can obtain the load level of each first communication link and the load level of each second communication link established above, and periodically or in real time update the routing table in each processor and each networking chip, and the routing table records the load level of each first communication link and the load level of each second communication link.

[0056] In this embodiment, the description will be made from the perspective of a data transmission device, which can be specifically integrated in a computer device having a storage unit and a microprocessor installed therein and having computing capabilities.

[0057] See also Figure 4 , Figure 4 A flow chart of a data transmission method provided in an embodiment of the present application. The data transmission method includes:

[0058] In step 201, a transmission instruction for a first processor to transmit processing data to a second processor is obtained.

[0059] Among them, the first processor and the second processor can be any one of the CPU, GPU and NPU in the computing board. In the process of data processing by the AI ​​model, the data is processed by the specific processor in the computing board, and the processed data obtained after processing generally needs to be handed over to a processor with other processing functions for reprocessing, so the processed data needs to be transmitted between processors.

[0060] Specifically, when the first processor needs to send processed data to the second processor, a transmission instruction is generated to inform the computer device of the action of the first processor sending the processed data to the second processor through the transmission instruction.

[0061] In step 202, when the first processor and the second processor are not configured on the same computing board, a first target computing board networking chip is determined from computing board networking chips that have established a first communication link with the first processor.

[0062] Among them, since there are multiple processors in the same computing board, in order to determine whether the data transmission is between two processors in the same computing board or between two processors in different computing boards, it is necessary to determine whether the first processor and the second processor are configured on the same computing board.

[0063] Specifically, when the first processor and the second processor are not configured on the same computing board, it indicates that the data transmission is a cross-computing board data transmission mode (the processed data needs to be transmitted from the computing board where the first processor is located to the computing board where the second processor is located).

[0064] Among them, the data transmission method across computing boards is: the processed data is transmitted from the computing board where the first processor is located to the switching board, and then transmitted to the computing board where the second processor is located through the switching board for reception by the second processor. Therefore, the detailed transmission process of the processed data is: transmitted from the first processor to the computing board networking chip of the computing board where the first processor is located, from the computing board networking chip of the computing board where the first processor is located to the switching board networking chip, from the switching board networking chip to the computing board networking chip of the computing board where the second processor is located, and from the computing board networking chip of the computing board where the second processor is located to the second processor.

[0065] Specifically, according to the data transmission method across computing boards, the processed data first needs to be transmitted from the first processor to the computing board networking chip of the computing board where the first processor is located, so it is necessary to determine the first target computing board networking chip from the computing board networking chips that have established a first communication link with the first processor. The first target computing board networking chip is the computing board networking chip for receiving the processed data among the computing board networking chips that have established a first communication link with the first processor.

[0066] In step 203, a target switch board networking chip is determined from the switch board networking chips that have established a second communication link with the first target computing board networking chip.

[0067] Among them, according to the data transmission method across computing boards, when the first target computing board networking chip is determined, the processing data needs to be transmitted from the computing board networking chip of the computing board where the first processor is located to the switching board networking chip, so it is necessary to determine the target switching board networking chip from the switching board networking chip that has established a second communication link with the first target computing board networking chip. The target switching board networking chip is the switching board networking chip for receiving the processing data in the switching board networking chip that has established a second communication link with the first target computing board networking chip.

[0068] In step 204, a second target computing board networking chip is determined from computing board networking chips that have established a second communication link with the target switching board networking chip and have established a first communication link with the second processor.

[0069] Among them, according to the data transmission method across computing boards, when the target switching board networking chip is determined, the processing data needs to be transmitted from the switching board networking chip to the computing board networking chip of the computing board where the second processor is located, so it is necessary to determine the second target computing board networking chip from the computing board networking chip that has established a second communication link with the target switching board networking chip and a first communication link with the second processor. The second target computing board networking chip is a computing board networking chip that has established a second communication link with the target switching board networking chip, used to receive the processing data sent by the target switching board networking chip, and has established a first communication link with the second processor, used to send processing data to the second processor.

[0070] In step 205, a data transmission path is established based on the first target computing board networking chip, any of the target switching board networking chips, and the second target computing board networking chip, and the processed data is transmitted from the first processor to the second processor through the data transmission path.

[0071] Among them, after determining the first target computing board networking chip, the target switching board networking chip and the second target computing board networking chip in the data transmission method across computing boards, a complete data transmission path for processed data can be formed to transmit the processed data from the first processor to the second processor through the data transmission path.

[0072] From the above, it can be seen that the embodiment of the present application establishes a data transmission path through a first target computing board networking chip determined from the computing board networking chip that has established a first communication link with the first processor, a target switching board networking chip determined from the switching board networking chip that has established a second communication link with the first target computing board networking chip, and a second target computing board networking chip determined from the computing board networking chip that has established a second communication link with the target switching board networking chip and has established a first communication link with the second processor when the first processor and the second processor perform data transmission across computing boards, so as to transmit processed data from the first processor to the second processor through the data transmission path. Compared with the related art, in which each data transmission needs to wait for the previous data transmission to be completed before transmission can be performed, the embodiment of the present application can establish a flexible data transmission path through different networking chip combinations each time data transmission is performed, thereby avoiding data blocking and improving data transmission efficiency.

[0073] In some embodiments, see Figure 5 , Figure 5 Another flowchart of a data transmission method provided in an embodiment of the present application. The data transmission method includes:

[0074] In step 301, a transmission instruction for a first processor to transmit processing data to a second processor is obtained.

[0075] The first processor and the second processor may be any one of a CPU, a GPU, and an NPU. For example, the CPU and the CPU transmit processing data, the CPU and the GPU transmit processing data, the CPU and the NPU transmit processing data, and the GPU and the NPU transmit processing data. The first processor is the sender of the processing data, and the second processor is the receiver of the processing data.

[0076] In step 302, when the first processor and the second processor are not configured on the same computing board, each computing board networking chip that has established a first communication link with the first processor is determined as a first target computing board networking chip.

[0077] When the first processor and the second processor are not configured on the same computing board, it indicates that the processed data needs to be transmitted through a data transmission method across computing boards. Therefore, each computing board networking chip that has established a first communication link with the first processor is first determined as the first target computing board networking chip.

[0078] For example Figure 2 In the example, the first processor is processor 1 in computing board 1, and the first target computing board networking chip is computing board networking chip 1 to computing board networking chip K in computing board 1 that establish a first communication link with processor 1.

[0079] Specifically, each processor, computing board networking chip, and switch board networking chip is configured with a routing table. The routing table is used to indicate whether a communication link is established between each processor or networking chip and other processors or networking chips. When determining the first target computing board networking chip, the target switch board networking chip, and the second target computing board networking chip, each processor or networking chip can be determined based on the routing table configured internally.

[0080] In step 303, each switch board networking chip that has established a second communication link with the first target computing board networking chip is determined as a target switch board networking chip.

[0081] Among them, after determining the first target computing board networking chip, since the data transmission method across computing boards requires the switching board networking chip in the switching board to forward the processed data to the computing board where the second processor is located, it is necessary to establish each switching board networking chip with the first target computing board networking chip. The second communication link needs to be determined as the target switching board networking chip.

[0082] For example Figure 2In the embodiment, the first target computing board networking chip is computing board networking chip 1 to computing board networking chip K in computing board 1, and the target switching board networking chip is each switching board networking chip 1 to switching board networking chip M in switching board 1 to switching board P that establishes a second communication link with the computing board networking chips in computing board networking chip 1 to computing board networking chip K.

[0083] In step 304, the computing board networking chip that has established a second communication link with the target switching board networking chip and has established a first communication link with the second processor is determined as the second target computing board networking chip.

[0084] After the target switch board networking chip is determined, the data transmission method across computing boards requires the computing board networking chip of the computing board where the second processor is located to receive the processing data sent by the target switch board and forward it to the second processor. Therefore, the second target computing board networking chip is a computing board networking chip that has a second communication link established with the target switch board networking chip and a first communication link established with the second processor.

[0085] For example Figure 2 In the embodiment, the target switch board networking chip is each switch board networking chip 1 to switch board networking chip M in switch board 1 to switch board P, and the second processor is processor 1 in computing board N. Then the second target computing board networking chip is computing board networking chip 1 to computing board networking chip K in computing board N which has established a second communication link with each switch board networking chip 1 to switch board networking chip M in switch board 1 to switch board P, and has established a first communication link with processor 1 in computing board N.

[0086] Among them, by determining the networking chip, each networking chip with a communication link established is used as a data receiver, so that multiple data transmission paths can be formed, avoiding the need for each data transmission to wait for the previous data transmission to be completed before transmission, thereby improving data transmission efficiency.

[0087] Specifically, considering that data transmission may be concurrent or asynchronous, it may be that during the data transmission from the first processor to the second processor, a first communication link and / or a second communication link is occupied by other transmissions, resulting in a situation where the load is too high. Based on this, the embodiment of the present application provides the following method of determining a networking chip in combination with the load degree from step 305 to step 308, which specifically includes:

[0088] In step 305, among the computing board networking chips that have established a first communication link with the first processor, the computing board networking chip whose load level of the first communication link has not reached a preset load level is determined as the first target computing board networking chip.

[0089] The preset load level is a pre-set determination condition for determining whether the first communication link or the second communication link is in an occupied state. The first target computing board networking chip is a computing board networking chip whose load level has not reached the preset load level among the computing board networking chips that have established the first communication link with the first processor.

[0090] For example, the preset load level is 80%, the load level of the first communication link established between the processor 1 in the computing board 1 and the computing board networking chip 1 is 30%, and the load level of the first communication link established between the processor 1 and the computing board networking chip 2 is 90%. Since the load level of the first communication link established between the processor 1 and the computing board networking chip 2 is 90%, which exceeds 80%, it is determined that the first communication link established between the processor 1 and the computing board networking chip 2 is occupied; since the load level of the first communication link established between the processor 1 and the computing board networking chip 1 is 30% and does not reach 80%, it is determined that the first communication link established between the processor 1 and the computing board networking chip 2 is not occupied, and the computing board networking chip 2 is determined as the first target computing board networking chip.

[0091] Specifically, the routing table configured inside each processor and networking chip can also indicate the load level of each communication link. The load level is obtained by the management board in the computing box, and the load level of each communication link in the routing table is updated in real time or periodically so that the processor and the networking chip can determine the networking chip based on the load level.

[0092] In step 306, among the switch board networking chips that have established a second communication link with the first target computing board networking chip, the switch board networking chip whose load level of the second communication link does not reach a preset load level is determined as the target switch board networking chip.

[0093] Among them, after determining the first target computing board networking chip, a target switching board networking chip whose load level of the second communication link does not reach a preset load level is determined from the switching board networking chips that have established a second communication link with the first target computing board networking chip.

[0094] For example, the first target computing board networking chip is computing board networking chip 2 in computing board 1, and the switching board networking chip that establishes a second communication link with the computing board networking chip 2 in computing board 1 is each switching board networking chip in each switching board. From each switching board networking chip, a target switching board networking chip whose load level of the second communication link established with the computing board networking chip 2 in computing board 1 does not reach a preset load level is selected.

[0095] In step 307, among the computing board networking chips that have established a second communication link with the target switching board networking chip and a first communication link with the second processor, the computing board networking chip whose load level of the second communication link established with the target switching board networking chip has not reached the preset load level, and whose load level of the first communication link established with the second processor has not reached the preset load level, is determined as the second target computing board networking chip.

[0096] Among them, when determining the second target computing board networking chip based on the load level, since the second target computing board networking chip needs to simultaneously establish a second communication link with the target switch board networking chip and a first communication link with the second processor, in order to ensure that the processed data received from the target switch board networking chip can be sent to the second processor, it is necessary to ensure that the load level of the second communication link established between the second target computing board networking chip and the target switch board networking chip, and the load level of the first communication link established with the second processor do not reach the preset load level.

[0097] Among them, by taking into account the problem of communication link occupation caused by concurrency or asynchrony in data transmission, when determining the networking chip, each networking chip is determined in combination with the load level, so that every part of the data transmission path finally formed will not be occupied, avoiding the need for each data transmission to wait for the previous data transmission to be completed before transmission can be carried out, so as to improve data transmission efficiency.

[0098] In step 308, a data transmission path is established in combination with the first communication link established between the first processor and the first target computing board networking chip, the second communication link established between the first target computing board networking chip and the target switch board networking chip, the second communication link established between the target switch board networking chip and the second target computing board networking chip, and the first communication link established between the second target computing board networking chip and the second processor, and the processed data is transmitted from the first processor to the second processor through the data transmission path.

[0099] Among them, after determining the first target computing board networking chip, the target switch board networking chip and the second target computing board networking chip in sequence, the first communication link between the first processor and the first target computing board networking chip, the second communication link established between the first target computing board networking chip and the target switch board networking chip, the second communication link established between the target switch board networking chip and the second target computing board networking chip, and the first communication link established between the second target computing board networking chip and the second processor form a continuous path as a data transmission path for processing data, so as to transmit the processed data from the first processor to the second processor through the data transmission path.

[0100] Specifically, in the process of transmitting the processed data along the data transmission path, the sender of the processed data may divide the processed data according to the number of receivers to transmit part of the data content of the processed data through the transmission route between each receiver.

[0101] For example, in the process of the first processor transmitting processed data to the first target computing board networking chip, if the number of the first target computing board networking chips is 3, the first processor will divide the processed data into three partial data contents, and transmit one partial data content of the three data through the first communication link between the first processor and each target computing board networking chip, so as to further improve the efficiency of data transmission.

[0102] In some embodiments, see Figure 6 , Figure 6 Another flowchart of a data transmission method provided in an embodiment of the present application. The data transmission method includes:

[0103] In step 401, a transmission instruction for a first processor to transmit processing data to a second processor is obtained.

[0104] The first processor and the second processor may be any one of a CPU, a GPU, and an NPU.

[0105] In step 402, when the first processor and the second processor are configured on the same computing board, a third target computing board networking chip is determined from computing board networking chips that have established a first communication link with the first processor and have established a first communication link with the second processor.

[0106] If the first processor and the second processor are configured on the same computing board, it means that the data transmission between the first processor and the second processor is only performed within the computing board, that is, a non-cross-computing board transmission mode. Since the switch board is used only when the data is transmitted across computing boards, in the non-cross-computing board transmission mode, it is only necessary to determine the computing board networking chip used for transmitting the processed data from the computing board networking chips that have established the first communication link with the first processor and the second processor respectively, that is, the third target computing board networking chip.

[0107] In step 403, a data transmission path is established based on the first processor, any third target computing board networking chip, and the second processor, and the processed data is transmitted from the first processor to the second processor through the data transmission path.

[0108] Among them, after determining the third target computing board networking chip in this cross-computing board data transmission method, a complete data transmission path for processing data can be formed to transmit the processed data from the first processor to the second processor through the data transmission path.

[0109] In some embodiments, see Figure 7 , Figure 7 Another flowchart of a data transmission method provided in an embodiment of the present application. The data transmission method includes:

[0110] In step 501, a transmission instruction for a first processor to transmit processing data to a second processor is obtained.

[0111] The first processor and the second processor may be any one of a CPU, a GPU, and an NPU.

[0112] In step 502, each computing board networking chip that has a first communication link established with the first processor and a first communication link established with the second processor is determined as a third target computing board networking chip.

[0113] When the first processor and the second processor are configured on the same computing board, it means that the processed data does not need to be transmitted through the data transmission method across computing boards. Therefore, each computing board networking chip that has established a first communication link with the first processor and the second processor is determined as the first target computing board networking chip.

[0114] For example Figure 2 In the figure, the first processor is processor 1 in computing board 1, and the second processor is processor 2 in computing board 1. Then the first target computing board networking chip is computing board networking chip 1 to computing board networking chip K in computing board 1 which have established first communication links with processor 1 and processor 2 respectively.

[0115] Specifically, each processor is internally configured with a routing table, which is used to indicate whether a first communication link is established between each processor and the computer networking chip, so that when determining the third target computing board networking chip, each processor can determine it according to its internally configured routing table.

[0116] Considering that data transmission may be concurrent or asynchronous, it is possible that during the data transmission from the first processor to the second processor, a first communication link may be occupied by other transmissions, resulting in excessive load. Based on this, the embodiment of the present application provides the following step 503, which specifically includes:

[0117] In step 503, the computing board networking chip that has established a first communication link with the first processor and a first communication link with the second processor, the load level of the first communication link established with the first processor has not reached the preset load level, and the load level of the first communication link established with the second processor has not reached the preset load level, is determined as the third target computing board networking chip.

[0118] The preset load level is a pre-set determination condition for determining whether the first communication link is in an occupied state. The third target computing board networking chip is a computing board networking chip whose load level has not reached the preset load level among the computing board networking chips that have established a first communication link with the first processor and a second communication link with the second processor.

[0119] For example, the preset load level is 80%, the load level of the first communication link established between the processor 1 in the computing board 1 and the computing board networking chip 1 is 30%, and the load level of the first communication link established between the processor 1 and the computing board networking chip 2 is 90%. Since the load level of the first communication link established between the processor 1 and the computing board networking chip 2 is 90%, which exceeds 80%, it is determined that the first communication link established between the processor 1 and the computing board networking chip 2 is occupied; since the load level of the first communication link established between the processor 1 and the computing board networking chip 1 is 30% and does not reach 80%, it is determined that the first communication link established between the processor 1 and the computing board networking chip 2 is not occupied, and the computing board networking chip 2 is determined as the third target computing board networking chip.

[0120] In step 504, a data transmission path is established by combining the first communication link established between the first processor and the third target computing board networking chip and the first communication link established between the third target computing board networking chip and the second processor.

[0121] Among them, after determining the third target computing board networking chip, the continuous path formed by the first communication link between the first processor and the first target computing board networking chip, the first communication link established by the third target computing board networking chip, and the first communication link established by the third target computing board networking chip and the second processor is used as a data transmission path for processing data, so as to transmit the processed data from the first processor to the second processor through the data transmission path.

[0122] Specifically, in the process of transmitting the processed data along the data transmission path, the sender of the processed data may divide the processed data according to the number of receivers to transmit part of the data content of the processed data through the transmission route between each receiver.

[0123] In addition, before the processed data is divided, the data volume of the processed data can be compared with the preset data volume, and the preset data volume is a determination condition for determining whether the processed data is large data. If the data volume of the processed data reaches the preset data volume, it means that the processed data is large data and the data volume is large, and the step of dividing the processed data according to the number of receivers is performed; if the data volume of the processed data does not reach the preset data volume, it means that the processed data is not large data and the data volume is small. If it is divided, it is not more efficient than direct transmission, and the step of dividing the processed data according to the number of receivers is not performed.

[0124] Among them, after determining the data transmission path, the number of paths of the data transmission path and the number of transmission tasks included in each data transmission path can also be obtained. According to the number of transmission tasks and the number of paths corresponding to each data transmission path, the processed data is divided to divide out part of the processed data suitable for each data transmission path, so as to balance the transmission task volume of each data transmission path.

[0125] Specifically, when the data transmission mode is a data transmission mode across computing boards, the transmission task amount included in each data transmission path is the sum of the transmission task amount of the first communication link established between the first processor and the first target computing board networking chip, the transmission task amount of the second communication link established between the first target computing board networking chip and the target switch board networking chip, the transmission task amount of the second communication link established between the target switch board networking chip and the second target computing board networking chip, and the transmission task amount of the first communication link established between the second target computing board networking chip and the second processor; when the data transmission mode is a data transmission mode across computing boards, the transmission task amount included in each data transmission path is the sum of the transmission task amount of the first communication link established between the first processor and the third target computing board networking chip, and the transmission task amount of the first communication link established between the third target computing board networking chip and the second processor.

[0126] Among them, according to the transmission task amount and the number of paths corresponding to each data transmission path, it includes:

[0127] Obtaining the transmission task volume of each data transmission path and the target task volume required for transmitting and processing data;

[0128] Calculating a sum of transmission task amounts of multiple data transmission paths to obtain a first total transmission task amount;

[0129] Determine the sum of the target task amount and the first total transmission task amount to obtain a second total transmission task amount;

[0130] Obtaining the ratio of the second total transmission task volume to the number of paths to obtain an average transmission task volume;

[0131] The difference between the transmission task amount of each data transmission path and the average transmission task amount is determined as the allocated data amount of each data transmission path;

[0132] The target task volume is allocated to each data transmission path according to the allocated data volume of each data transmission path.

[0133] For example, when the transmission task volume corresponding to data transmission path A is 3, the transmission task volume corresponding to data transmission path B is 2, and the transmission task volume corresponding to data transmission path C is 1, the number of paths is 3, the first total transmission task volume for processing data is 6, and the target task volume required for transmission is 12, then the second total transmission task volume is 18. Since the number of paths is 3, the average transmission task volume is 6, the allocated data volume corresponding to data transmission path A is 6-3=3, the allocated data volume corresponding to data transmission path B is 6-2=4, and the allocated data volume corresponding to data transmission path C is 6-1=5. Three tasks are divided from the target task volume and allocated to data transmission path A, four tasks are divided from the target task volume and allocated to data transmission path B, and five tasks are divided from the target task volume and allocated to data transmission path C, so that the allocated transmission task volumes of data transmission path A, data transmission path B and data transmission path C are all 6, so as to achieve balanced transmission task volume of each data transmission path.

[0134] In some embodiments, Figure 8 As shown, Figure 8 Another schematic diagram of the architecture of a computer device provided in an embodiment of the present application. Figure 8For example, a computing framework is configured in a computer device. The computing framework includes 16 computing boards and 8 switching boards. Four computing board networking chips (HCCS L1-1, HCCS L1-2, HCCS L1-3 and HCCS L1-4) based on HCCS are configured inside each computing board, and four switching board networking chips (L2-1, L2-2, L2-3 and L2-4) based on HCCS are configured inside each switching board. Each computing board networking chip establishes a second communication link with each switching board networking chip to form a super node network. Inside each computing board, each processor establishes a first communication link with the switching board networking chip on the same computing board to form an L1 network. Among them, a computing board networking chip (L1) based on ROH is also configured on each computing board, and a computing board networking chip (L2) based on ROH is also configured on each switching board. A communication link is established through L1 and L2 to form an L2 network. Among them, a fast serial communication electronic computer expansion system bus specification (Peripheral Component Interconnect Express, PCIE) is also set on each computing board, so that processors on the same computing board can transmit processing data through PCIE.

[0135] Among them, the supernode network is implemented on the first computing network layer and the second computing network layer in the computing box 110, and has no effect on traditional dedicated network communications. The processors in the computing board are connected to the computing board networking chip to form the first computing network layer of the supernode network. The network bandwidth of the first computing network layer can reach 650GB per second, and up to 4 neural network processors and 2 central processing units can be connected together. The switching board networking chip of the switching board in the computing box is interconnected with the computing board networking chip of the computing board to form the second computing network layer of the supernode network. The network bandwidth of the second computing network layer of the supernode network is as high as 650GB / s, and up to 64 neural network processors in the computing box can be connected. The first computing network layer and the second computing network layer together constitute a low-latency, high-performance, large-bandwidth, non-convergent high-performance supernode network.

[0136] The supernode network can realize high-speed interconnection between processors in the computing frame. For example, when NPU0 and NPU1 in the computing board transmit data, the optimal forwarding path can be automatically selected according to the load of the four computing board networking chips (HCCS L1). After NPU0's data is forwarded to the HCCS L1 chip, it can directly reach NPU1, avoiding the occurrence of network congestion caused by data forwarding from a remote direct data access network card. The first computing network layer and the second computing network layer of the supernode network described in this application are used to connect 64 NPU chips on 16 computing boards to realize a non-blocking, non-convergent supernode network, which is more friendly to artificial intelligence model training tasks.

[0137] Specifically, when data transmission is required between processors, data transmission can be performed through three methods: a super-node network built by HCCS, an L2 network built by ROH, or direct transmission by PCIE, thereby improving the diversity of data transmission and avoiding the problem of processing data not being able to be transmitted in time due to link occupation, resulting in slow transmission efficiency.

[0138] In addition, a cold plate-type full liquid cooling solution is adopted. The cold plate covers the main heat-generating components such as CPU, NPU, memory and network chips. No fan is required for heat dissipation, thus saving space. When a single computing framework contains 16 computing boards, 8 switching boards and 2 management boards, and the computer equipment accommodates 2 computing frames, the maximum AI computing power can reach more than 80 floating-point operations per second (PFLOPS).

[0139] The specific implementation of the above steps can be found in the previous embodiments, which will not be described in detail here.

[0140] In order to better implement the data transmission method provided in the embodiment of the present application, the embodiment of the present application also provides a device based on the above data transmission method. The meanings of the terms are the same as those in the above data transmission method, and the specific implementation details can refer to the description in the method embodiment.

[0141] See also Fig. 9 , Fig. 9A structural schematic diagram of a data transmission method device provided in an embodiment of the present application, the data transmission method device is applied to a computer device, the computer device includes at least one computing framework, the computing framework includes at least two computing boards and at least one switching board orthogonally connected to each of the computing boards, wherein each of the computing boards is configured with at least two computing board networking chips, and at least two processors that establish a first communication link with each of the computing board networking chips, each of the switching boards is configured with at least two switching board networking chips, and each of the computing board networking chips establishes a second communication link with each of the switching board networking chips. The data transmission method device may include an acquisition unit 601, a first determination unit 602, a second determination unit 603, a third determination unit 604, and an establishment unit 605, etc.

[0142] An acquisition unit 601 is used to acquire a transmission instruction for the first processor to transmit processing data to the second processor;

[0143] A first determining unit 602 is configured to determine a first target computing board networking chip from computing board networking chips that have established a first communication link with the first processor when the first processor and the second processor are not configured on the same computing board;

[0144] A second determining unit 603 is used to determine a target switching board networking chip from the switching board networking chips that have established a second communication link with the first target computing board networking chip;

[0145] A third determining unit 604 is used to determine a second target computing board networking chip from the computing board networking chips that have established a second communication link with the target switching board networking chip and have established a first communication link with the second processor;

[0146] Establishing unit 605 is used to establish a data transmission path based on the first target computing board networking chip, any of the target switching board networking chips and the second target computing board networking chip, and transmit the processed data from the first processor to the second processor through the data transmission path.

[0147] In some embodiments, the first determining unit 602 is configured to:

[0148] Determine each computing board networking chip that has established a first communication link with the first processor as a first target computing board networking chip;

[0149] The second determining unit 603 is configured to:

[0150] Determine the switch board networking chip that has established a second communication link with the first target computing board networking chip as the target switch board networking chip;

[0151] The third determining unit 604 is configured to:

[0152] A computing board networking chip that has established a second communication link with the target switching board networking chip and a first communication link with the second processor is determined as a second target computing board networking chip.

[0153] In some embodiments, the first determining unit 602 is configured to:

[0154] Determine, among the computing board networking chips that have established a first communication link with the first processor, a computing board networking chip whose load level of the first communication link has not reached a preset load level as a first target computing board networking chip;

[0155] The second determining unit 603 is configured to:

[0156] Determine, as a target switch board networking chip, a switch board networking chip whose load level of the second communication link does not reach a preset load level among the switch board networking chips that have established a second communication link with the first target computing board networking chip;

[0157] The third determining unit 604 is configured to:

[0158] Among the computing board networking chips that have established a second communication link with the target switch board networking chip and a first communication link with the second processor, the computing board networking chip whose load level of the second communication link established with the target switch board networking chip has not reached the preset load level, and whose load level of the first communication link established with the second processor has not reached the preset load level, is determined as the second target computing board networking chip.

[0159] In some embodiments, the establishing unit 605 is used to:

[0160] A data transmission path is established by combining the first communication link established between the first processor and the first target computing board networking chip, the second communication link established between the first target computing board networking chip and the target switch board networking chip, the second communication link established between the target switch board networking chip and the second target computing board networking chip, and the first communication link established between the second target computing board networking chip and the second processor.

[0161] In some embodiments, the data transmission device is further used to:

[0162] When the first processor and the second processor are configured on the same computing board, determining a third target computing board networking chip from computing board networking chips that have established a first communication link with the first processor and have established a first communication link with the second processor;

[0163] A data transmission path is established based on the first processor, the third target computing board networking chip and the second processor, and the processed data is transmitted from the first processor to the second processor through the data transmission path.

[0164] In some embodiments, the data transmission device is further used to:

[0165] Each computing board networking chip among the computing board networking chips that has established a first communication link with the first processor and has established a first communication link with the second processor is determined as a third target computing board networking chip.

[0166] In some embodiments, the data transmission device is further used to:

[0167] Among the computing board networking chips, the computing board networking chips that have established a first communication link with the first processor and a first communication link with the second processor, the computing board networking chips whose load level of the first communication link established with the first processor has not reached a preset load level, and the computing board networking chips whose load level of the first communication link established with the second processor has not reached a preset load level, are determined as third target computing board networking chips.

[0168] In some embodiments, the data transmission device is further used to:

[0169] A data transmission path is established by combining a first communication link established between the first processor and the third target computing board networking chip and a first communication link established between the third target computing board networking chip and the second processor.

[0170] The specific implementation of each of the above units can be found in the previous embodiments, which will not be described in detail here.

[0171] As can be seen from the above, the embodiment of the present application obtains a transmission instruction for the first processor to transmit processing data to the second processor through an acquisition unit 601; the first determination unit 602 determines the first target computing board networking chip from the computing board networking chip that has established a first communication link with the first processor when the first processor and the second processor are not configured on the same computing board; the second determination unit 603 determines the target switching board networking chip from the switching board networking chip that has established a second communication link with the first target computing board networking chip; the third determination unit 604 determines the second target computing board networking chip from the computing board networking chip that has established a second communication link with the target switching board networking chip and has established a first communication link with the second processor; the establishment unit 605 establishes a data transmission path based on the first target computing board networking chip, any of the target switching board networking chips and the second target computing board networking chip, and transmits the processed data from the first processor to the second processor through the data transmission path.

[0172] In this way, each time data transmission is performed, a flexible data transmission path is established through different networking chip combinations to avoid data blocking and improve data transmission efficiency. When determining the networking chip, each networking chip with an established communication link is used as a data receiver, so that multiple data transmission paths can be formed, avoiding the need to wait for the previous data transmission to be completed before each data transmission can be performed, thereby improving data transmission efficiency. Taking into account the problem of communication link occupation caused by possible concurrency or asynchrony in data transmission, when determining the networking chip, each networking chip is determined in combination with the load level, so that each part of the data transmission path finally formed will not be occupied, avoiding the need to wait for the previous data transmission to be completed before each data transmission can be performed, thereby improving data transmission efficiency.

[0173] The specific implementation of each of the above units can be found in the previous embodiments, which will not be described in detail here.

[0174] Reference Fig.10 , Fig.10The block diagram of the structure of part of the computer device 1000 for implementing the embodiment of the present disclosure. The computer device 1000 may have relatively large differences due to different configurations or performances, and may include one or more central processing units (CPUs) 622 (for example, one or more processors) and memory 632, and one or more storage media 630 (for example, one or more mass storage devices) storing application programs 642 or data 644. Among them, the memory 632 and the storage medium 630 can be temporary storage or permanent storage. The program stored in the storage medium 630 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations on the server 600. Furthermore, the central processing unit 622 can be configured to communicate with the storage medium 630 and execute a series of instruction operations in the storage medium 630 on the server 600.

[0175] The computer device 1000 may also include one or more power supplies 626, one or more wired or wireless network interfaces 650, one or more input and output interfaces 658, and / or one or more operating systems 641, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0176] The central processor 622 in the computer device 1000 may be used to execute the data transmission method of the embodiment of the present disclosure, for example:

[0177] Obtaining a transmission instruction for transmitting processing data from the first processor to the second processor;

[0178] When the first processor and the second processor are not configured on the same computing board, determining a first target computing board networking chip from computing board networking chips that have established a first communication link with the first processor;

[0179] Determine a target switch board networking chip from the switch board networking chips that have established a second communication link with the first target computing board networking chip;

[0180] Determine a second target computing board networking chip from computing board networking chips that have established a second communication link with the target switching board networking chip and have established a first communication link with the second processor;

[0181] A data transmission path is established based on the first target computing board networking chip, any of the target switching board networking chips, and the second target computing board networking chip, and the processed data is transmitted from the first processor to the second processor through the data transmission path.

[0182] The embodiments of the present disclosure further provide a computer-readable storage medium, which is used to store program codes, and the program codes are used to execute the data transmission methods of the aforementioned embodiments.

[0183] The present disclosure also provides a computer program product, which includes a computer program. The processor of a computer device reads and executes the computer program, so that the computer device executes the above-mentioned data transmission method. For example:

[0184] Obtaining a transmission instruction for transmitting processing data from the first processor to the second processor;

[0185] When the first processor and the second processor are not configured on the same computing board, determining a first target computing board networking chip from computing board networking chips that have established a first communication link with the first processor;

[0186] Determine a target switch board networking chip from the switch board networking chips that have established a second communication link with the first target computing board networking chip;

[0187] Determine a second target computing board networking chip from computing board networking chips that have established a second communication link with the target switching board networking chip and have established a first communication link with the second processor;

[0188] A data transmission path is established based on the first target computing board networking chip, any of the target switching board networking chips, and the second target computing board networking chip, and the processed data is transmitted from the first processor to the second processor through the data transmission path.

[0189] In addition, the terms "comprises" and "includes" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus that includes a series of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such process, method, product or apparatus.

[0190] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0191] It should be understood that in the description of the embodiments of the present application, the meaning of multiple (or multiple items) is more than two, greater than, less than, exceed, etc. are understood to not include the number, and above, below, within, etc. are understood to include the number.

[0192] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0193] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0194] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0195] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store program codes.

[0196] It should also be understood that the various implementations provided in the embodiments of the present application can be combined arbitrarily to achieve different technical effects.

[0197] In the embodiments of the present application, the term "module" or "unit" refers to a computer program or a part of a computer program that has a predetermined function and works together with other related parts to achieve a predetermined goal, and can be implemented in whole or in part by using software, hardware (such as processing circuits or memories), or a combination thereof. Similarly, a processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be part of an overall module or unit that includes the function of the module or unit.

[0198] The above is a specific description of the implementation method of the present application, but the present application is not limited to the above-mentioned implementation method. Technical personnel familiar with the field can also make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A data transmission method, characterized in that: Applied to a computer device, the computer device includes at least one computing framework, the computing framework includes at least two computing boards and at least one switching board orthogonally connected to each of the computing boards, wherein each of the computing boards is configured with at least two computing board networking chips, and at least two processors that establish a first communication link with each of the computing board networking chips, each of the switching boards is configured with at least two switching board networking chips, each of the computing board networking chips establishes a second communication link with each of the switching board networking chips, and the data transmission method includes: Obtaining a transmission instruction for transmitting processing data from the first processor to the second processor; When the first processor and the second processor are not configured on the same computing board, determining a first target computing board networking chip from computing board networking chips that have established a first communication link with the first processor; Determine a target switch board networking chip from the switch board networking chips that have established a second communication link with the first target computing board networking chip; Determine a second target computing board networking chip from computing board networking chips that have established a second communication link with the target switching board networking chip and have established a first communication link with the second processor; Establishing a data transmission path based on the first target computing board networking chip, the target switch board networking chip, and the second target computing board networking chip, and transmitting the processed data from the first processor to the second processor through the data transmission path; When the first processor and the second processor are configured on the same computing board, determining a third target computing board networking chip from computing board networking chips that have established a first communication link with the first processor and have established a first communication link with the second processor; A data transmission path is established based on the first processor, the third target computing board networking chip and the second processor, and the processed data is transmitted from the first processor to the second processor through the data transmission path.

2. The data transmission method according to claim 1, characterized in that: The step of determining a first target computing board networking chip from computing board networking chips that have established a first communication link with the first processor includes: Determine each computing board networking chip that has established a first communication link with the first processor as a first target computing board networking chip; The step of determining a target switch board networking chip from the switch board networking chips that have established a second communication link with the first target computing board networking chip comprises: Determine the switch board networking chip that has established a second communication link with the first target computing board networking chip as the target switch board networking chip; The determining a second target computing board networking chip from the computing board networking chips that have established a second communication link with the target switching board networking chip and have established a first communication link with the second processor includes: A computing board networking chip that has established a second communication link with the target switching board networking chip and a first communication link with the second processor is determined as a second target computing board networking chip.

3. The data transmission method according to claim 1, characterized in that: The step of determining a first target computing board networking chip from computing board networking chips that have established a first communication link with the first processor includes: Determine, among the computing board networking chips that have established a first communication link with the first processor, a computing board networking chip whose load level of the first communication link has not reached a preset load level as a first target computing board networking chip; The step of determining a target switch board networking chip from the switch board networking chips that have established a second communication link with the first target computing board networking chip comprises: Determine, as a target switch board networking chip, a switch board networking chip whose load level of the second communication link does not reach a preset load level among the switch board networking chips that have established a second communication link with the first target computing board networking chip; The determining a second target computing board networking chip from the computing board networking chips that have established a second communication link with the target switching board networking chip and have established a first communication link with the second processor includes: Among the computing board networking chips that have established a second communication link with the target switch board networking chip and a first communication link with the second processor, the computing board networking chip whose load level of the second communication link established with the target switch board networking chip has not reached the preset load level, and whose load level of the first communication link established with the second processor has not reached the preset load level, is determined as the second target computing board networking chip.

4. The data transmission method according to any one of claims 1 to 3, characterized in that: The establishing of a data transmission path based on the first target computing board networking chip, the target switching board networking chip, and the second target computing board networking chip includes: A data transmission path is established by combining the first communication link established between the first processor and the first target computing board networking chip, the second communication link established between the first target computing board networking chip and the target switch board networking chip, the second communication link established between the target switch board networking chip and the second target computing board networking chip, and the first communication link established between the second target computing board networking chip and the second processor.

5. The data transmission method according to claim 1, characterized in that: The determining a third target computing board networking chip from the computing board networking chips that have established a first communication link with the first processor and have established a first communication link with the second processor includes: Each computing board networking chip among the computing board networking chips that has established a first communication link with the first processor and has established a first communication link with the second processor is determined as a third target computing board networking chip.

6. The data transmission method according to claim 1, characterized in that: The determining a third target computing board networking chip from the computing board networking chips that have established a first communication link with the first processor and have established a second communication link with the second processor includes: Among the computing board networking chips, the computing board networking chips that have established a first communication link with the first processor and a first communication link with the second processor, the computing board networking chips whose load level of the first communication link established with the first processor has not reached a preset load level, and the computing board networking chips whose load level of the first communication link established with the second processor has not reached a preset load level, are determined as third target computing board networking chips.

7. The data transmission method according to any one of claims 1, 5 or 6, characterized in that: The establishing of a data transmission path based on the first processor, the third target computing board networking chip and the second processor includes: A data transmission path is established by combining a first communication link established between the first processor and the third target computing board networking chip and a first communication link established between the third target computing board networking chip and the second processor.

8. A data transmission device, applied to a computer device, the computer device comprising at least one computing framework, the computing framework comprising at least two computing boards and at least one switching board orthogonally connected to each of the computing boards, wherein: Each of the computing boards is configured with at least two computing board networking chips, and at least two processors that establish a first communication link with each of the computing board networking chips, each of the switching boards is configured with at least two switching board networking chips, each of the computing board networking chips establishes a second communication link with each of the switching board networking chips, and the data transmission device includes: An acquisition unit, used to acquire a transmission instruction from the first processor to transmit processing data to the second processor; A first determining unit is used to determine a first target computing board networking chip from computing board networking chips that have established a first communication link with the first processor when the first processor and the second processor are not configured on the same computing board; A second determining unit is used to determine a target switching board networking chip from the switching board networking chips that have established a second communication link with the first target computing board networking chip; A third determining unit is used to determine a second target computing board networking chip from the computing board networking chips that have established a second communication link with the target switching board networking chip and have established a first communication link with the second processor; an establishing unit, configured to establish a data transmission path based on the first target computing board networking chip, any of the target switching board networking chips, and the second target computing board networking chip, and transmit the processed data from the first processor to the second processor through the data transmission path; The data transmission device is further used for: When the first processor and the second processor are configured on the same computing board, determining a third target computing board networking chip from computing board networking chips that have established a first communication link with the first processor and have established a first communication link with the second processor; A data transmission path is established based on the first processor, the third target computing board networking chip and the second processor, and the processed data is transmitted from the first processor to the second processor through the data transmission path.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor to execute the data transmission method according to any one of claims 1 to 7.

10. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the data transmission method according to any one of claims 1 to 7 is implemented.

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