Printed circuit board, method of manufacturing the same and circuit board assembly

Abstract

The application provides a printed circuit board, a preparation method thereof and a circuit board assembly. By arranging an electrical connection part on a metal layer and selectively reducing the copper of the metal layer, a small-pitch pad can be made, so that the horizontal size of the soldering area of the electronic component and the printed circuit board can be reduced. Moreover, by selectively reducing the copper for multiple times to form a surface height difference (the surface of the pad is lower than the surface of the first outer line layer), the pad is in a concave structure, the soldering packaging height of the printed circuit board and the electronic component can be reduced, and the size in the vertical direction can be reduced. In addition, a heat dissipation block (thick copper area) is arranged near the pad, and the heat dissipation block and the unetched metal layer are connected to the surface of the printed circuit board, so that a heat dissipation channel of the electronic component can be formed, heat dissipation can be accelerated, and the heat dissipation performance is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit board, in particular to a printed circuit board preparation method, a printed circuit board and a circuit board assembly. BACKGROUND

[0002] With the overall size of chip and other electronic components tends to miniaturization or even micro development, the requirements for soldering packaging height and printed circuit board (PCB) through line spacing are also more and more strict. However, when the existing printed circuit board meets the small pitch of the solder pad (the pitch of the solder pad is generally 0.35mm, and the diameter of the solder pad is generally 0.25mm), it often cannot meet the demand of thick copper on the outer layer, resulting in poor heat dissipation performance. The existing printed circuit board can only make a choice between meeting the small pitch of the solder pad and meeting the heat dissipation demand. SUMMARY

[0003] Therefore, the present application provides a printed circuit board preparation method, so that the printed circuit board can have the characteristics of small pitch of the solder pad and good heat dissipation performance.

[0004] An embodiment of the present application provides a printed circuit board preparation method, comprising the following steps:

[0005] A first substrate is provided, which comprises a metal layer, a dielectric layer arranged on the surface of the metal layer, an inner layer circuit layer formed on the surface of the dielectric layer away from the metal layer, a plurality of electrical connection parts arranged in the dielectric layer and a heat dissipation block, the inner layer circuit layer is electrically connected with the electrical connection parts; the metal layer comprises a first area, a second area, a third area and a fourth area, the first area corresponds to the electrical connection parts, the second area corresponds to the heat dissipation block, the third area is located between adjacent first areas and between the first area and the second area, and the fourth area is other area of the metal layer except the first area, the second area and the third area;

[0006] A second substrate is laminated on the side of the first substrate away from the metal layer, the second substrate comprises at least one conductive layer and at least one insulating layer, each insulating layer is arranged between two adjacent conductive layers, and one insulating layer is arranged between the first substrate and the conductive circuit layer;

[0007] The thickness of the third area is thinned;

[0008] The thickness of the second area and the first area is thinned, and the thinned third area is removed, and the thinned first area forms a solder pad connected with the electrical connection parts;

[0009] The fourth region is made into a first outer layer circuit layer, and the outermost conductive layer of the second substrate is made into a second outer layer circuit layer.

[0010] In one embodiment, the preparation method further comprises the step of: disposing a protective layer outside the first outer layer circuit layer and the second outer layer circuit layer, respectively.

[0011] In one embodiment, the preparation method further comprises the step of: performing surface treatment on the solder pad and the thinned second region.

[0012] In one embodiment, before the step of "thinning the third region", the preparation method further comprises the step of: disposing a conductive hole in the first substrate and the second substrate to electrically connect the first substrate and the second substrate.

[0013] In one embodiment, the preparation method of the first substrate comprises the steps of: providing a metal layer, disposing a plurality of the electrically connecting parts and heat dissipation blocks on the surface of the metal layer; disposing the dielectric layer on the surface of the metal layer, the dielectric layer covering the third region and the fourth region away from the surface of the metal layer; disposing an electroplated layer on the surface of the dielectric layer away from the metal layer; and making the electroplated layer into an inner layer circuit layer, the inner layer circuit layer being electrically connected with the electrically connecting parts, to obtain the first substrate.

[0014] In one embodiment, before the step of disposing a plurality of the electrically connecting parts and heat dissipation blocks, the method further comprises the step of: disposing a carrier layer on the surface of the metal layer. The plurality of the electrically connecting parts and heat dissipation blocks are disposed on the surface of the metal layer away from the carrier layer.

[0015] In one embodiment, after the step of making the electroplated layer into an inner layer circuit layer, the method further comprises the step of: removing the carrier layer.

[0016] One embodiment of the present application provides a printed circuit board comprising a first substrate and a second substrate electrically connected.

[0017] The first substrate comprises a dielectric layer, an inner layer circuit layer formed on one surface of the dielectric layer, a solder pad and a first outer layer circuit layer formed on the other surface of the dielectric layer, an electrically connecting part and a heat dissipation block disposed in the dielectric layer. The electrically connecting part electrically connects the inner layer circuit layer and the solder pad.

[0018] The second substrate comprises at least one conductive circuit layer and at least one insulating layer, each insulating layer being disposed between two adjacent conductive circuit layers. One insulating layer is disposed between the first substrate and one conductive circuit layer, and the outermost conductive circuit layer is a second outer layer circuit layer.

[0019] In one embodiment, the diameter of the pad is 0.1mm-0.2mm, and the distance between two adjacent pads is 0.1mm-0.2mm.

[0020] In one embodiment, the application provides a circuit board assembly comprising an electronic component and the printed circuit board as described above. The electronic component is electrically connected to the pad.

[0021] In one embodiment, the application can make small-pitch pads by setting the electrically connecting part on the metal layer and selectively reducing the copper of the metal layer, so as to reduce the horizontal size of the soldering area of the electronic component and the printed circuit board. In addition, the application can form the surface height difference (the surface of the pad is lower than the surface of the first outer layer circuit layer) by selectively reducing the copper for multiple times, so as to make the pad in a concave structure, reduce the packaging height of the soldering of the printed circuit board and the electronic component, and reduce the size in the vertical direction. Furthermore, the heat dissipation block (thick copper area) is arranged near the pad and connected to the surface of the printed circuit board through the unetched metal layer, so as to form the heat dissipation channel of the electronic component, accelerate the heat dissipation, and improve the heat dissipation performance. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figures 1 to 6 The cross-sectional view of preparing the first substrate in one embodiment of the application is shown.

[0023] Figure 7 The cross-sectional view of the first substrate in one embodiment of the application is shown. Figure 6 The cross-sectional view of pressing the second substrate on the side of the first substrate in one embodiment of the application is shown.

[0024] Figure 8 The cross-sectional view of thinning the third region of the structure shown in one embodiment of the application is shown. Figure 7 The cross-sectional view of thinning the first region and the second region of the structure shown in one embodiment of the application is shown.

[0025] Figure 9 The cross-sectional view of removing the third region of the structure shown in one embodiment of the application is shown. Figure 8 The cross-sectional view of thinning the first region and the second region of the structure shown in one embodiment of the application is shown.

[0026] Figure 10 The cross-sectional view of forming the first outer layer circuit layer and the second outer layer circuit layer from the fourth region of the structure shown in one embodiment of the application is shown. Figure 9 The cross-sectional view of forming the first outer layer circuit layer and the second outer layer circuit layer from the fourth region of the structure shown in one embodiment of the application is shown.

[0027] Figure 11 The cross-sectional view of setting the protective layer on the outside of the structure shown in one embodiment of the application is shown. Figure 10

[0028] The cross-sectional view of the printed circuit board obtained by surface treating the pad and the second region of the structure shown in one embodiment of the application is shown. Figure 12 Figure 11

[0029] ​​Figure 13 A cross-sectional view of a circuit board assembly according to an embodiment of the present application.

[0030] Figure 14 A cross-sectional view of a circuit board assembly according to an embodiment of the present application. Figure 13 A cross-sectional view of a circuit board assembly according to an embodiment of the present application.

[0031] Explanation of main component symbols

[0032] Printed circuit board 100

[0033] First substrate 10

[0034] Second substrate 20

[0035] Metal layer 11

[0036] Carrier layer 12

[0037] Electrical connection portion 13

[0038] Heat sink 14

[0039] Dielectric layer 15

[0040] Plated layer 16

[0041] Inner layer circuit layer 17

[0042] First region 111

[0043] Second region 112

[0044] Third region 113

[0045] Fourth region 114

[0046] Conductive layer 21

[0047] Insulating layer 22

[0048] Via hole 30

[0049] Conductive via hole 31

[0050] Metal layer 40, 41

[0051] Pad 1111

[0052] First outer layer circuit layer 18

[0053] Second outer layer circuit layer 23

[0054] Protective layer 50

[0055] Plated gold layer 60

[0056] Conductive circuit layer 24

[0057] Circuit board assembly 1000

[0058] Electronic component 200

[0059] Ball grid array 201

[0060] The following detailed description will further describe the embodiments of the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of the present application belong. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the present application.

[0062] It should be noted that all directional directions (such as up, down, left, right, front, back, etc.) used in the embodiments of the present application are only used to explain the relative positional relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional directions also change accordingly.

[0063] It will be understood that when a layer is referred to as being "on" another layer, it can be directly on the other layer or intervening layers can also be present. In contrast, when a layer is referred to as being "directly on" another layer, there are no intervening layers present.

[0064] Embodiments of the present application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.

[0065] Some embodiments of the present application will be described in detail with reference to the drawings, which are shown by way of illustration. The following embodiments and features of the embodiments can be combined with each other, without conflict.

[0066] Referring to Figures 1 to 12 , the first aspect of the present application provides a method for manufacturing a printed circuit board 100, which includes steps S10-S80. It can be understood that the steps are numbered to clearly describe the specific manufacturing method, and are not limited to the order of the steps.

[0067] Step S10, referring to Figures 1 to 5 , a first substrate 10 is provided. The first substrate 10 can be manufactured by steps S11-S15.

[0068] As shown in FIG. 1, a metal layer 11 is provided in step S11. In the present embodiment, the metal layer 11 is a copper layer. In some embodiments, a carrier layer 12 can also be provided on the surface of the metal layer 11. The carrier layer 12 can be used to support the metal layer 11, and can be, but is not limited to, a peelable adhesive or the like. In some embodiments, the carrier layer 12 can also be omitted. Figure 1 As shown in FIG. 2, a plurality of electrical connection portions 13 and heat dissipation blocks 14 are provided on the surface of the metal layer 11 in step S12. Specifically, the electrical connection portions 13 and the heat dissipation blocks 14 can be provided on the surface of the metal layer 11 away from the carrier layer 12 by, but not limited to, electroplating. The electrical connection portions 13 and the heat dissipation blocks 14 can be made of copper. In the present embodiment, a plurality of electrical connection portions 13 can be provided at intervals between two heat dissipation blocks 14. The electrical connection portions 13 can be columnar, and the heat dissipation blocks 14 can be cuboid. The shapes of the electrical connection portions 13 and the heat dissipation blocks 14 are not limited in the present application.

[0069] Figure 2 The region of the metal layer 11 corresponding to the electrical connection portions 13 is a first region 111, the region of the metal layer 11 corresponding to the heat dissipation blocks 14 is a second region 112, the region between two adjacent first regions 111 and between the first region 111 and the second region 112 is a third region 113, and the remaining region is a fourth region 114. The correspondence means that the orthographic projections of the two regions can substantially overlap, or the orthographic projection area of one region can be slightly larger than that of the other region. For example, the (orthographic) area of the first region 111 can be larger than that of the electrical connection portions 13, and the ratio of the difference to the orthographic projection area of the electrical connection portions 13 is not greater than 5%. It should be understood that, depending on the actual situation, the ratio can also be adjusted to 10%, 15%, 20%, etc.

[0070] As shown in FIG. 3, a dielectric layer 15 is provided on the surface of the metal layer 11 away from the carrier layer 12 in step S13, and the dielectric layer 15 covers the surfaces of the third region 113 and the fourth region 114 away from the metal layer 11. That is, the surfaces of the metal layer 11 not covered by the heat dissipation blocks 14 or the electrical connection portions 13 are covered by the dielectric layer 15, and the gaps between the electrical connection portions 13 and the gaps between the electrical connection portions 13 and the heat dissipation blocks 14 are filled with the dielectric layer 15.

[0071] As shown in FIG. 4, the dielectric layer 15 can be formed on the surfaces of the electrical connection portions 13 and the heat dissipation blocks 14 when the dielectric layer 15 is provided. Therefore, the dielectric layer 15 needs to be ground to remove the dielectric layer 15 on the surfaces of the electrical connection portions 13 and the heat dissipation blocks 14, and to make the surface of the dielectric layer 15 flush with the surfaces of the electrical connection portions 13 and the heat dissipation blocks 14. Figure 3 The material of the dielectric layer 15 can be, but is not limited to, resin or the like.

[0072]

[0073] ​​like Figure 4 As shown, in step S14, an electroplating layer 16 may be provided on the surface of the dielectric layer 15 facing away from the metal layer 11 by electroplating. The electroplating layer 16 may cover the surface of the dielectric layer 15, the heat sink 14, and the electrical connection portion 13 facing away from the metal layer 11, and the electroplating layer 16 may be a copper layer.

[0074] like Figure 5 As shown, in step S15, the electroplated layer 16 is formed into an inner circuit layer 17, thereby obtaining the first substrate 10. Specifically, the inner circuit layer 17 can be formed by laminating, exposing, developing, etching, and stripping the electroplated layer 16. These steps are common techniques in the art and will not be described in detail here. It will be appreciated that after the inner circuit layer 17 is formed, the carrier layer 12 can be removed.

[0075] like Figure 5 As shown, the first substrate 10 includes a metal layer 11, a dielectric layer 15 disposed on the surface of the metal layer 11, an inner circuit layer 17 formed on the surface of the dielectric layer 15 facing away from the metal layer 11, and a plurality of electrical connections 13 and a heat sink 14 disposed in the dielectric layer 15. The inner circuit layer 17 is electrically connected to the electrical connections 13 but does not contact the heat sink 14 (copper block).

[0076] Step S20, see Figure 6 , a second substrate 20 is laminated onto the side of the first substrate 10 facing away from the metal layer 11. The second substrate 20 includes at least one conductive layer 21 and at least one insulating layer 22. Each insulating layer 22 is disposed between two adjacent conductive layers 21, and an insulating layer 22 is disposed between the first substrate 10 and a conductive layer 21. After lamination, the outermost portion of the second substrate 20 is the conductive layer 21, which is a copper foil layer. The conductive layer 21 located inside the outermost conductive layer 21 can be a pre-fabricated circuit layer (which can be formed by an image transfer and etching process using a copper foil layer).

[0077] In this embodiment, the second substrate 20 includes two conductive layers 21 and two insulating layers 22. In other embodiments, the number of conductive layers 21 and insulating layers 22 may be varied. The insulating layer 22 may be made of, but is not limited to, polyimide (PI), polyester (PET), polyethylene naphthalate diformic acid glycol ester (PEN), liquid crystal polymer (LCP), modified polyimide (MPI), and the like.

[0078] Step S30, seeFigure 7 In some embodiments, conductive holes 31 are provided in the first substrate 10 and the second substrate 20 to electrically connect the first substrate 10 and the second substrate 20 .

[0079] Specifically, such as Figure 7 As shown, through holes 30 can be formed in the first substrate 10 and the second substrate 20 by, but not limited to, mechanical drilling, laser drilling, or other methods. Through holes 30 extend through the first substrate 10 and the second substrate 20 along the thickness direction. The number of through holes 30 can be one or more, and this application does not impose any limitation. In this embodiment, there are two through holes 30.

[0080] Then, copper can be deposited on the inner wall of the through-hole 30 by electroplating to form a conductive via 31. The conductive via 31 electrically connects the first substrate 10 and the second substrate 20. It will be appreciated that when copper is electroplated in the through-hole 30, a metal layer 40 is plated on the outer surface of the outermost conductive layer 21 (copper foil layer) of the second substrate 20, and a metal layer 41 is plated on the outer surface of the outermost metal layer 11 of the first substrate 10. The metal layers 40 and 41 can be thin copper layers.

[0081] Step S40, see Figure 8 , reducing the thickness of the third region 113.

[0082] Specifically, a resist film (not shown) can be applied to the outer side of the outermost metal layer 11 (or metal layer 41, if present) of the first substrate 10 to prevent etching of the copper metal. The resist film exposes the third region 113 to be thinned (or, if present, the metal layer 41 corresponding to the third region 113). The substrate is then sprayed with an etching solution or immersed in the entire substrate. The resist film and etching solution can be conventional or unconventional in the art and are not limited in this application. The etching solution can be an acidic copper chloride etching solution, and the components and contents of the acidic copper chloride etching solution can be: copper chloride 130-180g / L, hydrochloric acid (concentration is 30%-38%) 120-200g / L, oxidant (can be sodium hypochlorite) 120-250g / L, industrial salt (can be sodium chloride or ammonium chloride) 150-250g / L, stabilizer (can be urea or thiourea) 0.5-15g / L, accelerator (can be potassium chloride) 5-30g / L, buffer (can be sodium hydroxide) 0.05-0.2g / L, and the rest is water.

[0083] After etching, the thickness of the third region 113 may be only 20% to 25% of the initial thickness.

[0084] Step S50, see Figure 9The thickness of the second region 112 and the first region 111 can be thinned by using an acidic copper chloride etching solution, and the thinned third region 113 can be continuously etched until the metal layer of the third region 113 is completely etched (part of the surface of the dielectric layer 15 is exposed). The thinned first region 111 forms a pad 1111 connected to the electrical connection 13. It can be understood that the metal layer 41 on the surface of the first region 111 and the second region 112 is also etched, and the surface of the thinned second region 112 and the thinned first region 111 (i.e. the pad 1111) is exposed.

[0085] Step S60, please refer to Figure 10 The fourth region 114 is made to form the first outer layer circuit layer 18, and the outermost conductive layer 21 of the second substrate 20 is made to form the second outer layer circuit layer 23. It can be understood that if the fourth region 114 has a metal layer 41 on its outer surface, the metal layer of the fourth region 114 and the metal layer 41 will jointly form the first outer layer circuit layer 18; if the outermost conductive layer 21 has a metal layer 40 on its outer surface, the outermost conductive layer 21 and the metal layer 40 will jointly form the second outer layer circuit layer 23.

[0086] Step S70, please refer to Figure 11 A protective layer 50 can also be provided outside the first outer layer circuit layer 18 and the second outer layer circuit layer 23. The protective layer 50 covers the outer surface of the first outer layer circuit layer 18 and the second outer layer circuit layer 23, and can fill the gaps of the first outer layer circuit layer 18 and the second outer layer circuit layer 23, and can also fill into the conductive hole 31. In this embodiment, the protective layer 50 is a solder mask.

[0087] Step S80, please refer to Figure 12 The pad 1111 and the thinned second region 112 can also be surface treated. For example, an oxidation resistant (OSP) treatment can be performed, or a gold layer 60, a tin layer, etc. can be formed on the surface of the pad 1111 and the thinned second region 112.

[0088] Please refer to Figure 12 The second aspect of the present application provides a printed circuit board 100, which comprises a first substrate 10 and a second substrate 20 electrically connected.

[0089] The first substrate 10 comprises a dielectric layer 15, an inner layer circuit layer 17 formed on one surface of the dielectric layer 15, a solder pad 1111 and a first outer layer circuit layer 18 formed on another surface of the dielectric layer 15, an electrical connection portion 13 and a heat dissipation block 14 disposed in the dielectric layer 15. The electrical connection portion 13 electrically connects the inner layer circuit layer 17 and the solder pad 1111. The heat dissipation block 14 is disposed close to the electrical connection portion 13 and the solder pad 1111, and the surface of the heat dissipation block 14 further has a metal layer 11 (i.e. a second region 112) which is not etched. The solder pad 1111 is exposed from the first outer layer circuit layer 18 and the second region 112, and the surface of the solder pad 1111 is lower than the surface of the first outer layer circuit layer 18.

[0090] The second substrate 20 comprises at least one conductive circuit layer 24 and at least one insulating layer 22, and each insulating layer 22 is disposed between two adjacent conductive circuit layers 24. One insulating layer 22 is disposed between the first substrate 10 and one of the conductive circuit layers 24, and the outermost conductive circuit layer 24 is a second outer layer circuit layer 23. The first substrate 10 and the second substrate 20 can be electrically connected through a conductive hole 31.

[0091] In some embodiments, the diameter of the solder pad 1111 is 0.1mm-0.2mm, and the distance between two adjacent solder pads 1111 (i.e. the straight line distance between the two closest points between two adjacent solder pads) is 0.1mm-0.2mm.

[0092] Please refer to Figure 13 The third aspect of the present application provides a circuit board assembly 1000 comprising an electronic component 200 and a printed circuit board 100, and the electronic component 200 is electrically connected to the solder pad 1111 of the printed circuit board 100.

[0093] In some embodiments, the electronic component 200 is soldered to the solder pad 1111 through a ball grid array 201 (BGA), so as to realize the electrical connection between the electronic component 200 and the printed circuit board 100. The electronic component 200 can be but is not limited to a resistor, a capacitor, an inductor, a chip, etc.

[0094] In some embodiments, as Figure 14 shown, the gap between the electronic component 200 and the printed circuit board 100 can be filled with an adhesive layer 202 to improve the structural stability and soldering reliability.

[0095] The application can make small-pitch pads 1111 by setting the electric connection part 13 on the metal layer 11 and selectively reducing the copper of the metal layer 11, thereby reducing the horizontal size of the welding area of the electronic component and the printed circuit board 100. Moreover, the application forms the surface height difference (the surface of the pad 1111 is lower than the surface of the first outer layer circuit layer 18) by multiple selective reduction of the copper, the pad 1111 is in the concave structure, thereby reducing the welding packaging height of the printed circuit board 100 and the electronic component, and reducing the vertical size. In addition, the heat dissipation block 14 (thick copper area) is arranged near the pad 1111 and the heat dissipation block 14 is connected to the surface of the printed circuit board 100 through the unetched metal layer 11, thereby forming the heat dissipation channel of the electronic component, accelerating the heat dissipation, and improving the heat dissipation performance.

[0096] The above description is some specific embodiments of the application, but in the actual application process, it cannot be limited to these embodiments only. Other modifications and changes made by the person skilled in the art according to the technical concept of the application should belong to the protection scope of the application.

Claims

1. A method for preparing a printed circuit board, characterized in that: The steps include: A first substrate is provided, comprising a metal layer, a dielectric layer disposed on a surface of the metal layer, an inner circuit layer formed on a surface of the dielectric layer facing away from the metal layer, a plurality of electrical connections and a heat sink disposed in the dielectric layer, wherein the inner circuit layer is electrically connected to the electrical connections; the metal layer comprises a first region, a second region, a third region, and a fourth region, wherein the first region corresponds to the electrical connection, the second region corresponds to the heat sink, the third region is located between adjacent first regions and between the first and second regions, and the fourth region is the region of the metal layer other than the first, second, and third regions; Laminating a second substrate on a side of the first substrate facing away from the metal layer, wherein the second substrate comprises at least one conductive layer and at least one insulating layer, each insulating layer being disposed between two adjacent conductive layers, and an insulating layer being disposed between the first substrate and one of the conductive layers; reducing the thickness of the third region; thinning the second region and the first region, and removing the thinned third region, so that the thinned first region forms a pad connected to the electrical connection portion; The fourth area is made into a first outer circuit layer, and the outermost conductive layer of the second substrate is made into a second outer circuit layer.

2. The preparation method according to claim 1, wherein The preparation method further includes the following steps: providing protective layers on the outer sides of the first outer circuit layer and the second outer circuit layer respectively.

3. The preparation method according to claim 2, wherein The preparation method further includes the following step: performing surface treatment on the pad and the second thinned region.

4. The preparation method according to claim 1, wherein Before “reducing the thickness of the third region”, the preparation method further includes the following step: providing conductive holes in the first substrate and the second substrate to electrically connect the first substrate and the second substrate.

5. The preparation method according to claim 1, wherein The method for preparing the first substrate comprises the following steps: Providing a metal layer, and arranging a plurality of the electrical connection parts and the heat dissipation blocks on the surface of the metal layer; Disposing the dielectric layer on the surface of the metal layer, wherein the dielectric layer covers the surfaces of the third region and the fourth region facing away from the metal layer; Disposing an electroplating layer on a surface of the dielectric layer facing away from the metal layer; The electroplating layer is made into an inner circuit layer, and the inner circuit layer is electrically connected to the electrical connection portion to obtain the first substrate.

6. The preparation method according to claim 5, wherein Before the step of providing a plurality of the electrical connection parts and the heat dissipation blocks, the method further includes: providing a carrier layer on the surface of the metal layer; Wherein, the plurality of electrical connection parts and heat dissipation blocks are arranged on a surface of the metal layer facing away from the carrier layer.

7. The preparation method according to claim 6, wherein After the step of forming the inner circuit layer with the electroplating layer, the method further includes: removing the carrier layer.

8. A printed circuit board manufactured by the method for manufacturing a printed circuit board according to claim 1, characterized in that: include: A first substrate comprises a dielectric layer, an inner circuit layer formed on one surface of the dielectric layer, a solder pad and a first outer circuit layer formed on the other surface of the dielectric layer, an electrical connection portion and a heat sink disposed in the dielectric layer; the electrical connection portion electrically connects the inner circuit layer and the solder pad; and The second substrate is electrically connected to the first substrate. The second substrate includes at least one conductive circuit layer and at least one insulating layer. Each insulating layer is arranged between two adjacent conductive circuit layers. One insulating layer is arranged between the first substrate and one conductive circuit layer. The outermost conductive circuit layer is the second outer circuit layer.

9. The printed circuit board according to claim 8, wherein The diameter of the pad is 0.1 mm to 0.2 mm, and the distance between two adjacent pads is 0.1 mm to 0.2 mm.

10. A circuit board assembly, characterized in that: The printed circuit board comprises an electronic component and the printed circuit board according to claim 8 or 9, wherein the electronic component is electrically connected to the pad.

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