Direct memory access circuits and integrated circuits

Abstract

The present application provides a direct memory access circuit and an integrated circuit, and relates to the field of integrated circuits. The direct memory access circuit is used in an integrated circuit, and the integrated circuit includes a memory, a system bus, and a direct memory access circuit. The direct memory access circuit reads a target image in the memory through the system bus, and the space occupied by any pixel in the target image is smaller than the width of the system bus. The direct memory access circuit includes: an input optimization module, which is configured to receive the target image, rearrange the target image into a first type of data in units of pixels, and output the first type of data to an input cache module so that the first type of data matches the storage mode of the input cache module; an input cache module, which is configured to receive and store the first type of data, and the storage mode of the input cache module matches the width of the system bus. By setting the modules in the direct memory access circuit, the image data processing efficiency in the integrated circuit can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a direct memory access circuit and an integrated circuit. Background Art

[0002] Direct memory access (DMA) is a feature in computer systems that allows certain hardware subsystems to access system memory directly without intervention from the central processing unit (CPU). Direct memory access circuits can be set up specifically for image processing types and are widely used in various integrated circuit applications.

[0003] Since the width of the integrated circuit's system bus is not completely consistent with the size of the storage space occupied by each pixel in the target image, there are inefficiencies in the image data reading and subsequent processing, such as a large number of invalid bits being used to fill the image data so that the image data meets specific format requirements. Therefore, how to improve the efficiency of image data processing in integrated circuits is an urgent problem to be solved. Summary of the invention

[0004] In view of this, the present application discloses a direct memory access circuit and an integrated circuit to improve the image data processing efficiency in the integrated circuit.

[0005] In a first aspect, the present application discloses a direct memory access circuit for an integrated circuit, the integrated circuit comprising a memory, a system bus and a direct memory access circuit, the direct memory access circuit reading a target image in the memory through the system bus, the space occupied by any pixel in the target image being smaller than the width of the system bus, the direct memory access circuit comprising: an input optimization module configured to receive the target image, rearrange the target image into first-category data in units of pixels, and output the first-category data to an input cache module so that the first-category data matches a storage mode of the input cache module; an input cache module configured to receive and store the first-category data, the storage mode of the input cache module matching the width of the system bus.

[0006] Optionally, the target image has a first layer and a second layer, the first type of data includes first data and second data, and the input cache module includes a first input cache module and a second input cache module; the input optimization module is configured to receive the first layer and the second layer of the target image, respectively, and rearrange the first layer of the target image into the first data, rearrange the second layer of the target image into the second data, output the first data to the first input cache module, and output the second data to the second input cache module.

[0007] Optionally, the direct memory access circuit also includes a mixing module; the mixing module includes a first input terminal and a second input terminal, the first input terminal receives first data or converted data of the first data, the second input terminal receives second data or converted data of the second data, and the output terminal of the mixing module outputs mixed third data; the mixing module performs weighted mixing based on each color channel value and transparency value in the data received by the first input terminal and the second input terminal to determine the third data.

[0008] Optionally, the conversion data of the first data and the conversion data of the second data satisfy a preset data format; when the first input end of the mixing module receives the conversion data of the first data and the second input end receives the conversion data of the second data, the mixing module determines the third data according to the following calculation formula:

[0009] ,

[0010] ,

[0011] ,

[0012] in, is the transparency value of the converted data of the first data, is the transparency value of the converted data of the second data, for and The modulation value of is the transparency value of the third data, Any color channel value of the converted data of the first data, Any color channel value of the converted data of the second data, is any color channel value of the third data, , and Represents the same color channel value.

[0013] Optionally, the preset data format matches the width of the system bus, and the color channel value includes a red channel value, a green channel value, and a blue channel value.

[0014] Optionally, the mixing module includes a first divider and a second divider; the first divider is configured to process a division with a divisor of 255, and the calculation formula is as follows:

[0015] ,

[0016] in, is the dividend;

[0017] The second divider is a general divider configured to process the division operation in the mixing module that is not processed by the first divider.

[0018] Optionally, the quotient calculated by the first divider and the second divider may be rounded down.

[0019] Optionally, the direct memory access circuit also includes an input data processing module; the input data processing module is arranged between the input cache module and the mixing module, and is configured to convert the first data into conversion data of the first data, and convert the second data into conversion data of the second data, so that the conversion data of the first data and the conversion data of the second data meet a preset data format.

[0020] Optionally, the direct memory access circuit also includes a first output data processing module, an output optimization module, an output cache module and a second output data processing module; the first output data processing module is configured to receive third data and process the third data into fourth data, the third data meets a preset data format, and the fourth data does not meet the preset data format; the output optimization module is configured to receive the fourth data, rearrange the fourth data into second-category data in units of pixels, and output the second-category data to the output cache module so that the second-category data matches a storage mode of the output cache module; the output cache module is configured to receive and store the second-category data, and the storage mode of the output cache module matches the width of the system bus; the second output data processing module is configured to read the second-category data and convert the data format of the second-category data into a target data format.

[0021] Optionally, the input optimization module determines, based on the data format of the target image, that the space size occupied by any pixel in the target image is a first space value, and the first space value is smaller than the width of the system bus; the input optimization module reads the target image row by row, and determines, based on the offset between the starting address of each row of the target image and the alignment address, whether the starting data of each row of the target image is rearranged, and the alignment address matches the width of the system bus; the input optimization module determines, based on the first space value and the number of pixels in each row of the target image, whether the ending data of each row of the target image is rearranged.

[0022] In a second aspect, the present application further discloses an integrated circuit, comprising the direct memory access circuit disclosed in the first aspect above.

[0023] The direct memory access circuit and integrated circuit disclosed in the present application have at least the following beneficial effects:

[0024] (1) Through the design of direct memory access circuit, the number of pipeline processing steps is reduced, and the processing efficiency of image data is increased, which is especially suitable for scenarios when the image data format is inconsistent with the system bus width;

[0025] (2) In the process of bus data acquisition, data format conversion and bus data output, common image formats are split and spliced ​​for optimization to avoid a large amount of invalid data and affect cache efficiency;

[0026] (3) By optimizing the transaction processing logic of the divider in the hybrid module, not only the division operation time is greatly saved, but also the area occupied by the divider in the integrated circuit is greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The following is a brief introduction to the drawings used in describing the embodiments of the present application:

[0028] Figure 1 It is a structural schematic diagram of the storage method of image data in a memory in the prior art.

[0029] Figure 2 It is a schematic diagram of the structure of an integrated circuit provided in an embodiment of the present application.

[0030] Figure 3 It is a schematic diagram of an input optimization module provided in an embodiment of the present application.

[0031] Figure 4 It is a structural diagram of a direct memory access circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the specific implementation methods of the present application will be described below with reference to the accompanying drawings. The accompanying drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other accompanying drawings and other implementation methods can be obtained based on these drawings without creative work. Adjustments and improvements made without departing from the concept of the present application are all within the scope of protection of the present application.

[0033] In order to simplify the drawings, only the parts related to the corresponding embodiments are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, only part of the components with the same structure or function in some figures are schematically drawn, and there may be more or fewer components with the same structure or function in reality.

[0034] In this application, unless otherwise clearly specified and limited, ordinal numbers, such as "first", "second", etc., are only used to distinguish and describe associated objects, and cannot be understood as indicating or implying the relative importance or order between associated objects; in addition, they do not represent the number of associated objects. "Multiple" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between associated objects, which indicates the "or" relationship between associated objects. "And / or" is used to describe the relationship between associated objects, which includes any combination relationship between associated objects, such as "a and / or b" includes: "alone a", "alone b", or "a and b". "One or more" or "at least one" in multiple objects refers to any object or any combination of multiple objects, such as "one or more of a1, a2, a3" or "at least one of a1, a2, a3" includes: "alone a1", "alone a2", "alone a3", "a1 and a2", "a1 and a3", "a2 and a3", or "a1, a2 and a3".

[0035] Indexed color mode and direct color mode are two common ways to represent image colors. Among them, indexed color mode uses a color lookup table (CLUT) to manage the colors in the image. The color lookup table can also be called a palette. Each pixel in the image does not store the actual color value, but an index pointing to a specific color in the palette. The palette is a limited set of colors, for example, it can contain 256 colors (corresponding to an 8-bit index length), and each color has a unique index in the palette (from 0 to 255). The value of each pixel is an index number, not direct color data. The index points to a color in the palette, and the actual color of the image is determined by looking up the table. Image data formats that can use indexed color mode include L8, AL44, AL88, and L4. In contrast, direct color mode does not use a palette, and each pixel directly stores the actual value of the color. Color can be composed of multiple channels, such as red (R), green (G), and blue (B). Each pixel contains the actual color value, represented by several bytes. Image data formats that can use direct color mode include ARGB8888, RGB888, RGB565, ARGB1555, ARGB4444, A4, and A8. In the above data formats, except for ARGB8888, which means that the storage space occupied by each pixel is 32 bits, the storage space occupied by each pixel in other data formats is less than 32 bits (such as 4 bits, 8 bits, 16 bits, or 24 bits).

[0036] Please refer to Figure 1, which is a schematic diagram of the structure of the storage method of image data in the memory in the prior art. Figure 1 As shown, each grid in the figure is the address where a pixel is stored. The image pixels present a matrix style in the continuous memory address, with the characteristics of rows and columns. The fixed address between rows is called the row spacing, such as the grids corresponding to 18-21, 28-31 or 38-41 in the figure. Each pixel in the image is stored in the grids corresponding to 12-17, 22-27, 32-27 and 42-47 in sequence, and the overall arrangement is 4 rows and 6 columns. The traditional data reading method cannot skip invalid row spacing addresses during continuous reading at the hardware level. For example, in the row-by-row reading method, when reading an image stored in the memory, the reading order is: 0-9, 10-19, 20-29, 30-39, 40-49, 50-59. In this way, a large number of invalid bits will be read, such as the row spacing addresses mentioned above. This may cause the processor to be occupied for a long time, and the processor includes, for example, a central processing unit. If the processor is configured to read directly according to the specified address, it will take up more processor computing time, causing the rest of the program to fail to execute normally. Therefore, when faced with a large number of invalid bits in the data, the reading method in the prior art may not be able to achieve efficient data reading, resulting in a decrease in the overall work efficiency of the system.

[0037] With the advancement of science and technology in modern society, people's requirements for image processing are also increasing. In traditional integrated circuits, the way to process images is to use the CPU in conjunction with software to convert and move image data. As more and more electronic devices have added clear color screens to display information, the traditional image processing method of CPU in conjunction with software has gradually fallen behind the human requirements for image processing speed. In an integrated circuit, there is a system bus for data transmission and communication between various sub-circuits in the integrated circuit. The width of the system bus is the number of data bits that can be transmitted simultaneously on the bus. The width of the system bus can be, for example, 32bit, 64bit or 128bit. In this application, the common 32bit bus width is used as an example for explanation; since other types of buses are not involved, the system bus of the integrated circuit mentioned in this application can be referred to as a bus.

[0038] For a 32-bit bus, this means that the bus can transmit 32 bits of data, that is, 4 bytes of data, in one clock cycle. However, after the traditional image DMA class design obtains non-32-bit image data from the bus, it will generate a corresponding number of invalid data, or padding data, according to the image data format to meet the format requirements of the bus. For example, taking the common RGB888 format image data as an example, the storage space size of each pixel in the target image is 24 bits, that is, the red, green and blue channels each occupy 8 bits, and the selection of each channel is 2 to the 8th power, that is, 0-255. At this time, in order to meet the format requirements of the 32-bit bus, the system will add an additional 8 bits of invalid data on the basis of the original 24 bits, and then store all valid data (24 bits) and invalid data (8 bits) in the input cache. The actual utilization rate of the input cache is low; in the pipeline process of processing data, due to the existence of a large amount of invalid data, the data utilization rate is always low. When processing the same amount of data, more cache reads and writes are required, and the actual utilization rate of the input and output caches is low. Similarly, when outputting image data in a non-32-bit format to the bus, a large amount of invalid data is generated after the image format is standardized, which also affects the utilization rate of the output buffer. It is understandable that when the format of the target image is less than 32 bits and is not the RGB888 format mentioned in the above example, those skilled in the art can also infer the processing method of images in other data formats based on this application document.

[0039] In addition, since the DMA circuit that processes image data has operations such as image format conversion and mixing, and the pipeline level is long, when reading data continuously from the bus, the input data will accumulate in the input buffer and cannot be processed in time. The maximum amount of valid data that can be stored in the input buffer becomes one of the bottlenecks of the overall data conversion and transmission efficiency.

[0040] The traditional approach is to increase the capacity of the input cache, which can indeed solve the overall data transmission efficiency problem when continuously reading bus data to a certain extent, but it will also bring about a large chip area overhead. In addition, in non-extreme cases, the utilization rate of the large-capacity input cache cannot be guaranteed, resulting in a certain amount of waste. Therefore, relatively speaking, it is more meaningful to explore how to increase the maximum storage capacity of valid data without changing the input cache capacity.

[0041] Please refer to Figure 2 , which shows a schematic diagram of the structure of an integrated circuit provided by an embodiment of the present application. Figure 2As shown, the integrated circuit 20 includes a memory 210, a system bus 220 and a direct memory access circuit 230. The direct memory access circuit 230 is used for the integrated circuit 20. The direct memory access circuit 230 reads a target image in the memory 210 through the system bus 220. The space occupied by any pixel in the target image is smaller than the width of the system bus 220. The direct memory access circuit 230 includes:

[0042] The input optimization module 231 is configured to receive a target image, rearrange the target image into first-type data in units of pixels, and output the first-type data to the input buffer module 232 so that the first-type data matches a storage mode of the input buffer module 232;

[0043] The input buffer module 232 is configured to receive and store the first type of data. The storage mode of the input buffer module 232 matches the width of the system bus 220 .

[0044] Exemplarily, all cache modules in the present application (including the input cache module 232) can be first in first out (FIFO) type caches, which is a cache mechanism that processes and removes data in the order in which the elements enter. Its basic principle is "first come, first served", that is, the data that first enters the cache is processed or removed first.

[0045] Referring to the above content, taking the width of the system bus 220 as 32 bits as an example, the data format of the target image can be RGB888, RGB565, ARGB1555, ARGB4444, A4, A8, L8, AL44, AL88 or L4. The above data formats satisfy that the space occupied by any pixel in the target image is smaller than the width of the system bus 220. The storage mode of the input buffer module 232 matches the width of the system bus 220, that is, the size of each cache unit in the input buffer module 232 is equal to the width of the system bus 220, both of which are 32 bits. Since the space occupied by any pixel in the target image is smaller than the width of the system bus 220, a certain amount of invalid data will be generated when the system bus 220 reads data. The input optimization module 231 optimizes the data read from the system bus 220, that is, rearranges the data into the first type of data in units of pixels, so that the first type of data can match the storage mode of the input buffer module 232.

[0046] In the prior art, since the target data read by the bus includes invalid data, after the target data is stored in the cache module, some of the cache units (especially the cache units at the head and the cache units at the tail) may contain invalid data, resulting in low cache utilization. This situation can be called the target data does not match the storage mode of the cache module. Similarly, if after the target data is stored in the cache module, there is no invalid data in the cache unit, that is, all data is valid data, this situation can be called the target data matches the storage mode of the cache module.

[0047] The input optimization module 231 in the present application removes invalid data from the target data corresponding to the target image, and rearranges the target data into the first type of data in units of pixels: the target data is cropped and spliced ​​to optimize its data storage format. Through the design of the direct memory access circuit, the number of pipeline processing steps is reduced, and the processing efficiency of the image data is increased, which is particularly suitable for the scenario when the image data format is inconsistent with the system bus width.

[0048] In some embodiments of the present application, the input optimization module 231 determines the space size occupied by any pixel in the target image as a first space value based on the data format of the target image, and the first space value is smaller than the width of the system bus 220;

[0049] The input optimization module 231 reads the target image row by row, and determines whether the starting data of each row of the target image should be rearranged according to the offset between the starting address of each row of the target image and the alignment address, wherein the alignment address matches the width of the system bus 220;

[0050] The input optimization module 231 determines whether the end data of each row of the target image is to be rearranged according to the first spatial value and the number of pixels of each row of the target image.

[0051] Please refer to Figure 3 , which shows a schematic diagram of an input optimization module provided by an embodiment of the present application. Figure 3As shown, each square represents the size of a byte, that is, 8 bits; dark squares represent invalid data, light squares represent valid data, and colorless squares represent no data (or the corresponding cache unit is empty). The address of the memory is 0x0 to 0xF. The cache diagram on the lower left shows the internal situation of the cache module in the prior art, and the cache diagram on the lower right shows the internal situation of the cache module after optimization in this application. The width of the system bus is 32 bits, and the storage size of each cache unit in the cache module is also 32 bits. Valid data can be, for example, a target image in RGB888 data format, where one pixel corresponds to three light squares, that is, 24 bits. When in the memory, some invalid data already exists to fill the vacant memory addresses, namely addresses 0x0, 0xD, 0xE, and 0xF. For the prior art, it reads 32 bits (i.e., four squares) of data each time according to the order of addresses from small to large, and stores it in the corresponding cache unit. Thus, there will be corresponding invalid data at the starting position of the first cache unit (where there are 8 bits of invalid data) and at the ending position of the fourth cache unit (where there are 24 bits of invalid data). The presence of these invalid data will reduce the read and write efficiency of the cache.

[0052] In the present application, after cropping and splicing by the input optimization module 231, all invalid data is removed and then placed in three 32-bit cache units, which saves one 32-bit cache unit compared to the storage method of the traditional cache. The input optimization module 231 first determines the space size occupied by any pixel in the target image as the first space value based on the data format of the target image, and the first space value is less than the width of the system bus 220. In the above example, the first space value is 24 bits, which is less than the line width of the system bus 32 bits. Subsequently, the input optimization module 231 reads the target image row by row, and determines whether the starting data of each row of the target image is rearranged based on the starting address of each row of the target image and the offset of the alignment address, wherein the alignment address matches the width of the system bus 220. For example, if the starting address is 0x5, the offset relative to the 32-bit alignment address 0x3 is 0x2. In the above example, the starting address is 0x1, and the offset relative to the alignment address 0x0 is 0x1, so the starting data of the target image is rearranged, that is, the data of the first byte is identified as invalid data, which is cropped and discarded. Finally, the input optimization module 231 determines whether the end data of each row of the target image is rearranged according to the first spatial value and the number of pixels of each row of the target image. In the above example, the first spatial value is 24 bits, and the number of pixels of each row of the target image is 4. The valid data of the first row in the memory is 24*4=96 bits in total, and the storage space of this row in the memory is 16*8=128 bits in total. Counting the 8 bits of invalid data cropped at the starting position, there will be 128-96-8=24 bits of invalid data at the end data of the row of the target image. The end data of the target image is rearranged, that is, the data of the last 3 bytes is identified as invalid data, which is cropped and discarded. For the remaining valid data, for the first-in-first-out cache module, on the basis of maintaining its original order, the address is moved forward by 8 bits in sequence for re-splicing. When storing in the cache module, the cache units located in the front order store valid data, while the last cache unit does not store any data and is in an idle state, which can be used to store the image data of the next line. In this way, through cropping and splicing, all invalid data in the target data is discarded, which improves the utilization rate of the cache module.

[0053] Please refer to Figure 4 , which shows a schematic diagram of the structure of a direct memory access circuit provided by an embodiment of the present application. Figure 4As shown, the target image has a first layer and a second layer, the first type of data includes first data and second data, and the input cache module 420 includes a first input cache module 421 and a second input cache module 422; the input optimization module 410 is configured to receive the first layer and the second layer of the target image respectively, and rearrange the first layer of the target image into the first data, rearrange the second layer of the target image into the second data, output the first data to the first input cache module 421, and output the second data to the second input cache module 422.

[0054] Exemplarily, the first layer of the target image may be a foreground layer, and the second layer of the target image may be a background layer. The foreground layer is the portion of the image that contains the main object or area of ​​interest. It is the portion that the user's eyes focus on first and is also the area of ​​the image that has the main meaning. The object in the foreground layer may be the protagonist in the image, such as a person, object, or other important element. The foreground is usually clearer and more vivid than the background, and has a stronger color contrast. In image processing, the foreground can be extracted for further processing, such as object recognition, target tracking, and cutout. The background layer is the portion of the image that contains the environment or secondary information, which is located behind the foreground and is not the main object of the user's attention. The background layer may contain the environment, scene, or space in the image, and the colors and details may be blurred or monotonous. The background layer can provide context for the foreground, but it will not attract much attention. The background will be separated or blurred in image processing to highlight the foreground object. In addition, in some cases, the background may be replaced or edited to change the overall feeling of the image.

[0055] In some image processing applications, splitting the foreground layer and background layer of the target image and processing them separately can help improve processing efficiency. By processing the foreground and background separately, the processor can focus on important image areas and reduce unnecessary computational burden. For example, in image encoding, the foreground may be the only part that requires high-quality processing, while the background can be processed with a lower resolution or frame rate. Moreover, after splitting the foreground and background, they can be assigned to different processing units or threads for parallel processing, further improving processing speed and efficiency. In addition, after separating the foreground and background, different processing operations can be performed on them separately, such as color correction, brightness adjustment, sharpening, etc.; this makes the foreground object more prominent, while blur or hue can be used to adjust the background processing to create a more attractive visual effect. In film and television production or photography, by splitting the foreground and background, the background can be easily replaced, such as removing the characters from the original scene and placing them in a virtual scene. In addition, after separating the foreground and background, the position, transparency and effect of each layer can be flexibly adjusted when the image is synthesized. For example, in image design, the background color can be easily changed or different textures can be added without affecting the main object in the foreground.

[0056] Please continue to refer to Figure 4 The direct memory access circuit 400 also includes a mixing module 440; the mixing module 440 includes a first input terminal and a second input terminal, the first input terminal receives the first data or the conversion data of the first data, the second input terminal receives the second data or the conversion data of the second data, and the output terminal of the mixing module 440 outputs the mixed third data; the mixing module 440 performs weighted mixing based on the respective color channel values ​​and transparency values ​​in the data received by the first input terminal and the second input terminal to determine the third data.

[0057] After the data is split into a foreground layer and a background layer, the two can be remixed into unified data through a mixing module 440. For example, in an application scenario of photo processing (such as an ID photo), the foreground layer can be a portrait, and the background layer can be a pure white background; after adjusting the facial features of the portrait in the foreground layer, the background layer can also be replaced with a pure blue background, and then the data of the foreground layer and the background layer are weighted and mixed based on the color channel values ​​and transparency values ​​therein to obtain the modified photo. By referring to the color channel values ​​and transparency values ​​at the same time, the effect of data mixing can be better. The working principle of the mixing module 440 can refer to the following embodiments.

[0058] In some embodiments of the present application, the direct memory access circuit 400 also includes an input data processing module 430; the input data processing module 430 is arranged between the input cache module 420 and the mixing module 440, and is configured to convert the first data into conversion data of the first data, and convert the second data into conversion data of the second data, so that the conversion data of the first data and the conversion data of the second data meet the preset data format.

[0059] The input data processing module 430 can process the image data of the foreground layer and the background layer respectively, and process the image details. At the same time, the input data processing module 430 also plays the role of the same data format. According to the above embodiments, the data format of the first data and the second data obtained after rearrangement is no different from that before the rearrangement, and only the storage address of the pixel is changed. Therefore, the data format of the first data and the second data is still RGB888. In order to obtain a better mixing effect, the preset data format can be set to ARGB8888, that is, the parameter of increasing transparency. In this way, the input data processing module 430 makes the data format of the conversion data of the first data and the conversion data of the second data both ARGB8888; moreover, such a preset data format matches the width of the system bus.

[0060] In addition, the input data processing module 430 can also divide the continuous data in the cache into "single" data according to the data format. For example, if the cache stores continuous 8-bit image format data, the preprocessing can split the 32-bit data in a cache into 4 8-bit data for subsequent data processing.

[0061] In some embodiments of the present application, the conversion data of the first data and the conversion data of the second data satisfy a preset data format; when the first input end of the mixing module 440 receives the conversion data of the first data and the second input end receives the conversion data of the second data, the mixing module 440 determines the third data according to the following calculation formula:

[0062] ,

[0063] ,

[0064] ,

[0065] in, is the transparency value of the converted data of the first data, is the transparency value of the converted data of the second data, for and The modulation value of is the transparency value of the third data, Any color channel value of the converted data of the first data, Any color channel value of the converted data of the second data, is any color channel value of the third data, , and Represents the same color channel value. The color channel value includes the red channel value, the green channel value, and the blue channel value.

[0066] Weighted mixing of the RGB values ​​and transparency values ​​in the foreground and background layers can bring richer visual effects, enhance the realism of the image, and improve the flexibility of image synthesis. By optimizing the transparency effect, enhancing color balance and visual transition, the quality of image processing and user experience can be greatly improved.

[0067] In some embodiments of the present application, the mixing module 440 includes a first divider and a second divider; the first divider is configured to process a division with a divisor of 255, and the calculation formula is as follows:

[0068] ,

[0069] in, is the dividend;

[0070] The second divider is a general divider configured to process the division operation not processed by the first divider in the mixing module 440. The quotient calculated by the first divider and the second divider may be rounded down.

[0071] For formulas where the divisor is a variable, this application uses a complete divider logic to avoid indeterminate results caused by the divisor being 0 or being indeterminate. For formulas where the divisor is fixed to 255, if a complete divider is also used, the logic will be bloated and the divider timing will not meet the high-speed timing requirements. This application uses an approximate optimization algorithm for integer division by 255, which not only greatly saves the division operation time, but also greatly reduces the area occupied by the divider. According to calculation verification, the error ratio caused by the approximate algorithm is extremely small, which is completely within an acceptable range and can meet the accuracy required by the subsequent algorithm.

[0072] By optimizing the transaction processing logic of the divider in the hybrid module 440, that is, setting different types of dividers for different processing situations, not only the division operation time is greatly saved, but also the area occupied by the divider in the integrated circuit is greatly reduced.

[0073] In some embodiments of this application, please continue to refer to Figure 4The direct memory access circuit 400 also includes a first output data processing module 450, an output optimization module 460, an output cache module 470 and a second output data processing module 480; the first output data processing module 450 is configured to receive the third data and process the third data into fourth data, the third data meets the preset data format, and the fourth data does not meet the preset data format; the output optimization module 460 is configured to receive the fourth data, rearrange the fourth data into second-category data in units of pixels, and output the second-category data to the output cache module 470 so that the second-category data matches the storage mode of the output cache module 470; the output cache module 470 is configured to receive and store the second-category data, and the storage mode of the output cache module 470 matches the width of the system bus; the second output data processing module 480 is configured to read the second-category data and convert the data format of the second-category data into the target data format.

[0074] Among them, the first output data processing module 450 is configured to receive the third data and process the third data into the fourth data. The third data is the output data of the mixing module 440, which meets the preset data format, i.e., ARGB8888; however, the storage space occupied by the data format of ARGB8888 is large, and users tend to choose the more commonly used data format of RGB888. In most cases, the effect presented by the image data of RGB888 is sufficient to meet the needs of users. Therefore, the first output data processing module 450 can be used to process the received third data in the data format of ARGB8888 into the fourth data in the data format of RGB888 to meet the needs of users. The output optimization module 460 is configured to receive the fourth data, rearrange the fourth data into the second type of data in units of pixels, and output the second type of data to the output buffer module 470 so that the second type of data matches the storage mode of the output buffer module 470. The setting of the output buffer module 470 can refer to the setting of the above input buffer module 420, that is, the size of each buffer unit is 32 bits, which matches the width of the system bus. Since the data format of the fourth data received by the output optimization module 460 is smaller than the width of the system bus, the same problem as the input cache module 420 will occur, that is, the data stored in the cache may have a large amount of invalid data, which reduces the utilization rate of the cache. Therefore, the function setting of the output optimization module 460 can refer to the function setting of the input optimization module 410, and will not be repeated here. Through the rearrangement of the output optimization module 460, the fourth data is optimized into the second type of data, and the second type of data matches the storage mode of the output cache module 470, that is, when the second type of data is stored in the output cache module 470, no additional invalid data will be generated, thereby improving the utilization rate of the output cache module 470. The second output data processing module 480 can be regarded as the pre-processing of the data before it is output from the direct memory access circuit 400, and is configured to read the second type of data and convert the data format of the second type of data into the target data format. The pre-processing of the output data is to cooperate with writing data to the bus, read out the continuous data in the output cache, and then split it into the format required for the bus write data, because some bus write situations are not 32-bit aligned. All image data cache outputs are preprocessed to adapt them to the required data processing format.

[0075] In some embodiments of this application, please continue to refer to Figure 4 The direct memory access circuit 400 also includes a bus host interface 490 .

[0076] The bus host interface 490 is connected to the input optimization module 410 and the second output data processing module 480 respectively, and can be used to obtain image data from the memory through the system bus, and can also be used to transmit the processed image data to other sub-circuits in the integrated circuit through the system bus.

[0077] Based on similar technical concepts, the present application also discloses an integrated circuit, including a direct memory access circuit as disclosed in the above embodiments. The integrated circuit can be used, for example, in an embedded system or a dedicated image processing field. Exemplarily, in a microcontroller (MCU), the integrated circuit of the present application can improve data transmission efficiency and achieve high-speed image data transmission without occupying CPU resources. In the field of image signal processors (ISP), such as in camera modules or other imaging devices, DMA is used to efficiently transfer image data from a sensor to a memory or processor for further image processing, such as face recognition, image enhancement, etc. In the field of display controllers, in a graphics processing unit (GPU) or a display controller, DMA is used to quickly transfer image data to a display device, such as an LCD screen or LED display, especially in scenes with high-resolution displays or multi-layer image overlays.

[0078] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. A direct memory access circuit, characterized in that: For an integrated circuit, the integrated circuit includes a memory, a system bus and the direct memory access circuit, the direct memory access circuit reads a target image in the memory through the system bus, the target image has a first layer and a second layer, a space occupied by any pixel in the target image is smaller than a width of the system bus, and the direct memory access circuit includes: an input optimization module, configured to receive the first layer and the second layer of the target image respectively, rearrange the target image into first-type data in units of pixels, the first-type data including first data and second data, the first layer of the target image is rearranged into the first data, the second layer of the target image is rearranged into the second data, and output the first-type data to an input cache module so that the first-type data matches a storage mode of the input cache module, the input cache module includes a first input cache module and a second input cache module, the first data is output to the first input cache module, and the second data is output to the second input cache module; a mixing module, the mixing module comprising a first input terminal and a second input terminal, the first input terminal receiving the first data or the converted data of the first data, the second input terminal receiving the second data or the converted data of the second data, and an output terminal of the mixing module outputting the mixed third data; the mixing module performs weighted mixing based on the respective color channel values ​​and transparency values ​​in the data received by the first input terminal and the second input terminal to determine the third data; The input buffer module is configured to receive and store the first type of data, and the storage mode of the input buffer module matches the width of the system bus; the conversion data of the first data and the conversion data of the second data meet the preset data format; When the first input terminal of the mixing module receives the conversion data of the first data and the second input terminal receives the conversion data of the second data, the mixing module determines the third data according to the following calculation formula: ， ， ， in, is the transparency value of the converted data of the first data, is the transparency value of the converted data of the second data, for and The modulation value of is the transparency value of the third data, is any color channel value of the converted data of the first data, is any color channel value of the converted data of the second data, is any color channel value of the third data, , and Represents the same color channel value.

2. The direct memory access circuit according to claim 1, characterized in that: The preset data format matches the width of the system bus, and the color channel values ​​include a red channel value, a green channel value, and a blue channel value.

3. The direct memory access circuit according to claim 1 or 2, characterized in that: The mixing module includes a first divider and a second divider; The first divider is configured to process division with a divisor of 255, and the calculation formula is as follows: ， in, is the dividend; The second divider is a general divider configured to process division operations in the mixing module that are not processed by the first divider.

4. The direct memory access circuit according to claim 1 or 2, characterized in that: Also included is an input data processing module; The input data processing module is arranged between the input cache module and the mixing module, and is configured to convert the first data into the conversion data of the first data, and convert the second data into the conversion data of the second data, so that the conversion data of the first data and the conversion data of the second data meet the preset data format.

5. The direct memory access circuit according to claim 1, characterized in that: It also includes a first output data processing module, an output optimization module, an output cache module, and a second output data processing module; The first output data processing module is configured to receive the third data and process the third data into fourth data, the third data meets the preset data format, and the fourth data does not meet the preset data format; The output optimization module is configured to receive the fourth data, rearrange the fourth data into second-type data in units of pixels, and output the second-type data to the output buffer module so that the second-type data matches a storage mode of the output buffer module; The output cache module is configured to receive and store the second type of data, and the storage mode of the output cache module matches the width of the system bus; The second output data processing module is configured to read the second type of data and convert the data format of the second type of data into a target data format.

6. The direct memory access circuit according to claim 1, characterized in that: The input optimization module determines, based on the data format of the target image, that the space size occupied by any pixel in the target image is a first space value, and the first space value is smaller than the width of the system bus; The input optimization module reads the target image row by row, and determines whether the starting data of each row of the target image should be rearranged according to the offset between the starting address of each row of the target image and the alignment address, wherein the alignment address matches the width of the system bus; The input optimization module determines whether the end data of each row of the target image should be rearranged according to the first spatial value and the number of pixels of each row of the target image.

7. An integrated circuit, characterized in that: Comprising the direct memory access circuit as claimed in any one of claims 1-6.

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