Solder paste printing quality abnormality prediction method, system, device and storage medium

Abstract

The present invention discloses a method, system, device and storage medium for predicting solder paste printing quality anomaly, which are one-to-one corresponding schemes. In the scheme, according to the spatial correlation of PCB hierarchical structure and printing quality, pin map convolution and component map convolution are respectively used to capture the spatial correlation between pins and components, and then the distribution-aggregation operation is used to build a communication bridge between the pin map convolution and the component map convolution, so that the correlation between solder paste printing quality and PCB layout at different levels can be captured in layers, thereby effectively improving the prediction accuracy of printing anomalies.

Description

Technical Field

[0001] The present invention relates to the technical field of solder paste printing quality abnormality prediction, and in particular to a solder paste printing quality abnormality prediction method, system, device and storage medium. Background Art

[0002] Prediction of solder paste printing quality anomalies is mainly used for parameter adjustment of solder paste printers. Solder paste printing is achieved through solder paste printers. There are a large number of parameters that need to be set in solder paste printers. Usually these parameters will not change, but when printing quality anomalies are predicted, the printing quality can be adjusted by adjusting the printing parameters, thereby reducing the production of defective products. Accurate predictions can effectively adjust parameters in a targeted manner. If the prediction is wrong, the PCB that was originally a qualified product may become a defective product due to the adjustment of parameters. Or if the defective products are not predicted, the parameters cannot be adjusted in time, and defective products will still be processed.

[0003] The Chinese invention patent "A method and system for predicting solder paste printing quality based on IGA-DNN" with the authorization announcement number CN113094980B uses a deep fully connected neural network to predict the volume of solder paste printing. The Chinese invention patent "SMT solder paste printing volume prediction method based on industrial big data" with the authorization announcement number CN110543616B selects key factors affecting the volume of solder paste printing as features and constructs a solder paste volume time series as features, and uses RBF (RadialBasisFunction) neural network to predict the volume of solder paste printing. However, neither of these two methods considers the relationship between solder paste printing quality and PCB (Printed circuit board) layout, so the prediction effect can be further improved. In the Chinese invention patent application with publication number CN116796292A, "A method for predicting PCB solder paste printing quality based on time-reconstructed graph convolution", an adjacency matrix is ​​established based on timing correlation, and graph convolution is used to model the overall PCB layout for solder paste printing quality prediction. This method is not accurate enough in modeling the PCB layout, as it ignores the natural layered structure of the PCB. It is reasonable to use the timing correlation between pins locally, but using component coordinates to establish a distance adjacency matrix globally can more accurately characterize the PCB layout.

[0004] In view of this, the present invention is proposed. Summary of the invention

[0005] The purpose of the present invention is to provide a method, system, device and storage medium for predicting abnormal solder paste printing quality, which can utilize the historical solder paste printing quality sequence of PCB and predict the solder paste printing quality of PCB at a future moment according to the PCB layout so as to make timely corrections; and can improve the prediction accuracy.

[0006] The objective of the present invention is achieved through the following technical solutions:

[0007] A method for predicting abnormal solder paste printing quality, comprising:

[0008] Step 1, obtaining the historical solder paste printing quality sequence of all components in the PCB; wherein the PCB is a printed circuit board;

[0009] Step 2: Perform graph convolution operation on the historical solder paste printing quality sequence of each component to obtain the pin-level output features of each component, aggregate the pin-level output features of each component into component-level features, and concatenate the pin-level output features of all components into pin-level total features;

[0010] Step 3: Concatenate the component-level features of all components and perform graph convolution operation to obtain the output features of all components, and then combine the output features of all components and the pin-level total features to obtain the output total features;

[0011] Step 4: Use the output total features to predict the solder paste printing quality of all components at future times.

[0012] A solder paste printing quality abnormality prediction system, comprising:

[0013] A data acquisition unit, used to acquire a historical solder paste printing quality sequence of all components in a PCB; wherein the PCB is a printed circuit board;

[0014] The solder paste printing quality abnormality prediction model includes: a pin map convolution unit, an aggregation unit, a splicing unit, a component map convolution unit, a distribution unit and a timing prediction unit; wherein:

[0015] The pin graph convolution unit is responsible for performing graph convolution operations on the historical solder paste printing quality sequence of each component to obtain the pin-level output features of each component;

[0016] The aggregation unit is responsible for aggregating the pin-level output features of each component into component-level features;

[0017] The splicing unit is responsible for splicing the pin-level output features of all components into pin-level total features;

[0018] The component graph convolution unit is responsible for concatenating the component-level features of all components and performing graph convolution operations to obtain the output features of all components;

[0019] The allocation unit is responsible for combining the output characteristics of all components with the output characteristics of all components and the pin-level total characteristics to obtain the output total characteristics;

[0020] The timing prediction unit is responsible for predicting the solder paste printing quality of all components at future moments using the output total features.

[0021] A processing device, comprising: one or more processors; a memory for storing one or more programs;

[0022] When the one or more programs are executed by the one or more processors, the one or more processors implement the aforementioned method.

[0023] A readable storage medium stores a computer program, which implements the above method when the computer program is executed by a processor.

[0024] It can be seen from the technical solution provided by the present invention that, based on the spatial correlation of the PCB layered structure and the printing quality, the pin map convolution and the component map convolution are respectively used to capture the spatial correlation between pins and components, and then the allocation-aggregation operation is used to build a communication bridge between the pin map convolution and the component map convolution. The correlation between the solder paste printing quality and the PCB layout at different levels can be captured in layers, thereby effectively improving the prediction accuracy of printing abnormalities. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0026] Figure 1 A schematic diagram of a method for predicting abnormal solder paste printing quality provided by an embodiment of the present invention;

[0027] Figure 2 A schematic diagram of the overall framework of a method for predicting abnormal solder paste printing quality provided by an embodiment of the present invention;

[0028] Figure 3 A schematic diagram of a solder paste printing quality abnormality prediction system provided by an embodiment of the present invention;

[0029] Figure 4 A schematic diagram of a processing device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of the present invention.

[0031] First, the terms that may be used in this article are explained as follows:

[0032] The terms "include", "comprises", "contains", "has" or other descriptions with similar semantics should be interpreted as non-exclusive inclusion. For example, including certain technical feature elements (such as raw materials, components, ingredients, carriers, dosage forms, materials, dimensions, parts, components, mechanisms, devices, steps, procedures, methods, reaction conditions, processing conditions, parameters, algorithms, signals, data, products or products, etc.) should be interpreted as including not only certain technical feature elements explicitly listed, but also other technical feature elements known in the art that are not explicitly listed.

[0033] The term "consisting of..." means excluding any technical feature elements not explicitly listed. If this term is used in a claim, it will make the claim closed, so that it does not contain technical feature elements other than the technical feature elements explicitly listed, except for the conventional impurities related to them. If this term only appears in a clause of a claim, it only limits the elements explicitly listed in the clause, and the elements recorded in other clauses are not excluded from the overall claim.

[0034] The following is a detailed description of a method, system, device and storage medium for predicting abnormal solder paste printing quality provided by the present invention. The contents not described in detail in the embodiments of the present invention belong to the prior art known to professional and technical personnel in the field. If no specific conditions are specified in the embodiments of the present invention, the conventional conditions in the field or the conditions recommended by the manufacturer shall be followed.

[0035] Embodiment 1

[0036] The embodiment of the present invention provides a method for predicting abnormal quality of solder paste printing. Figure 1 As shown, it mainly includes the following steps:

[0037] Step 1: Get the historical solder paste printing quality sequence of all components in the PCB.

[0038] In the embodiment of the present invention, the method for predicting abnormal solder paste printing quality mainly uses the historical solder paste printing quality sequence of the PCB to predict the solder paste printing quality of the PCB at a future moment according to the PCB layout.

[0039] Step 2: Perform graph convolution operation on the historical solder paste printing quality sequence of each component to obtain the pin-level output features of each component, aggregate the pin-level output features of each component into component-level features, and concatenate the pin-level output features of all components into pin-level total features.

[0040] The preferred implementation of this step is as follows:

[0041] (1) Perform graph convolution operation on the historical solder paste printing quality sequence of each component to obtain the pin-level output features of each component.

[0042] Specifically: Design the pin adjacency matrix, let the number of components in the PCB be m, and the kth component has Pads, the order of pads in PCB is , then the historical solder paste printing quality sequence of the kth component is expressed as , k=1,…,m; adjacency matrix of the kth element It is expressed as:

[0043] ;

[0044] Where j is the serial number of the first pad in the kth component (that is, the serial number of the jth pad in the PCB). is the serial number of the last pad in the kth component (that is, the pads), is the printing quality sequence of the first one in the kth element, is the printing quality sequence of the last pad in the kth component, is the solder paste printing quality correlation between the first pad and the last pad in the kth component, is the solder paste printing quality correlation between the last pad and the first pad in the kth component. The correlation is calculated using and The cosine similarity is used to calculate; there is a one-to-one correspondence between pads and pins.

[0045] The following graph convolution operation is used to obtain the pin-level output features, expressed as:

[0046] ;

[0047] in, Output characteristics of the pin level of the kth component, Represents the parameters to be trained (trainable parameters), is the adjacency matrix The degree matrix of The sum of all elements in each row, all off-diagonal elements are 0.

[0048] Each component obtains pin-level output characteristics in the above manner.

[0049] (2) Feature aggregation.

[0050] The pin-level output characteristics of the kth component are recorded as , aggregated into component-level features by the following formula:

[0051] ;

[0052] in, is the component-level feature of the kth component, is the weight parameter corresponding to the kth element, is the bias parameter corresponding to the kth element, both of which are parameters to be trained.

[0053] Similarly, each component is feature aggregated in the above manner.

[0054] (3) Feature stitching.

[0055] Connect all components in rows to obtain pin-level features , Output characteristics for the pin level of the first component, Output characteristics at the pin level for the mth component.

[0056] Step 3: Concatenate the component-level features of all components and perform graph convolution operation to obtain the output features of all components, and then combine the output features of all components and the pin-level total features to obtain the output total features.

[0057] The preferred implementation of this step is as follows:

[0058] (1) The component-level features of all components are concatenated and then graph convolution is performed to obtain the output features of all components.

[0059] Specifically: Concatenate the component-level features of all components to obtain the component-level total features ;in, is the component-level feature of the first component, is the component-level feature of the mth component.

[0060] Construct a component adjacency matrix based on the distance between components in the PCB :

[0061] ;

[0062] in, is the distance between the first element and the mth element, is the distance between the mth component and the first component; m is the number of components in the PCB.

[0063] The output features of all components are obtained by performing graph convolution operation as follows:

[0064] ;

[0065] in, is the output characteristic of all components, represents the parameters to be trained, is the adjacency matrix The degree matrix of The sum of all elements in each row, all off-diagonal elements are 0.

[0066] (2) The total output characteristics are obtained by combining the output characteristics of all components and the total pin-level characteristics, which is expressed as:

[0067] ;

[0068] in, is the pin-level total feature, is the output characteristic of all components, is the total output feature, is the weight parameter corresponding to all components, are the bias parameters corresponding to all components.

[0069] Considering that the number of PCBs in this part can be determined according to actual conditions, it can be one or more, therefore, the concept of the number of PCBs is omitted in the descriptions of various symbols.

[0070] Step 4: Use the output total features to predict the solder paste printing quality of all components at future times.

[0071] As a preferred solution: a solder paste printing quality anomaly prediction model can be constructed to implement step 2, step 3 and step 4; wherein, the solder paste printing quality anomaly prediction model includes: a pin map convolution unit, an aggregation unit, a splicing unit, a component map convolution unit, an allocation unit and a timing prediction unit; wherein: the pin map convolution unit, the aggregation unit and the splicing unit execute step 2, the pin map convolution unit is responsible for performing a graph convolution operation to obtain the pin-level output features of each component, the aggregation unit is responsible for aggregating the pin-level output features of each component into component-level features, and the splicing unit is responsible for splicing the pin-level output features of all components into pin-level total features; the component map convolution unit and the allocation unit execute step 3, the component map convolution unit is responsible for splicing the component-level features of all components and performing a graph convolution operation to obtain the output features of all components, and the allocation unit is responsible for combining the output features of all components and the pin-level total features to obtain the output total features; the timing prediction unit executes step 4, and is responsible for using the output total features to predict the solder paste printing quality of all components at future moments.

[0072] The solder paste printing quality anomaly prediction model needs to be trained in advance. During training, the solder paste printing quality sequence of the PCB used for training is divided into time series segments, including an input sequence composed of the solder paste printing quality sequences of all components in the first part of the PCB, and an output sequence composed of the solder paste printing quality sequences of all components in the second part of the PCB.

[0073] The input sequence is used as the output of the solder paste printing quality anomaly prediction model to obtain the solder paste printing quality sequence of all components in the latter part of the PCB predicted by the solder paste printing quality anomaly prediction model; a loss function is constructed by combining the solder paste printing quality sequence of all components in the latter part of the predicted output with the output sequence, and the solder paste printing quality anomaly prediction model is trained using the loss function.

[0074] As a preferred solution: Step 2 and Step 3 are an iterative process. When multiple iterative processes are performed, Step 2 of the first iterative process uses the data obtained in Step 1 as input, and Step 2 of the non-first iterative process uses the total output features obtained in Step 3 of the previous iterative process as input. The total output features obtained in Step 3 of the last iterative process are used as input for Step 4. Figure 2 As shown, the overall framework diagram is shown. Of course, considering the length of the attached figure, Figure 2 Only an example of two iterations is provided, and the specific number of iterations can be set by the user according to actual conditions or experience.

[0075] The advantages of the above scheme of the present invention are analyzed as follows: Under the same component, the Pearson correlation of the time series changes in the solder paste printing quality of different pins is mostly above 0.7. The Pearson correlation of the time series changes in the solder paste printing quality between components with the same structural distribution and between components with similar distances is also mostly above 0.7. Compared with the previous methods, the method of the present invention uses the pin map convolution and the component map convolution to capture the spatial correlation between pins and components based on the spatial correlation of the PCB layered structure and printing quality, and then uses the allocation-aggregation operation to build a communication bridge between the pin map convolution and the component map convolution, which can capture the correlation between the solder paste printing quality and PCB layout at different levels in a layered manner, thereby effectively improving the prediction accuracy of printing abnormalities.

[0076] In order to more clearly demonstrate the technical solution and the technical effects provided by the present invention, the method provided by the embodiment of the present invention is described in detail with a specific embodiment below. Considering that the training and reasoning processes are roughly the same, the training process is used as an example for introduction below.

[0077] 1. Obtain the solder paste printing quality sequence of the PCB and divide the solder paste printing quality sequence into time sequence segments.

[0078] (1) Obtain the solder paste printing quality sequence of the PCB. The solder paste printing quality of the i-th PCB is recorded as , is the symbol of a real number set, M is the number of pads, there is a one-to-one correspondence between pads and pins, and each pad must be printed with solder paste that meets the standard. Then the solder paste printing quality sequence of N PCBs is expressed as .

[0079] (2) The obtained PCB solder paste printing quality sequence is divided into time segments, each segment length is T+P, expressed as , where T represents the input sequence length, P represents the output sequence Length.

[0080] In the embodiment of the present invention, a single PCB adopts Indicates that the PCB sequence with timing characteristics uses It means that starting from block i to block i+T+P, the sequence increases by 1, and the production is carried out in the order of serial numbers; for example, the production interval of PCBs with adjacent serial numbers is about 15s (seconds).

[0081] For ease of understanding, the input sequence can be divided into It is regarded as the historical solder paste printing quality sequence in the aforementioned step 1, that is, the PCBs it contains are the i-th block to the i+T-th block.

[0082] 2. Establish pin map convolution, learn the impact of local proximity on printing quality based on the printing quality correlation between pins, and aggregate and splice the pin map convolution results.

[0083] (1) Design the pin adjacency matrix.

[0084] The principle is as follows: define Represents the printing quality sequence of the jth pad, combined with the aforementioned input sequence , here is the printing quality sequence of the jth pad from the i-th PCB to the i+T-th PCB, , They are the printing quality sequences of the j-th pad in the i-th PCB and the i+T-th PCB respectively.

[0085] According to the principle of local similarity, the interaction relationship within the same component is quantified as follows:

[0086] ;

[0087] in, That is, it indicates the solder paste printing quality correlation between the jth pad and the j+1th pad.

[0088] Based on the above principle, assuming that a PCB has m components, for the kth component there is Pads, the order of pads in PCB is , then compare the above input sequence The definition of , where the solder paste printing quality sequence of the kth component from the i-th PCB to the i+T-th PCB is expressed as The adjacency matrix of the kth component from the i-th PCB to the i+T-th PCB It is expressed as follows:

[0089] ;

[0090] Where j is the serial number of the first pad in the kth component, The serial number of the last pad in the kth component, when k=m, , that is, the total number of pads of all components is M defined above.

[0091] In the embodiment of the present invention, is a symmetric matrix with all diagonal elements being 1 and all off-diagonal elements being the corresponding correlations.

[0092] (2) Perform pin graph convolution operation. According to the adjacency matrix and the solder paste printing quality sequence of the components, the graph convolution operation can be performed, which is formulated as follows:

[0093] ;

[0094] in, Represents the output characteristics (pin-level output characteristics) of the kth component from the i-th PCB to the i+T-th PCB. Represents a trainable parameter. is the adjacency matrix The degree matrix of The sum of all elements in each row, all off-diagonal elements are 0.

[0095] (3) Feature splicing. Splice all components row by row to obtain the output of the pin graph convolution, that is, the pin-level total features of all components from the i-th PCB to the i+T-th PCB , Output characteristics for the pin level of the first component, Output characteristics at the pin level for the mth component.

[0096] (4) Feature aggregation operation to build a bridge from pin features to component features. For the kth component, the features obtained by convolution of the pin graph from the i-th PCB to the i+T-th PCB are: , all pin features of the component are aggregated into component-level features using the following formula :

[0097] ;

[0098] in, and These are all trainable parameters.

[0099] 3. Establish component graph convolution, learn the impact of PCB layout on printing quality according to the spatial distribution of components on PCB, and perform feature allocation in combination with component graph convolution structure.

[0100] (1) Design the element adjacency matrix.

[0101] For the kth component, its coordinates on the PCB can be expressed as Similarly, the coordinates of the sth component on the PCB can be expressed as , then the distance between the kth element and the sth element It can be expressed as follows:

[0102] ;

[0103] Then the association between the kth element and the sth element is expressed as: .

[0104] Based on this, the element adjacency matrix It is expressed as follows:

[0105] ;

[0106] Among them, k,s=1,…m, m is the number of components in the PCB, and k and s are not equal.

[0107] (2) Perform component graph convolution operations. First, concatenate all component-level features to obtain the total component-level features from the i-th PCB to the i+T-th PCB. .

[0108] According to the element adjacency matrix And the overall characteristics of the component level , graph convolution operation can be performed, which is formulated as follows:

[0109] ;

[0110] in, Represents the output characteristics of all components from the i-th PCB to the i+T-th PCB. Represents a trainable parameter. is the adjacency matrix The degree matrix of The sum of all elements in each row, all off-diagonal elements are 0.

[0111] (3) Feature assignment operation, building a bridge from component to pin. Output features of existing component graph convolution The total output features of the convolution with the pin graph , then the feature allocation process is:

[0112] ;

[0113] in, and are all trainable parameters. It is the total output feature after the component graph convolution and pin graph convolution from the i-th PCB to the i+T-th PCB.

[0114] 4. Design a timing prediction unit to capture the timing variation pattern of solder paste printing quality.

[0115] As an example, a one-dimensional CNN (convolutional neural network) can be used as a timing prediction unit. The prediction process means performing a convolution operation on the printing quality timing characteristics of each pad. The formalization is as follows:

[0116] .

[0117] As mentioned before, PCBs are produced by serial number, and the order of serial numbers is the production order, so you can use It represents the model's prediction of the printing quality from i+T to i+T+P in the future, which is equivalent to the solder paste printing quality of all components at future moments predicted in the aforementioned step 4.

[0118] 5. Loss function calculation.

[0119] In order to accurately predict the solder paste printing quality, the predicted With the output sequence Constructing the loss function , loss function As shown below:

[0120] ;

[0121] in, is the parameter of the solder paste printing quality abnormality prediction model, including the , , , , , ; is a hyperparameter, is the symbol of L2 norm.

[0122] Based on the above loss function, the solder paste printing quality abnormality prediction model is trained and the parameters are continuously optimized. , until the stopping condition is met (for example, the set number of training times is reached, or the loss function converges), thus completing the training. After the training is completed, the historical solder paste printing quality sequence of the PCB can be used to accurately predict the solder paste printing quality of the PCB at a future moment based on the PCB layout.

[0123] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above embodiments can be implemented by software, or by means of software plus necessary general hardware platforms. Based on such understanding, the technical solutions of the above embodiments can be embodied in the form of software products, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.), including several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0124] Embodiment 2

[0125] The present invention also provides a solder paste printing quality abnormality prediction system, which is mainly used to implement the method provided in the above embodiment, such as Figure 3 As shown, the system mainly includes:

[0126] A data acquisition unit, used to acquire a historical solder paste printing quality sequence of all components in a PCB; wherein the PCB is a printed circuit board;

[0127] The solder paste printing quality abnormality prediction model includes: a pin map convolution unit, an aggregation unit, a splicing unit, a component map convolution unit, a distribution unit and a timing prediction unit; wherein:

[0128] The pin graph convolution unit is responsible for performing graph convolution operations on the historical solder paste printing quality sequence of each component to obtain the pin-level output features of each component;

[0129] The aggregation unit is responsible for aggregating the pin-level output features of each component into component-level features;

[0130] The splicing unit is responsible for splicing the pin-level output features of all components into pin-level total features;

[0131] The component graph convolution unit is responsible for concatenating the component-level features of all components and performing graph convolution operations to obtain the output features of all components;

[0132] The allocation unit is responsible for combining the output characteristics of all components with the output characteristics of all components and the pin-level total characteristics to obtain the output total characteristics;

[0133] The timing prediction unit is responsible for predicting the solder paste printing quality of all components at future moments using the output total features.

[0134] Considering that the main technical details involved in the system have been introduced in detail in the previous embodiments, they will not be repeated here.

[0135] Technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the system can be divided into different functional modules to complete all or part of the functions described above.

[0136] Embodiment 3

[0137] The present invention also provides a processing device, such as Figure 4 As shown, it mainly includes: one or more processors; a memory for storing one or more programs; wherein, when the one or more programs are executed by the one or more processors, the one or more processors implement the methods provided in the aforementioned embodiments.

[0138] Furthermore, the processing device also includes at least one input device and at least one output device; in the processing device, the processor, memory, input device, and output device are connected via a bus.

[0139] In the embodiment of the present invention, the specific types of the memory, input device and output device are not limited; for example:

[0140] The input device may be a touch screen, an image acquisition device, a physical button or a mouse, etc.;

[0141] The output device may be a display terminal;

[0142] The memory may be a random access memory (RAM) or a non-volatile memory such as a disk storage.

[0143] Embodiment 4

[0144] The present invention also provides a readable storage medium storing a computer program, which implements the method provided in the above embodiment when the computer program is executed by a processor.

[0145] In the embodiment of the present invention, the readable storage medium as a computer-readable storage medium can be set in the aforementioned processing device, for example, as a memory in the processing device. In addition, the readable storage medium can also be a U disk, a mobile hard disk, a read-only memory (ROM), a disk or an optical disk, etc., which can store program codes.

[0146] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for predicting abnormal solder paste printing quality, characterized in that: include: Step 1, obtaining the historical solder paste printing quality sequence of all components in the PCB; wherein the PCB is a printed circuit board; Step 2: Perform graph convolution operation on the historical solder paste printing quality sequence of each component to obtain the pin-level output features of each component, aggregate the pin-level output features of each component into component-level features, and concatenate the pin-level output features of all components into pin-level total features; Step 3: Concatenate the component-level features of all components and perform graph convolution operation to obtain the output features of all components, and then combine the output features of all components and the pin-level total features to obtain the output total features; Step 4: Use the output total features to predict the solder paste printing quality of all components at future times; The step of performing a graph convolution operation on the historical solder paste printing quality sequence of each component to obtain the pin-level output features of each component includes: Design the pin adjacency matrix. Let the number of components in the PCB be m. The kth component has Pads, the order of pads in PCB is , then the historical solder paste printing quality sequence of the kth component is expressed as , k=1,…,m; adjacency matrix of the kth element It is expressed as: ； Where j is the serial number of the first pad in the kth component, is the serial number of the last pad in the kth component, is the printing quality sequence of the first one in the kth element, is the printing quality sequence of the last pad in the kth component, is the solder paste printing quality correlation between the first pad and the last pad in the kth component, is the solder paste printing quality correlation between the last pad and the first pad in the kth component. The correlation is calculated using and The cosine similarity is used to calculate; the pads and pins are in one-to-one correspondence; The following graph convolution operation is used to obtain the pin-level output features, expressed as: ； in, Output characteristics of the pin level of the kth component, represents the parameters to be trained, is the adjacency matrix The degree matrix of The sum of all elements in each row, all elements in the non-diagonal area are 0; The component-level features of all components are concatenated and then subjected to graph convolution operation to obtain the output features of all components, including: The component-level features of all components are concatenated to obtain the component-level total features. ; Construct a component adjacency matrix based on the distances between components in the PCB : ； in, is the distance between the first element and the mth element, is the distance between the mth component and the first component; m is the number of components in the PCB; The output features of all components are obtained by performing graph convolution operation as follows: ； in, is the output characteristic of all components, represents the parameters to be trained, is the adjacency matrix The degree matrix of The sum of all elements in each row, all off-diagonal elements are 0.

2. The method for predicting abnormal solder paste printing quality according to claim 1, characterized in that: Aggregating the pin-level output features of each component into component-level features includes: The pin-level output characteristics of the kth component are recorded as , aggregated into component-level features by the following formula: ； in, is the component-level feature of the kth component, is the weight parameter corresponding to the kth element, is the bias parameter corresponding to the kth element.

3. The method for predicting abnormal solder paste printing quality according to claim 1, characterized in that: The total output characteristics obtained by combining the output characteristics of all components and the total pin-level characteristics are expressed as: ； in, is the pin-level total feature, is the output characteristic of all components, is the total output feature, is the weight parameter corresponding to all components, are the bias parameters corresponding to all components.

4. A method for predicting abnormal solder paste printing quality according to any one of claims 1 to 3, characterized in that: Also includes: Construct a solder paste printing quality anomaly prediction model to implement step 2, step 3 and step 4; wherein, the solder paste printing quality anomaly prediction model includes: a pin map convolution unit, an aggregation unit, a splicing unit, a component map convolution unit, an allocation unit and a timing prediction unit; wherein: the pin map convolution unit, the aggregation unit and the splicing unit perform step 2, the pin map convolution unit is responsible for performing a graph convolution operation to obtain the pin-level output features of each component, the aggregation unit is responsible for aggregating the pin-level output features of each component into component-level features, and the splicing unit is responsible for splicing the pin-level output features of all components into pin-level total features; the component map convolution unit and the allocation unit perform step 3, the component map convolution unit is responsible for splicing the component-level features of all components and performing a graph convolution operation to obtain the output features of all components, and the allocation unit is responsible for combining the output features of all components and the pin-level total features to obtain the output total features; the timing prediction unit performs step 4, and is responsible for using the output total features to predict the solder paste printing quality of all components at future moments; The solder paste printing quality abnormality prediction model needs to be trained in advance. During the training, the solder paste printing quality sequence of the PCB used for training is divided into time series segments, including an input sequence composed of the solder paste printing quality sequences of all components in the first part of the PCB, and an output sequence composed of the solder paste printing quality sequences of all components in the second part of the PCB; The input sequence is used as the output of the solder paste printing quality anomaly prediction model to obtain the solder paste printing quality sequence of all components in the latter part of the PCB predicted by the solder paste printing quality anomaly prediction model; a loss function is constructed by combining the solder paste printing quality sequence of all components in the latter part of the predicted output with the output sequence, and the solder paste printing quality anomaly prediction model is trained using the loss function.

5. A method for predicting abnormal solder paste printing quality according to any one of claims 1 to 3, characterized in that: Also includes: Step 2 and step 3 are an iterative process. When multiple iterative processes are performed, step 2 of the first iterative process uses the data obtained in step 1 as input, step 2 of a non-first iterative process uses the total output features obtained in step 3 of the previous iterative process as input, and the total output features obtained in step 3 of the last iterative process are used as input for step 4.

6. A solder paste printing quality abnormality prediction system, characterized in that: The method for implementing any one of claims 1 to 5 comprises: A data acquisition unit, used to acquire a historical solder paste printing quality sequence of all components in a PCB; wherein the PCB is a printed circuit board; The solder paste printing quality abnormality prediction model includes: a pin map convolution unit, an aggregation unit, a splicing unit, a component map convolution unit, a distribution unit and a timing prediction unit; wherein: The pin graph convolution unit is responsible for performing graph convolution operations on the historical solder paste printing quality sequence of each component to obtain the pin-level output features of each component; The aggregation unit is responsible for aggregating the pin-level output features of each component into component-level features; The splicing unit is responsible for splicing the pin-level output features of all components into pin-level total features; The component graph convolution unit is responsible for concatenating the component-level features of all components and performing graph convolution operations to obtain the output features of all components; The allocation unit is responsible for combining the output characteristics of all components with the output characteristics of all components and the pin-level total characteristics to obtain the output total characteristics; The timing prediction unit is responsible for predicting the solder paste printing quality of all components at future moments using the output total features.

7. A processing device, characterized in that: include: one or more processors; A memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 5.

8. A readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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