Split-gate structure silicon carbide MOSFET and manufacturing method thereof

Abstract

The present invention discloses a split-gate structure silicon carbide MOSFET and a manufacturing method thereof. The split-gate structure silicon carbide MOSFET comprises a table, a substrate of a first conductivity type, an epitaxial layer and a source region, a well region of a second conductivity type, a body region and an electric field modulation region, and the isolation dielectric is in a climbing shape. The electric field modulation region is used to effectively protect the gate dielectric of the split-gate structure, and the Schottky contact length is precisely controlled by designing the climbing-shaped isolation dielectric and the electric field modulation region, thereby accurately controlling the reverse conduction voltage drop of the device, achieving a good balance between reducing the reverse conduction voltage drop and maintaining low leakage, and improving the third quadrant characteristics of the device without damaging the breakdown characteristics. The present invention also discloses a manufacturing method of the device structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a split-gate structure silicon carbide MOSFET and a manufacturing method thereof. Background Art

[0002] As power electronics technology continues to develop towards high power density, low switching loss, and miniaturization, the performance of power semiconductor devices needs to be improved. Compared with Si-based power devices, SiC power devices have obvious advantages in high power, high temperature and other fields, and have attracted much attention from domestic and foreign companies and research institutions.

[0003] Among SiC power devices, SiC metal oxide semiconductor field effect transistors (MOSFETs) have been widely used due to their advantages such as simple gate drive and unipolar conduction. The cell structure of conventional SiC MOSFETs is as follows: Figure 5 As shown, the first isolation dielectric 14 wraps the gate conductor 8. However, conventional SiC MOSFET has a problem of large feedback capacitance, which leads to increased switching loss and excessively high dV / dt in practical applications, causing energy waste and reducing application reliability.

[0004] A common solution is the split-gate SiC MOSFET, such as Figure 6 As shown in Figure 1. This structure divides the gate into two parts, left and right, to control the left and right conductive channels respectively, and the left and right gates are isolated by an insulating layer. Since the gate-drain overlap area is greatly reduced, this structure can greatly reduce the device feedback capacitance, thereby reducing switching losses and reducing dV / dt.

[0005] However, there are new problems with split-gate SiC MOSFET. Since this structure divides the gate into two parts, the right edge of the left gate and the left edge of the right gate are located near the top of the epitaxial layer between the well regions. The electric field concentration effect causes a strong electric field to be generated in this area, which makes the gate dielectric there prone to premature breakdown, causing the device to fail prematurely. How to effectively protect the gate dielectric near the left and right gate edges is the key point in the design of split-gate SiC MOSFET.

[0006] In addition, the larger bandgap width of SiC material leads to a higher body diode turn-on voltage, poor reverse recovery characteristics, and high switching losses when the device operates in the third quadrant. The conduction of the body diode will cause bipolar degradation problems. Integrating a Schottky barrier diode inside the SiC MOSFET device can reduce the reverse conduction voltage drop of the device and prevent the body diode from turning on. However, if the Schottky contact length is too large and the barrier is too low, the reverse leakage of the device will increase significantly. If the Schottky contact length is too small, the reverse conduction voltage drop of the device will not decrease significantly, and it may even be impossible to completely suppress the body diode from turning on. Integrating Schottky barrier diodes will also bring about problems such as increased cell size or increased manufacturing difficulty. Summary of the invention

[0007] Technical purpose: In view of the shortcomings of the above-mentioned split-gate structure SiC MOSFET device, the present invention provides a split-gate structure silicon carbide MOSFET and a manufacturing method thereof. The purpose of the present invention is to maintain the inherent advantage of the split-gate structure in reducing feedback capacitance under the premise of effectively protecting the gate dielectric near the left and right gate edges, and at the same time to achieve a better balance between reducing the reverse conduction voltage drop of the device and maintaining low leakage current, and significantly improve the third quadrant characteristics of the device without increasing the cell size.

[0008] Technical solution: In order to achieve the above technical objectives, the present invention adopts the following technical solution.

[0009] A split-gate structure silicon carbide MOSFET, comprising:

[0010] a fourth electrical conductor;

[0011] A substrate located on the fourth conductor, and an epitaxial layer located on the substrate; the epitaxial layer is in a convex shape;

[0012] A well region located in the low terraces on both sides of the epitaxial layer; a source region located in the well region; a body region located in the well region and adjacent to the source region;

[0013] A first dielectric located above the well region and the source region; a first conductor and a second conductor located above the first dielectric and on the left and right sides of the epitaxial layer; a distance between the right boundary of the first conductor and the right boundary of the source region is greater than a distance between the right boundary of the well region and the right boundary of the source region; a distance between the left boundary of the second conductor and the left boundary of the source region is greater than a distance between the left boundary of the well region and the left boundary of the source region;

[0014] An isolation medium located on both sides and above the first conductor and the second conductor and on the raised step in the center of the epitaxial layer, the isolation medium being in a climbing shape;

[0015] A mesa located between adjacent well regions and at a raised step in the center of the epitaxial layer; an electric field modulation region located at the bottom or sidewall of the mesa;

[0016] The third conductor is located on both sides and above the isolation medium and completely fills the mesa.

[0017] A method for manufacturing a split-gate structure silicon carbide MOSFET, used to manufacture the split-gate structure silicon carbide MOSFET described above, comprises the following steps:

[0018] Step 1, forming an epitaxial layer on a substrate;

[0019] Step 2, etching the epitaxial layer to form a convex shape;

[0020] Step 3, forming a well region at the low terraces on both sides of the epitaxial layer, and forming a source region and a body region adjacent to the source region in the well region;

[0021] Step 4, forming a first dielectric on the surface of the well region and the source region, and forming a first conductor and a second conductor on the first dielectric and on the low terraces on both sides of the epitaxial layer respectively;

[0022] Step 5, forming an isolation dielectric on both sides and on the first conductor and the second conductor and on the raised step in the center of the epitaxial layer;

[0023] Step 6, etching and removing part of the epitaxial layer between adjacent well regions to form a mesa;

[0024] Step 7, forming an electric field modulation region at the bottom or side wall of the table;

[0025] Step 8: Form a third conductor that completely fills the mesa on both sides and above the isolation medium, and form a fourth conductor at the bottom of the substrate; the third conductor forms an ohmic contact with the top surface of part of the source region and the top surface of the body region, and the third conductor forms a Schottky contact with the epitaxial layer at the side wall or bottom of the mesa.

[0026] Beneficial effects:

[0027] (1) The split-gate silicon carbide MOSFET proposed in the present invention forms a table on the surface of the epitaxial layer between adjacent well regions, and forms an electric field modulation region on the sidewall or bottom of the table. In the off state, the electric field modulation region is used to effectively protect the first dielectric at the edge of the first conductor and the second conductor. At the same time, the electric field modulation region is far away from the conductive channel region to ensure that the device current density is not affected. While ensuring the inherent advantage of the split-gate structure in reducing feedback capacitance, the most difficult problem of protecting the gate dielectric in the structure is solved.

[0028] (2) The split-gate silicon carbide MOSFET proposed in the present invention fills the mesa with a third conductor, controls the boundary position of the ramp-shaped isolation dielectric through photolithography and etching processes, and controls the position and depth of the electric field modulation region through ion implantation process energy, dose and tilt angle, thereby achieving precise control of the Schottky contact length, while ensuring that the body diode is not turned on and the reverse conduction voltage drop of the device is reduced, without increasing the reverse leakage. In addition, the present invention does not need to sacrifice the cell size to realize the integrated Schottky diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Schematic diagram of a split-gate silicon carbide MOSFET of Example 1.

[0030] Figure 2 Schematic diagram of a split-gate silicon carbide MOSFET according to Example 2.

[0031] Figure 3 Schematic diagram of a split-gate silicon carbide MOSFET of Example 3.

[0032] Figure 4 Schematic diagram of a split-gate silicon carbide MOSFET of Example 4.

[0033] Figure 5 Schematic diagram of existing silicon carbide MOSFET.

[0034] Figure 6 Schematic diagram of an existing split-gate structure silicon carbide MOSFET.

[0035] Figure 7 to Figure 14 Schematic diagram of the preparation process of the split-gate structure silicon carbide MOSFET of Example 1.

[0036] Explanation of the accompanying drawings: 1. fourth conductor; 2. substrate; 3. epitaxial layer; 4. well region; 5. source region; 6. body region; 7. first dielectric; 8. gate conductor; 8-1. first conductor; 8-2. second conductor; 9. electric field modulation region; 10. isolation dielectric; 11. third conductor; 12. table; 13. current spreading layer. DETAILED DESCRIPTION

[0037] A split-gate silicon carbide MOSFET and a manufacturing method thereof of the present invention are further explained and illustrated below in conjunction with the accompanying drawings and embodiments.

[0038] The embodiments are only used to illustrate the present invention and do not limit the scope of the claims. Other alternative means that can be thought of by those skilled in the art are all within the scope of the claims of the present invention.

[0039] In addition, in the description of the present invention, it should be noted that the terms "central", "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0040] Example 1

[0041] As attached Figure 1 As shown, a split-gate structure silicon carbide MOSFET of this embodiment includes:

[0042] a fourth conductor 1;

[0043] A substrate 2 located on the fourth conductor 1, and an epitaxial layer 3 located on the substrate 2; the epitaxial layer 3 is in a convex shape;

[0044] A well region 4 located in the low terraces on both sides of the epitaxial layer 3; a source region 5 located in the well region 4; a body region 6 located in the well region 4 and adjacent to the source region 5;

[0045] A first dielectric 7 located on the well region 4 and the source region 5; a first conductor 8-1 and a second conductor 8-2 located on the first dielectric 7 and on the left and right sides of the epitaxial layer 3; the distance between the right boundary of the first conductor 8-1 and the right boundary of the source region 5 is greater than the distance between the right boundary of the well region 4 and the right boundary of the source region 5; the distance between the left boundary of the second conductor 8-2 and the left boundary of the source region 5 is greater than the distance between the left boundary of the well region 4 and the left boundary of the source region 5; the first dielectric 7 serves as a gate dielectric; the first conductor 8-1 and the second conductor 8-2 serve as left and right gates in a split-gate structure;

[0046] An isolation dielectric 10 located on both sides and above the first conductor 8-1 and the second conductor 8-2 and on the raised step in the center of the epitaxial layer 3, the isolation dielectric 10 being in a climbing shape;

[0047] A terrace 12 located between adjacent well regions 4 and at a raised step in the center of the epitaxial layer 3;

[0048] An electric field modulation region 9 is located at the bottom or side wall of the mesa 12; the bottom surface of the electric field modulation region is higher than the bottom surface of the well region, and the height difference between the two is not less than 0.1 μm;

[0049] The third conductive body 11 is located on both sides and on the isolation medium 10 and completely covers the mesa 12 .

[0050] The doping types of the substrate, epitaxial layer and source region are the first conductivity type, and the doping types of the well region, body region and electric field modulation region are the second conductivity type. The first conductivity type can be N-type or P-type, and correspondingly, the second conductivity type can be P-type or N-type.

[0051] As attached Figure 7 To Attachment Fig.14 As shown, a method for manufacturing a split-gate structure silicon carbide MOSFET of the present invention comprises the following steps:

[0052] Step 1: forming an epitaxial layer 3 on a substrate 2; Figure 7 As shown, an epitaxial layer 3 is formed on a substrate 2 by epitaxial growth; the depth of the substrate 2 ranges from 80µm to 300µm, and the average doping concentration of the substrate 2 is 1e19cm -3 ~ 1e20cm -3 ; The depth of epitaxial layer 3 ranges from 5µm to 50µm, and the doping concentration of epitaxial layer 3 is 1e15cm -3 ~ 1e17cm -3 ; The semiconductor material used for the substrate 2 and the epitaxial layer 3 can be 3C-SiC, 4H-SiC or 6H-SiC.

[0053] Step 2, etching the epitaxial layer 3 to form a convex shape; Figure 8 As shown, a portion of the epitaxial layer 3 is removed by etching to form a convex shape, and the depth of the etched portion of the epitaxial layer 3 ranges from 0.5µm to 3.5µm; the width of the convex step at the center of the epitaxial layer 3 ranges from 1µm to 5µm;

[0054] Step 3, forming a well region 4 at the low terraces on both sides of the epitaxial layer 3, forming a source region 5 and a body region 6 adjacent to the source region 5 in the well region 4; Fig. 9 As shown, a well region 4, a source region 5 and a body region 6 are formed respectively by an ion implantation process, wherein the well region 4 is formed at the low terraces on both sides of the epitaxial layer 3 by the ion implantation process, the top surface of the well region 4 is flush with the low terraces on both sides of the epitaxial layer 3, the bottom surface of the well region 4 is higher than the bottom surface of the epitaxial layer 3, the depth of the well region 4 ranges from 0.5µm to 3.0µm, and the average doping concentration is 5e16cm -3 ~ 5e18cm -3 , the width between adjacent well regions 4 ranges from 1.0µm to 6.0µm; a source region 5 and a body region 6 adjacent to the source region 5 are formed in the well region 4 by an ion implantation process, the top surface of the source region 5 is flush with the top surface of the well region 4, the bottom surface of the source region 5 is higher than the bottom surface of the well region 4, the depth of the source region 5 ranges from 0.2µm to 0.5µm, and the average doping concentration is 5e18cm -3 ~ 2e20cm -3, the width between adjacent source regions 5 ranges from 0.5µm to 3.0µm; the top surface of the body region 6 is flush with the top surface of the source region 5 and the top surface of the well region 4, the bottom surface of the body region 6 is higher than the bottom surface of the well region 4, the depth of the body region 6 ranges from 0.2µm to 0.5µm, and the average doping concentration is 5e18cm -3 ~ 2e20cm -3 ;

[0055] Step 4, forming a first dielectric 7 on the surface of the well region 4 and the source region 5, and forming a first conductor 8-1 and a second conductor 8-2 on the first dielectric 7 and on the low terraces on both sides of the epitaxial layer 3; Fig.10 As shown, a first dielectric 7 is formed on the surface of the well region 4 and the source region 5 by thermal oxidation and LPCVD (Low Pressure Chemical Vapor Deposition) processes, and the first dielectric 7 covers a portion of the epitaxial layer 3, a portion of the well region 4, and a portion of the source region 5. The first dielectric 7 is subjected to high temperature annealing treatment, and then a first conductor 8-1 and a second conductor 8-2 are formed on the first dielectric 7 and on the low terraces on both sides of the epitaxial layer 3 by the LPCVD process, and the first conductor 8-1 and the second conductor 8-2 are implanted and activated by annealing;

[0056] The distance between the right boundary of the first conductor 8-1 and the right boundary of the source region 5 is greater than the distance between the right boundary of the well region 4 and the right boundary of the source region 5; the distance between the left boundary of the second conductor 8-2 and the left boundary of the source region 5 is greater than the distance between the left boundary of the well region 4 and the left boundary of the source region 5; this structural design ensures that the first conductor 8-1 and the second conductor 8-2 can effectively control the conductive channel.

[0057] The material of the first dielectric 7 can be silicon oxide, silicon nitride, borophosphosilicate glass, aluminum oxide, sapphire or hafnium oxide, and the thickness of the first dielectric ranges from 40nm to 200nm. The material of the first conductor 8-1 and the second conductor 8-2 can be metal or doped polysilicon.

[0058] Step 5, forming an isolation dielectric 10 on both sides and on the first conductor 8-1 and the second conductor 8-2 and on the raised step in the center of the epitaxial layer 3; Fig.11 As shown, through LPCVD process, photolithography process and etching process, a climbing-shaped isolation medium 10 is formed on both sides and above the first conductor 8-1 and the second conductor 8-2 and on the central raised step of the epitaxial layer 3. The isolation medium 10 is divided into two unconnected parts, and both sides of the central raised step of the epitaxial layer 3 are in a climbing shape; the material of the isolation medium 10 can be silicon dioxide, or nitride, or a composite of silicon dioxide and nitride.

[0059] Step 6: etching and removing part of the epitaxial layer 3 between adjacent well regions 4 to form a mesa 12; Fig.12 As shown, a portion of the epitaxial layer 3 between adjacent well regions 4 is removed by an etching process to form a mesa 12, which is located on the central raised step of the epitaxial layer 3 and is centrally arranged; the depth of the mesa 12 ranges from 0.4µm to 2.5µm, the width of the mesa 12 ranges from 0.5µm to 3.0µm, and the angle of the side walls of the mesa 12 is not less than 80 degrees; the depth direction of the device of the mesa 12, that is, perpendicular to Figure 1 In the direction of the paper shown, it can be distributed continuously or discontinuously. In this embodiment, at the raised step in the center of the epitaxial layer 3, the top of the epitaxial layer except the terrace 12 is completely covered by the isolation dielectric 10, that is, the side wall of the isolation dielectric 10 is adjacent to the terrace 12;

[0060] Step 7: forming an electric field modulation region 9 at the bottom or side wall of the mesa 12; Fig.13 As shown, an electric field modulation region 9 is formed at the bottom or sidewall of the mesa 12 by an ion implantation process. The depth of the electric field modulation region 9 ranges from 0.2µm to 1.5µm, and the average doping concentration is 5e16cm -3 ~ 5e18cm -3 The bottom surface of the electric field modulation area is higher than the bottom surface of the well area, and the height difference between the two is not less than 0.1µm. The position and concentration of the electric field modulation area are precisely controlled by the energy, dose, angle and barrier layer (not shown in the figure) of the ion implantation process, thereby precisely controlling the length of the subsequently formed Schottky contact.

[0061] Step 8: Form a third conductor 11 completely covering the mesa 12 on both sides and on the isolation medium 10, and form a fourth conductor 1 at the bottom of the substrate 2; Fig.14 As shown, a third conductor 11 is grown on both sides and on the isolation dielectric 10, the third conductor 11 completely covers the mesa 12, the third conductor 11 forms an ohmic contact with the top surface of part of the source region 5 and the top surface of the body region 6, and the third conductor 11 forms a Schottky contact with the epitaxial layer 3 at the side wall or bottom of the mesa 12. A fourth conductor is grown on the bottom layer of the substrate, and the fourth conductor forms an ohmic contact with the substrate.

[0062] The etching process in step 2 and step 6 may adopt an ICP (Inductive Coupled Plasma) etching process, and the etching gas adopted may be one or more combinations of gases such as SF6, HBr, Cl2, O2, and Ar.

[0063] The material of the third conductor 11 can be one or more combinations of metals such as Ti, Al, Ag, etc. The material of the fourth conductor can be one or more combinations of metals such as Ti, Al, Ni, Ag, etc.

[0064] The present invention controls the boundary position of the climbing isolation medium through photolithography and etching processes, and controls the position and depth of the electric field modulation area through ion implantation process energy, dosage and tilt angle, so as to achieve precise control of the Schottky contact length, and does not increase the reverse leakage while ensuring that the body diode is not turned on and the reverse conduction voltage drop of the device is reduced. The tilt angle range is 10 degrees to 80 degrees.

[0065] Example 2

[0066] As attached Figure 2 As shown, a split-gate silicon carbide MOSFET of this embodiment is different from that of Embodiment 1 in that: the top width of the isolation dielectric 10 is smaller, that is, at the raised step in the center of the epitaxial layer 3, the top portion of the epitaxial layer except for the table 12 is covered by the isolation dielectric 10. Therefore, the third conductor 11 forms a Schottky contact with the epitaxial layer 3 at the bottom of the table 12, the side walls on both sides, and the top of the epitaxial layer 3 located at the raised step in the center of the epitaxial layer 3. Such a design can appropriately increase the Schottky contact length and further reduce the reverse conduction voltage drop of the device, which is suitable for application scenarios with high requirements on reverse recovery characteristics and low requirements on switching losses.

[0067] Example 3

[0068] As attached Figure 3 As shown, a split-gate silicon carbide MOSFET of this embodiment is different from that of Embodiment 1 in that the electric field modulation region 9 completely covers the bottom of the table 12 and covers part of the side walls of the table 12, and the third conductor 11 forms a Schottky contact with the epitaxial layer 3 in the side wall area of ​​the table 12 not covered by the electric field modulation region 9. Such a design can further reduce the device leakage at the premise of slightly sacrificing the reverse conduction voltage drop, and is suitable for application scenarios with lower device leakage requirements.

[0069] Example 4

[0070] As attached Figure 4 As shown, a split-gate silicon carbide MOSFET of this embodiment is different from that of embodiment 1 in that a current spreading layer 13 adjacent to the well region 4 is formed between adjacent well regions 4, the doping type of the current spreading layer 13 is the first conductivity type, the depth range of the current spreading layer 13 is 0.5µm ~ 3.0µm, and the doping concentration is 5e16cm -3 ~ 5e17cm -3 The depth of the current spreading layer can be the same as or different from the depth of the well region. The introduction of the current spreading layer can further reduce the on-resistance of the device and increase the current density.

[0071] The manufacturing method of a split-gate silicon carbide MOSFET of this embodiment is different from that of Embodiment 1 in that: in step 3, when forming well regions 4 at the low terraces on both sides of the epitaxial layer 3, a current expansion layer 13 adjacent to the well regions 4 is formed between adjacent well regions 4 by an ion implantation process.

[0072] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A split-gate silicon carbide MOSFET, characterized in that: include: a fourth electrical conductor; A substrate located on the fourth conductor, and an epitaxial layer located on the substrate; the epitaxial layer is in a convex shape; A well region located in the low terraces on both sides of the epitaxial layer; a source region located in the well region; a body region located in the well region and adjacent to the source region; A first dielectric located above the well region and the source region; a first conductor and a second conductor located above the first dielectric and on the left and right sides of the epitaxial layer; a distance between the right boundary of the first conductor and the right boundary of the source region is greater than a distance between the right boundary of the well region and the right boundary of the source region; a distance between the left boundary of the second conductor and the left boundary of the source region is greater than a distance between the left boundary of the well region and the left boundary of the source region; An isolation medium located on both sides and above the first conductor and the second conductor and on the raised step in the center of the epitaxial layer, the isolation medium being in a climbing shape; On the raised step in the center of the epitaxial layer, part or all of the top of the epitaxial layer except the terrace is covered by the isolation dielectric; A terrace located between adjacent well regions and at a raised step in the center of the epitaxial layer; an electric field modulation region located at the bottom or sidewall of the mesa; The third conductor is located on both sides and above the isolation medium and completely fills the mesa.

2. A split-gate silicon carbide MOSFET according to claim 1, characterized in that: The bottom surface of the electric field modulation region is higher than the bottom surface of the well region, and the height difference between the two is not less than 0.1µm.

3. The split-gate silicon carbide MOSFET according to claim 1, characterized in that: The depth of the table is in the range of 0.4µm to 2.5µm, the width of the table is in the range of 0.5µm to 3.0µm, and the angle of the side walls on both sides of the table is not less than 80 degrees.

4. The split-gate silicon carbide MOSFET according to claim 1, characterized in that: The third conductor forms an ohmic contact with a portion of the top surface of the source region and the top surface of the body region, and the third conductor forms a Schottky contact with the epitaxial layer at the side wall or bottom of the mesa.

5. The split-gate silicon carbide MOSFET according to claim 1, characterized in that: The electric field modulation region completely covers the bottom of the mesa and partially covers the side walls of the mesa. The third conductor forms a Schottky contact with the epitaxial layer in the side wall area of ​​the mesa not covered by the electric field modulation region.

6. The split-gate silicon carbide MOSFET according to claim 1, characterized in that: A current spreading layer adjacent to the well region is formed between adjacent well regions, the doping type of the current spreading layer is the first conductivity type, and the depth of the current spreading layer ranges from 0.5µm to 3.0µm.

7. A method for manufacturing a split-gate silicon carbide MOSFET, used to manufacture a split-gate silicon carbide MOSFET as claimed in any one of claims 1 to 6, characterized in that: The following steps are involved: Step 1, forming an epitaxial layer on a substrate; Step 2, etching the epitaxial layer to form a convex shape; Step 3, forming a well region at the low terraces on both sides of the epitaxial layer, and forming a source region and a body region adjacent to the source region in the well region; Step 4, forming a first dielectric on the surface of the well region and the source region, and forming a first conductor and a second conductor on the first dielectric and on the low terraces on both sides of the epitaxial layer respectively; Step 5, forming an isolation dielectric on both sides and on the first conductor and the second conductor and on the raised step in the center of the epitaxial layer; Step 6, etching and removing part of the epitaxial layer between adjacent well regions to form a mesa; Step 7, forming an electric field modulation region at the bottom or side wall of the table; Step 8: Form a third conductor that completely fills the mesa on both sides and above the isolation medium, and form a fourth conductor at the bottom of the substrate; the third conductor forms an ohmic contact with the top surface of part of the source region and the top surface of the body region, and the third conductor forms a Schottky contact with the epitaxial layer at the side wall or bottom of the mesa.

8. The method for manufacturing a split-gate silicon carbide MOSFET according to claim 7, characterized in that: The etching process in step 2 and step 6 adopts ICP etching process, and the etching gas adopted is one or more combinations of SF6, HBr, Cl2, O2, and Ar gases.

9. The method for manufacturing a split-gate silicon carbide MOSFET according to claim 7, characterized in that: In step 5, the edge position of the climbing isolation medium is precisely controlled by photolithography and etching processes. In step 7, the position and concentration of the electric field modulation area are precisely controlled by the energy, dose, angle and barrier layer of the ion implantation process, thereby precisely controlling the length of the subsequently formed Schottky contact.

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