Chip testing device and method

Abstract

The invention provides a chip testing device and method. The device comprises a probe support and a testing probe arranged on the probe support. Wherein the metal bump of the to-be-detected chip comprises a support column arranged on a chip protection layer and a solder cap positioned at the end part of the support column; the test probe is provided with an opening end, the material of the test probe comprises memory metal, and the opening end of the test probe is in contact conduction with the support column when meeting a preset condition; a first positioning piece is arranged on the probe support, a second positioning piece is arranged on the to-be-detected chip, and the test probes and the to-be-detected chip are positioned through the first positioning piece and the second positioning piece, so that the test probes are in one-to-one correspondence with the metal bumps. According to the invention, the related test of the chip can be completed under the condition that the solder cap is not damaged.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and more specifically, to a chip testing device and method. Background Art

[0002] In the field of semiconductor chip stacking technology, before a chip is formed or shipped, its related performance needs to be tested to achieve chip quality inspection, grading, and defective product screening. Currently, there are various ways to stack chips, such as HBM, Wide-IO, or HMC. When testing such chips, an external probe is required to contact the metal bumps on the chip to achieve the transmission of test signals and test results.

[0003] However, since the metal bumps on the chip are small and fragile, if the existing probes are used to directly contact the metal bumps, the solder ends of the metal bumps will be damaged. The positioning error between the chip and the probe will also cause the probe and the solder end to collide, thereby affecting the subsequent bonding process and chip performance, and affecting the product yield.

[0004] Therefore, there is an urgent need for a chip testing solution that can achieve precise positioning between the chip and the test signal while achieving conduction between the two, so as to prevent the solder end of the metal bump from being damaged and affecting the chip performance. Summary of the invention

[0005] In view of the above problems, the purpose of the present invention is to provide a chip testing device and method to solve the problem that the solder end of the chip is damaged due to contact testing and positioning reasons in the existing chip testing scheme, thereby affecting the chip performance.

[0006] The chip testing device provided by the present invention comprises: a probe bracket and a test probe arranged on the probe bracket; wherein the metal bump of the chip to be tested comprises a support column arranged on the chip protection layer and a solder cap located at the end of the support column; the test probe has an open end, and the material comprises a memory metal, and the open end of the test probe contacts and conducts with the support column when a preset condition is met; a first positioning piece is arranged on the probe bracket, and a second positioning piece is arranged on the chip to be tested, and the test probe and the chip to be tested are positioned by the first positioning piece and the second positioning piece so that the test probe and the metal bump correspond one-to-one.

[0007] In addition, an optional technical solution is that the first positioning member includes at least one alignment hole, and the second positioning member includes a marking corresponding to the position of the alignment hole; the marking is a color or mark that is different from the chip to be detected.

[0008] In addition, an optional technical solution is that the first positioning member includes at least one positioning block / groove, and the second positioning member includes a groove / positioning block corresponding to the position of the positioning block / groove; when the test probe is in contact with the support column, the positioning block is limited in the groove at the corresponding position.

[0009] In addition, an optional technical solution is that the probe bracket is a PCB, and the test probe is connected to an external test system through the PCB; and the alignment hole is a through hole that penetrates the PCB.

[0010] In addition, an optional technical solution is that the alignment holes are arranged on both sides of the PCB, and the marking objects are arranged in the area of ​​the chip to be tested where the metal bumps are not arranged; or, the alignment holes are arranged inside each test probe, and the marking objects are the solder caps.

[0011] In addition, an optional technical solution is to provide a camera module on the side of the alignment hole away from the marking object; wherein the camera module is used to capture a position image between the chip to be detected and the test probe to adjust the relative position of the chip to be detected and the test probe according to the position image.

[0012] In addition, an optional technical solution is that it also includes a driving device for driving the movement of the chip to be detected and a suction nozzle head arranged on the driving device; wherein the suction nozzle head is adsorbed and fixed on the chip to be detected; and the driving device is used to adjust the relative position between the chip to be detected and the test probe according to the position image.

[0013] In addition, an optional technical solution is that the test probe has a deformable internal cavity structure; the cross-section of the cavity structure is a circular structure; and the difference between the cross-sectional dimensions of the cavity structure and the solder cap ranges from 0 to 50 um.

[0014] In addition, an optional technical solution is that the preset condition is that the temperature is greater than 70° C.; when the preset condition is not met, the open end of the test clamp is in an open state, and the size of the open end is greater than the size of the solder cap.

[0015] On the other hand, the present invention also provides a chip testing method, which uses the above-mentioned chip testing device to test the chip to be tested, and the method includes: after moving the test probe to the top of the chip to be tested, aligning the test probe and the chip to be tested by using a first positioning member and a second positioning member; controlling the test probe to descend or the chip to be tested to rise until the end of the test probe is located on the outside of a supporting column; controlling the test probe to contact and conduct with the supporting column when preset conditions are met, and sending a test signal to the chip to be tested through the test probe to complete the test of the chip to be tested.

[0016] By utilizing the above-mentioned chip testing device and method, the test probe is set to a cavity structure with an open end, and a shape-changeable memory metal material is used, so that the open end of the test probe is in contact with the support column and is connected when preset conditions are met. At the same time, the structure of the first positioning member and the second positioning member is coordinated to ensure the positional accuracy of each test probe and the metal bump at the corresponding position, and the conduction between the test probe and the metal bump is achieved through the support column, thereby avoiding direct contact between the test probe and the solder cap, ensuring the integrity of the shape of the solder cap, and avoiding the subsequent process and performance being affected due to damage to the solder cap.

[0017] In order to achieve the above and related purposes, one or more aspects of the present invention include the features that will be described in detail later. The following description and the accompanying drawings describe some exemplary aspects of the present invention in detail. However, these aspects indicate only some of the various ways in which the principles of the present invention can be used. In addition, the present invention is intended to include all these aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] By referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will become more apparent and easy to understand. In the accompanying drawings:

[0019] Figure 1 is a schematic structural diagram of a chip testing device in a first state according to an embodiment of the present invention;

[0020] Figure 2 is a schematic structural diagram of a chip testing device in a second state according to an embodiment of the present invention;

[0021] Figure 3 is a schematic diagram of the structure of a chip testing device before positioning according to an embodiment of the present invention;

[0022] Figure 4 is a schematic diagram of the structure of a chip testing device after positioning according to an embodiment of the present invention;

[0023] Figure 5is a schematic diagram of the structure of a chip testing device before positioning according to another embodiment of the present invention;

[0024] Figure 6 is a schematic diagram of the structure of a chip testing device after positioning according to another embodiment of the present invention;

[0025] Figure 7 FIG. 4 is a flow chart of a chip testing method according to an embodiment of the present invention.

[0026] The reference numerals therein include: test probe 1, base 11, inclined side arm 12, open end 13, solder cap 21, support column 22, alignment hole 31, nozzle head 5, chip to be tested 6, marking object 61, camera module 7, AC-DA chip 8.

[0027] The same reference numerals throughout the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0028] In the following description, for the purpose of illustration, in order to provide a comprehensive understanding of one or more embodiments, many specific details are set forth. However, it is apparent that these embodiments may also be implemented without these specific details. In other examples, for ease of describing one or more embodiments, known structures and devices are shown in the form of block diagrams.

[0029] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0030] It will be understood by those skilled in the art that, unless otherwise stated, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that the term "and / or" used herein includes any unit and all combinations of one or more associated listed items.

[0031] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless defined as herein.

[0032] To describe the chip testing device and method in detail, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0033] Figures 1 to 6 The overall or partial schematic structures of the chip testing device according to the embodiment of the present invention are shown from different angles.

[0034] like Figures 1 to 6 As shown together, the chip testing device of the embodiment of the present invention includes a probe holder and a test probe 1 arranged on the probe holder, wherein the metal bump of the chip 6 to be tested includes a support column 22 arranged on the chip protection layer and a solder cap 21 located at the end of the support column 22. Generally, the material of the support column 22 is slightly harder than the solder cap 21. For example, the support column 22 can be made of copper, which is less susceptible to damage than the solder cap 21. In order to avoid direct contact between the traditional test probe 1 and the solder cap 21, the test probe 1 in the embodiment of the present invention has an open end 13 and may also include a deformable internal cavity structure. The material may include memory metal and alloy. The ratio of the alloy and the memory metal may be determined according to the test probe. The deformation requirement can be flexibly set. It can be known that according to the characteristics of the memory metal, the open end 13 of the test probe 1 can be in contact and conduction with the support column 22 when the preset conditions are met, so that the metal bump to be detected and the test probe 1 can realize signal transmission through the support column 22, that is, the test signal is partially transmitted through the support column 22 to ensure the integrity of the solder cap 21 at its end. In order to ensure the position accuracy between the test probe 1 and the chip to be detected 6, a first positioning piece is provided on the probe bracket, and a second positioning piece is provided on the chip to be detected 6. The test probe 1 and the chip to be detected 6 are precisely positioned by the first positioning piece and the second positioning piece, so that the test probe 1 corresponds to the metal bumps one by one.

[0035] The first positioning member may be at least one alignment hole 31 set on the probe holder, and the second positioning member at this time is a marking object 61 corresponding to the position of the alignment hole 31. When relative displacement occurs between the probes and the chip 6 to be detected, the marking object 61 can be observed through the alignment hole 31. In the direction perpendicular to the probe holder, if the standard mark can be accurately aimed through the alignment hole 31, it indicates that the positions between the two are corresponding. At this time, the positions between the two can be further adjusted along this direction, and finally the contact test is realized. The marking object 61 can be a special color or logo of the chip 6 to be detected.

[0036] It can be seen that the first positioning member and the second positioning member can also be set as compatible structural members such as positioning blocks and grooves. For example, the first positioning member includes at least one positioning block / groove, and the second positioning member at this time is a groove / positioning block that is compatible with the positioning block / groove in position and shape. When the test probe 1 moves to the support column to contact and conduct, the positioning block can be limited in the groove corresponding to the position, that is, through the cooperation of the positioning block and the groove, the position of the chip to be tested and the test probe 1 can be accurately located.

[0037] In a specific embodiment of the present invention, the probe holder can be a DSA chip, and the test probe 1 can be connected to an external test system through the DSA chip. At this time, the through hole is a through hole that passes through the DSA chip, and is aligned with the corresponding marking object 61 to achieve a one-to-one position correspondence between each test probe 1 and each metal bump on the chip 6 to be tested.

[0038] It should be noted that the above-mentioned alignment holes 31 can be set on both sides of the DSA chip, and the corresponding marking objects 61 are set in the area where the metal bumps are not set on the chip to be tested 6, that is, the alignment between the entire test chip and the test probe 1 is achieved through at least two alignment holes 31 at the edge of the chip, such as Figure 3 and Figure 4 As shown; or, the alignment hole 31 can also be set inside each test probe 1, that is, a through hole penetrating the internal cavity is set at the base of the test probe 1 as the alignment hole 31, and the marking object 61 at this time is the solder cap under the corresponding test probe 1, so as to achieve a one-to-one alignment effect, as shown Figure 5 and Figure 6 As shown, if there is a position deviation, the position of the test probe 1 at the corresponding position can be adjusted to ensure the accuracy of each detection position.

[0039] Furthermore, a corresponding camera module 7 can be arranged on the side of the alignment hole 31 away from the marking object 61; wherein, the camera module 7 can capture a real-time position image between the chip to be detected 6 and the test probe 1, so that the test system controls the driving device to adjust the relative position of the chip to be detected 6 and the test probe 1 according to the position image.

[0040] Specifically, the chip testing device of the embodiment of the present invention also includes a driving device for driving the chip to be tested 6 or the test probe 1 to move, and a nozzle head 5 arranged on the driving device; for example, the nozzle head 5 can be adsorbed and fixed on the chip to be tested 6; the relative position between the chip to be tested 6 and the test probe 1 is adjusted according to the position image by the driving device.

[0041] In addition, a pressure sensor can be arranged above the test probe 1. When the test probe contacts the chip protective layer, the pressure sensor can detect a sudden change signal. At this time, it can be confirmed that the test probe has moved to the corresponding position, thereby preventing the test probe from being damaged or broken due to excessive squeezing. That is, double insurance is achieved by the positioning piece and the pressure sensor to improve the test accuracy.

[0042] As a specific example, the above-mentioned preset conditions can be set as temperature conditions, so that the memory metal is in different shapes at different temperatures, thereby completing the connection or disconnection between the test probe 1 and the metal bump; wherein, within the first preset temperature range, the open end 13 of the test probe 1 is opened, and at this time, the test probe 1 can be driven by the driving device to move to the outside of the support column 22, so that the entire metal bump is located in the internal cavity of the test probe 1; the external ambient temperature is changed, so that within the second preset temperature range, the open end 13 of the test probe 1 retracts and clamps the support column 22, and the solder cap 21 at this time is avoided in the internal cavity of the test probe 1, thereby effectively protecting the solder cap 21 structure when the metal bump and the test probe 1 are in contact and conductive.

[0043] The temperature range and shape types of memory metals can be diversified through material design and processing technology. The types of memory metal materials may include:

[0044] 1. Low temperature range materials: able to work in a temperature range as low as -100°C. For example, copper-based alloys (such as Cu-Zn-Al) can exhibit good shape memory effects in low temperature environments;

[0045] 2. Materials in the normal temperature range: For example, nickel-titanium alloy (Nitinol) usually exhibits the best shape memory effect between -50°C and 100°C;

[0046] 3. High temperature range: NiTi alloys with hafnium (Hf) or aluminum (Al) can increase the phase transition temperature to 200°C or even higher. For example, the phase transition temperature of Ni-Ti-Hf alloy can reach 200°C to 400°C;

[0047] 4. Ultra-high temperature range: Iron-based alloys (such as Fe-Mn-Si) also exhibit shape memory effect in the temperature range of 200°C to 400°C. Such materials can be used in extremely high temperature environments.

[0048] In a specific embodiment of the present invention, the memory metal adopts a metal material within the normal temperature range (for example, nickel-titanium alloy). At this time, the first preset temperature can be set to normal temperature, ranging from 0 to 70°C; the range of the second preset temperature is greater than 70°C, and the first preset temperature can also be preferably set to normal temperature, for example, 0 to 40°C, which can ensure that the opening end 13 of the test probe 1 is in an open state at normal temperature, and the size of the opening end 13 after opening is larger than the maximum size of the metal bump, so that the metal bump can penetrate into the internal cavity of the test probe 1. During the test process, the test probe 1 is temperature-controlled and heated or its ambient temperature is changed so that the ambient temperature reaches the second preset temperature range required for the deformation of the test probe 1. At this time, the opening end 13 of the test probe 1 shrinks inward and deforms until it fits with the support column 22.

[0049] Since the solder cap 21 on the chip is usually a spherical structure, and the support column 22 below it is a cylindrical structure, which is adapted to the outer shape of the metal bump, so that the test probe 1 can effectively contact the support column 22 when deformed, the cross-section of the internal cavity of the test probe 1 (parallel to the direction of the chip protective layer) can be set to a circular structure, and it is ensured that the space of the internal cavity has sufficient margin to accommodate the solder cap 21. For example, the difference between the cross-sectional dimensions of the internal cavity and the solder cap 21 ranges from 0 to 50um, and can preferably be set to 0 to 27um. At this time, the collision between the solder cap 21 and the test probe 1 can be effectively avoided, ensuring that the open end 13 of the test probe 1 can be safely avoided in the internal cavity before and after the shrinkage deformation, thereby ensuring the integrity of the solder cap 21.

[0050] In the chip testing device of the embodiment of the present invention, the test probe 1 is a hollow structure having an open end 13, an internal cavity connected to the open end 13, and a base 11 connected to the probe bracket. Furthermore, the open end 13 and the base 11 are connected by an inclined side arm 12, so that when the open end 13 is connected to the support column 22, the solder cap 21 is avoided; within the first preset temperature range, the size of the open end 13 is larger than the size D of the solder cap 21, or further smaller than the size E of the internal cavity. At this time, when the test probe 1 is deformed due to the influence of temperature, since the base 11 is a solid structure, the deformation thereof has little effect on the size. At the same time, under the action of the inclined side arm 12, the deformation of the open end 13 is maximized, thereby achieving the deformation effect of opening outward or contracting inward.

[0051] It should be noted that, in order to prevent the test probe 1 from shrinking or expanding as a whole, which may cause the internal cavity to collide with the solder cap 21, the open end 13 and / or the inclined side arm 12 of the test probe 1 may be made of memory metal material, while the base 11 and other parts may be made of conventional probe materials to ensure that the open end 13 is effectively opened or clamped. The cross section of the base 11 may be set to a rectangular or square shape, so that it is easy to fix on the probe bracket and reduce interference between it and the test probes 1 at other positions.

[0052] In addition, since there will be certain temperature changes during the process of testing the chip through the test probe 1, in order to avoid mutual interference between adjacent test probes 1 or between the test probe 1 and the test chip, an insulating protective layer surrounding the test probe 1 can be set on the outside of the base 11 of the test probe 1. The material and thickness of the insulating protective layer can be set according to the specific probe size, which can play both insulating and protective roles. In addition, the test probe 1 can be connected to an external test system through a PCB, and the chip to be tested 6 is tested through the test system. In other words, the test probe 1 can be fixed on the PCB through a probe holder or the PCB can be directly used as a probe holder. During the test process, the external test system is connected to the test probe 1 through the PCB and the AC-DA chip 8 set on the PCB to achieve the transmission of the test signal.

[0053] Corresponding to the above chip testing device, the present invention also provides a chip testing method, which uses the above chip testing device to test the chip to be tested.

[0054] Figure 7 The schematic flow of the chip testing method according to the embodiment of the present invention is shown.

[0055] like Figure 7 As shown, the chip testing method of the embodiment of the present invention mainly includes the following steps:

[0056] S100: after moving the test probe to above the chip to be tested, aligning the test probe and the chip to be tested by using a first positioning member and a second positioning member;

[0057] S200: Control the test probe to descend or the chip to be tested to ascend until the end of the test probe is located outside the support column;

[0058] S300: Controlling the test probe to be in contact with the support column and conducting when a preset condition is met, and sending a test signal to the chip to be tested through the test probe to complete the test of the chip to be tested.

[0059] Specifically, when using the chip testing device to test the chip to be tested, the probe holder and the test probe thereon are first moved to just above the metal bump on the chip to be tested by a driving device; then, when the open end of the test probe is in an open state, the test probe is controlled to move downward until the first positioning piece and the second positioning piece are aligned with each other, and the open end is located outside the support column of the metal bump; then, the test probe is controlled to be within a second preset temperature range, and due to the characteristics of the memory metal, the open end of the test probe will shrink inward at this time and contact and conduct with the support column, and finally, the external testing system completes the relevant performance detection of the chip through the test probe.

[0060] It should be noted that the embodiments of the above chip testing method can refer to the description in the chip testing device embodiment, which will not be described in detail here.

[0061] According to the chip testing device and method of the present invention, the test probe is set to a cavity structure with an open end, and is combined with a shape-changeable memory metal material so that the open end of the test probe can be deformed accordingly when the preset conditions are met, so that the open end can be in contact and conduct with the support column in a clamping manner, and at the same time, the structure of the first positioning member and the second positioning member is combined to ensure the positional accuracy of each test probe and the metal bump at the corresponding position, and to avoid direct contact between the test probe and the solder cap, so as to achieve conduction between the test probe and the metal bump through the support column, thereby ensuring the integrity of the solder cap and avoiding the chip performance and service life being affected by damage to the solder cap.

[0062] The chip testing device and method according to the present invention are described above by way of example with reference to the accompanying drawings. However, those skilled in the art should understand that various improvements can be made to the chip testing device and method proposed by the present invention without departing from the content of the present invention. Therefore, the protection scope of the present invention should be determined by the content of the attached claims.

Claims

1. A chip testing device, characterized in that: include: A probe holder and a test probe arranged on the probe holder; wherein, The metal bumps of the chip to be tested include support columns arranged on the chip protection layer and solder caps located at the ends of the support columns; The test probe has an open end, and the material includes memory metal. The open end of the test probe contacts and conducts with the support column when a preset condition is met; A first positioning member is arranged on the probe holder, and a second positioning member is arranged on the chip to be tested. The test probe and the chip to be tested are positioned by the first positioning member and the second positioning member so that the test probe corresponds to the metal bumps one by one.

2. The chip testing device according to claim 1, characterized in that: The first positioning member includes at least one alignment hole, and the second positioning member includes a marking corresponding to the position of the alignment hole; The label is a color or mark that is different from the chip to be detected.

3. The chip testing device according to claim 1, characterized in that: The first positioning member includes at least one positioning block / groove, and the second positioning member includes a groove / positioning block corresponding to the position of the positioning block / groove; When the test probe is in contact with the support column, the positioning block is limited in the groove at the corresponding position.

4. The chip testing device according to claim 2, characterized in that: The probe holder is a PCB, and the test probe is connected to an external test system via the PCB; The alignment hole is a through hole that penetrates the DSA chip.

5. The chip testing device according to claim 4, characterized in that: The alignment holes are arranged on both sides of the PCB, and the marking objects are arranged in the area of ​​the chip to be tested where the metal bumps are not arranged; or, The alignment hole is arranged inside each test probe, and the marking object is the solder cap.

6. The chip testing device according to claim 2, characterized in that: A camera module is arranged on the side of the alignment hole away from the marking object; wherein, The camera module is used to capture a position image between the chip to be detected and the test probe, so as to adjust the relative position of the chip to be detected and the test probe according to the position image.

7. The chip testing device according to claim 6, characterized in that: It also includes a driving device for driving the chip to be detected to move and a nozzle head arranged on the driving device; wherein, The nozzle head is adsorbed and fixed on the chip to be detected; The driving device is used to adjust the relative position between the chip to be detected and the test probe according to the position image.

8. The chip testing device according to claim 1, characterized in that: The test probe has a deformable internal cavity structure; The cross section of the cavity structure is a circular structure; and, The difference between the cross-sectional dimensions of the cavity structure and the solder cap ranges from 0 to 50 μm.

9. The chip testing device according to claim 1, characterized in that: The preset condition is that the temperature is greater than 70°C; When the preset condition is not met, the opening end of the test clamp is in an open state, and the size of the opening end is larger than the size of the solder cap.

10. A chip testing method, characterized in that: Using the chip testing device according to any one of claims 1 to 9 to test a chip to be tested, the method comprising: After the test probe is moved to above the chip to be tested, the test probe and the chip to be tested are aligned by a first positioning member and a second positioning member; Control the test probe to descend or the chip to be tested to ascend until the end of the test probe is located outside the support column; The test probe is controlled to contact and conduct with the support column when a preset condition is met, and a test signal is sent to the chip to be tested through the test probe to complete the test of the chip to be tested.

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