FDDS application of FPGA in magnetic suspension controller

Abstract

According to the FDDS application of the FPGA in the magnetic suspension controller, the FPGA and the DSP adopt an SPI communication mode, the DSP controls the FPGA to output digital signals with corresponding amplitudes, frequencies and phases, differential subtraction is carried out on the output signals passing through a bridge circuit to obtain a position relative difference value, whether a magnetic suspension bearing deviates in the direction or not and whether the magnetic suspension bearing deviates in the position or not are judged on the basis of a set warning value, and then the magnetic suspension bearing is subjected to FDDS detection. An alarm is sent to the DSP; and meanwhile, an output signal passing through the bridge circuit is detected and amplified and then is transmitted to an AD (Analog to Digital) of a DSP (Digital Signal Processor) for sampling so as to obtain the position information of the magnetic suspension bearing, and then the DSP performs certain protection or compensation measures on the real-time position information based on the alarm information so as to finish closed-loop adjustment. According to the invention, a zero-setting filter, a digital detector, a digital comparator and the like are realized by using internal resources of the FPGA, the advantages of low cost, low power consumption, high resolution, fast time conversion and the like are realized, and the method has very strong practicability and wide applicability.

Description

Technical Field

[0001] The present invention specifically relates to an FDDS application of FPGA in a magnetic suspension controller, and belongs to the technical field of magnetic suspension bearings. Background Art

[0002] Bearings are important components in contemporary industrial equipment. In rotating machinery, bearings are a very critical component that supports the rotor in the rotating machinery. Without bearings, the rotor cannot rotate freely in a fixed position. Therefore, it determines the performance, quality and reliability of major equipment and host products, and is known as the "heart" of equipment manufacturing.

[0003] Magnetic bearings are a new type of high-performance bearings. Compared with traditional ball bearings, sliding bearings and oil film bearings, magnetic bearings do not have mechanical contact, and the rotor can reach a very high speed. They have the advantages of low mechanical wear, low energy consumption, low noise, long life, no lubrication, and no oil pollution. They are particularly suitable for special environments such as high speed, vacuum, and ultra-clean. They can be widely used in mechanical processing, turbomachinery, aerospace, vacuum technology, rotor dynamics characteristics identification and testing, and other fields, and are recognized as a very promising new type of bearing.

[0004] The DDS signal generator uses direct digital synthesis (DDS) technology to improve the frequency stability and accuracy of the signal generator to the same level as the reference frequency, and can perform fine frequency adjustment in a wide frequency range. The signal source designed using this method can work in a modulation state, adjust the output level, and output various waveforms.

[0005] The current DDS chips are relatively expensive, and in the magnetic levitation controller composed of FPGA and DSP dual cores, the functions are relatively overlapping, the output range of the DDS chip is relatively fixed, and the passband is relatively narrow.

[0006] The existing technology has a large demand on the ROM resources of FPGA, which can generally meet the waveform synthesis of sine wave, triangle wave, sawtooth wave and square wave, but the sampling accuracy still depends on the reliability of the subsequent filtering circuit.

[0007] Therefore, it is necessary to provide an FDDS application of FPGA in a magnetic levitation controller. Summary of the invention

[0008] In order to solve the deficiencies of the prior art, the object of the present invention is to provide an FDDS application of FPGA in a magnetic levitation controller.

[0009] In order to achieve the above object, the present invention adopts the following technical solution:

[0010] An FDDS application of FPGA in a magnetic levitation controller includes the following steps:

[0011] S1, DSP controls FPGA to output the signal fed back by the magnetic bearing sensor as an FDDS signal with corresponding amplitude, frequency and phase;

[0012] S2, FDDS signal is output to the bridge circuit, the bridge circuit outputs the difference, and then amplified, the amplified signal is zeroed and filtered;

[0013] S3, the output signal after zero adjustment and filtering is amplified to the range that can be collected by the AD sampling port after detection for DSP to sample;

[0014] S4, the output signal after zeroing and filtering is compared with the set warning value signal by the digital comparator to determine whether the magnetic bearing is offset in direction and position, and send an alarm to the DSP;

[0015] S5. Based on the sampling information and the alarm information, DSP adjusts the position of the magnetic bearing.

[0016] The generation of the above FDDS signal includes the following steps:

[0017] A1. Determine the waveform sampling point, generate a file with the ideal waveform, use the ROM IP core, and store the file data in ROM;

[0018] A2. DSP controls FPGA to output the corresponding frequency control word through communication, changes the accumulation progress of the phase accumulator, indirectly controls the ROM reading speed, and thus controls the frequency of the output waveform;

[0019] A3. DSP controls FPGA to output the corresponding phase control word through communication, changes the phase modulator, and indirectly controls the initial value read by ROM, thereby controlling the initial value of the output waveform, that is, the phase parameter;

[0020] A4. DSP defines the amplitude control parameter Z through communication. When reading the value in the ROM address through the waveform lookup table, it uses a multiplier to multiply it by Z to control the amplitude of the FPGA output waveform.

[0021] A5. Finally, after D / A conversion, it is the output FDDS signal.

[0022] The application according to claim 2 is characterized in that the detection adopts an internal digital filter of FPGA.

[0023] The above zeroing filtering is implemented by FPGA.

[0024] The above digital comparator is an internal resource of FPGA.

[0025] The present invention is beneficial in that:

[0026] The present invention uses an FPGA in a magnetic suspension controller for FDDS. The FPGA and DSP use SPI communication. The DSP controls the FPGA to output digital signals of corresponding amplitude, frequency, and phase. The output signals after passing through the bridge circuit are then differentially subtracted to obtain the relative position difference. Based on the set warning value, the direction and position of the magnetic suspension bearing are determined to be offset, and an alarm is issued to the DSP. At the same time, the output signal after passing through the bridge circuit is detected and amplified and then transmitted to the DSP for AD sampling to obtain the position information of the magnetic suspension bearing. The DSP then performs certain protection or compensation measures on the real-time position information based on the alarm information to complete the closed-loop regulation. It has the following advantages:

[0027] 1. The present invention adopts digital programmable devices to form corresponding circuits, which have great operability. Except for the necessary amplifier, other components such as FDDS, zero adjustment filter, digital detector, and digital comparator are all digital circuits, which are all realized by using the internal resources of FPGA.

[0028] Compared with traditional frequency synthesizers, FDDS has the advantages of low cost, low power consumption, high resolution and fast conversion time. It is widely used in the fields of telecommunications and electronic instruments and is a key technology for achieving full digitalization of equipment. The controllable range and space are wider than those of traditional DDS chips. Since FPGA is used for signal output, the signal generation and output modules are all programmable, so it has better flexibility and scalability.

[0029] Moreover, through communication, FPGA can output ideal signals, and the adjustable range is much higher than that of DDS chip. It also has the advantages of low cost, low power consumption, high resolution and fast conversion time, which plays a very important role in digital signal processing and its hardware implementation.

[0030] 2. Analog circuits are mostly affected by noise, etc., resulting in low stability and reliability. If analog filters are used, more components such as operational amplifiers, resistors, and capacitors will be added, making the circuit board layout bloated, with less space and higher costs. The digital filter used in the present invention has high reliability, giving engineers more filtering options and more flexible filtering methods.

[0031] 3. The circuit of the present invention is simple and reliable, which reduces the design cost and power consumption of the measurement circuit and improves the reliability of the sensor. The frequency, phase and amplitude of the carrier source signal are stable and are not affected by environmental factors such as external temperature. The digital demodulation module completely replaces the hardware detection circuit, has a reliable design, is not affected by external interference, and has no errors caused by its own noise; there is no distortion and zero drift caused by hardware circuit parameter design.

[0032] 4. FPGA can process multiple signals in parallel, and phase delay can be minimized; the sensor bandwidth is high, which fully meets the application of magnetic bearings; digital demodulated data can be directly transmitted to the controller inside the chip, effectively improving the system response speed.

[0033] Although this architecture is limited by the FPGA clock frequency (60MHz) and the analog-to-digital conversion frequency (60MHz), the maximum carrier source frequency can only be designed to be on the order of 1MHz, but it still has lower latency, better demodulation speed and performance than the digital demodulation of the FM sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is the framework diagram of FDDS signal output.

[0035] Figure 2 This is the flow chart of FDDS signal.

[0036] Figure 3 Schematic diagram of the circuit structure of the bridge circuit.

[0037] Figure 4 This is the amplitude adjustment waveform.

[0038] Figure 5 To adjust the frequency waveform.

[0039] Figure 6 To adjust the waveform phase diagram.

[0040] Figure 7 This is the detection measurement diagram.

[0041] Figure 8 This is the filter measurement diagram. DETAILED DESCRIPTION

[0042] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] Working principle: The stable dynamic suspension of the magnetic suspension bearing requires constant detection of the magnetic suspension sensor. By giving the magnetic suspension sensor circuit a corresponding excitation signal and collecting the bearing sensor voltage value, the suspension condition of the bearing and whether there is any offset can be determined.

[0044] An FDDS application of FPGA in a magnetic levitation controller includes the following steps:

[0045] S1, DSP controls FPGA to output the signal fed back by the magnetic bearing sensor as an FDDS signal with corresponding amplitude, frequency and phase, specifically:

[0046] DDS is mainly composed of a phase accumulator, a phase modulator, and a waveform lookup table.

[0047] A1. First, use the waveform generation software to generate the ideal waveform file (the file format is determined by the chip), and use the ROM IP core to store the file data in ROM.

[0048] Second, determine the waveform sampling points:

[0049] Assume that the output signal is divided into 64 sampling points, and each sampling point is sampled with a period of 1ms. Therefore, the output signal is 64ms / T (period), so its output frequency is

[0050] It can be seen that the output frequency can be adjusted by adjusting the clock frequency and the number of samples. However, it is difficult to adjust the clock frequency. This is because adjusting the clock frequency will bring unknown interference and whether the two clocks are synchronized will bring many system errors and affect stability and reliability. Adjusting the number of samples is also a troublesome thing, because the number of samples of FDDS is determined when the waveform file is generated and stored in ROM. If you want to modify it, you need to modify the ROM, but it is not advisable to modify the ROM in a product.

[0051] A2. Introduce a controllable variable F_WORD (frequency control word) in frequency control, then the above formula can be modified to

[0052] DSP controls FPGA to output the corresponding frequency control word through communication, changes the accumulation progress of the phase accumulator, and indirectly controls the ROM reading speed, thereby controlling the frequency of the output waveform, that is, achieving the purpose of controlling the frequency.

[0053] A3. DSP controls FPGA to output the corresponding phase control word P_WORD through communication, changes the phase modulator, and indirectly controls the initial value read by ROM, thereby controlling the initial value of the output waveform, that is, the phase parameter; that is, achieving the purpose of controlling the phase parameter of the output signal.

[0054] Assuming that the word length of the phase adder is M, when the phase control word jumps from 0 to P_WORD, the read value in the ROM is the sum of the output of the phase accumulator and the phase control word P_WORD, so the phase of its output will increase by P_WORD / 2M, causing the output signal to produce a phase shift. In this way, the waveform sampling value stored in the ROM can be found by looking up the table, and the phase change is completed. The N-bit addressing ROM is equivalent to discretizing the 0-360° sinusoidal signal into a sequence of 2N sample values. If there are D-bit data bits in the ROM, the amplitudes of the 2N sample values ​​are solidified in the ROM as D-bit binary values. The amplitude of the sinusoidal signal of the corresponding phase can be output according to the different addresses.

[0055] A4. Amplitude control You can define an amplitude control parameter Z. When reading the value in the ROM address, use a multiplier to multiply it by Z.

[0056] A5. Finally, after D / A conversion (digital-to-analog converter), the output is the FDDS signal; FDDS has certain requirements on the resolution of the digital-to-analog converter. The higher the resolution, the more steps of the synthesized sine wave, and the higher the output waveform accuracy.

[0057] S2, FDDS signal is output to the bridge circuit, and after passing through the bridge, it is as shown in the following formula:

[0058]

[0059] In the formula, L1 and L2 are equivalent inductors, L1=L2=L; R1 and R2 are equivalent resistors, R1=R2=R; u0 + 、u0 - The response signal output by the measurement circuit should also be a standard sine wave.

[0060] The output signal after passing through the bridge is differentiated to obtain its relative position difference. Since the output signal difference is very small, it needs to be amplified and then sent to the FPGA for zero adjustment and filtering. At this time, the signal already carries the inductor position information.

[0061] The instrumentation amplifier is a special differential amplifier with ultra-high input impedance, extremely strong common-mode rejection ratio, low input drift, and low output impedance. Therefore, it is suitable for the output of this circuit.

[0062] The amplified signal is input to the FPGA for zero adjustment and filtering to further eliminate the error of the instrumentation amplifier output. The filter uses the digital filter inside the FPGA.

[0063] S3, the output signal after zero adjustment and filtering is then detected. However, if the weak signal after detection is directly connected to the AD sampling port, it will lead to low accuracy and large error. Therefore, an analog operational amplifier is used to amplify the signal to the range that the AD sampling port can collect for DSP sampling.

[0064] Common hardware circuit detection generally uses analog multiplier synchronous detection and envelope detection, etc. These two detection modes can be digitally implemented through FPGA programming. Since the use of multipliers consumes a lot of resources in hardware circuits, the calculation consumes a long clock, and the output phase delay of the measurement results is large, this solution uses a more suitable voltage doubler envelope detection mode to achieve digital design.

[0065] S4. The output signal after zeroing and filtering is compared by the digital comparator according to the set warning value signal to determine whether the magnetic bearing is offset in direction and position, and issue an alarm to the DSP; that is, when the signal generated when the bearing deviates in a certain direction and position is greater than the signal generated at a warning position, a warning signal is output to the main chip through the digital comparator, which means that the bearing is out of the safe position.

[0066] S5. Based on the sampling information and the alarm information, DSP adjusts the position of the magnetic bearing.

[0067] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any form, and any technical solution obtained by equivalent replacement or equivalent transformation falls within the protection scope of the present invention.

Claims

1. An FDDS application of FPGA in a magnetic levitation controller, characterized in that: The following steps are involved: S1, DSP controls FPGA to output the signal fed back by the magnetic bearing sensor as an FDDS signal with corresponding amplitude, frequency and phase; S2, FDDS signal is output to the bridge circuit, the bridge circuit outputs the difference, and then amplified, the amplified signal is zeroed and filtered; S3, the output signal after zero adjustment and filtering is amplified to the range that can be collected by the AD sampling port after detection for sampling by the DSP; S4, the output signal after zeroing and filtering is compared with the set warning value signal by the digital comparator to determine whether the magnetic bearing is offset in direction and position, and send an alarm to the DSP; S5. Based on the sampling information and the alarm information, DSP adjusts the position of the magnetic bearing.

2. The use according to claim 1, characterized in that: The generation of the FDDS signal comprises the following steps: A1. Determine the waveform sampling point, generate a file with the ideal waveform, use the ROM IP core, and store the file data in ROM; A2. DSP controls FPGA to output the corresponding frequency control word through communication, changes the accumulation progress of the phase accumulator, indirectly controls the ROM reading speed, and thus controls the frequency of the output waveform; A3. DSP controls FPGA to output the corresponding phase control word through communication, changes the phase modulator, and indirectly controls the initial value read by ROM, thereby controlling the initial value of the output waveform, that is, the phase parameter; A4. DSP defines the amplitude control parameter Z through communication. When reading the value in the ROM address through the waveform lookup table, it uses a multiplier to multiply it by Z to control the amplitude of the FPGA output waveform. A5. Finally, after D / A conversion, it is the output FDDS signal.

3. The use according to claim 1, characterized in that: The detection adopts the digital filter inside the FPGA.

4. The use according to claim 1, characterized in that: The zeroing filter is implemented by FPGA.

5. The use according to claim 1, characterized in that: The digital comparator is an internal resource of the FPGA.

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