CXL memory module, memory repair method, control chip, medium and system

Abstract

A CXL memory module, a memory repair method, a control chip, a medium and a system, which relate to the technical field of data access, wherein the CXL memory module comprises a control chip and one or more memory chips managed by the control chip, and the available storage space of the one or more memory chips comprises multiple areas; the control chip is configured to: in the working process, take each of the multiple areas as a to-be-detected area in turn to determine whether there is an unreliable storage unit in the to-be-detected area; when the to-be-detected area is in an idle state, directly perform a failure detection on the to-be-detected area; when the to-be-detected area is in a used state, copy the data in the to-be-detected area to a target area, record the address mapping relationship between the to-be-detected area and the target area, and then perform a failure detection on the to-be-detected area; if there is an unreliable storage unit, replace the unreliable storage unit with a predetermined redundant storage unit and record it.

Description

Technical Field

[0001] The disclosed embodiments relate to the field of CXL memory modules, and in particular to a CXL memory module, a memory repair method, a control chip, a medium, and a system. Background Art

[0002] CXL (Compute Express Link) is a new memory interface protocol based on the PCIe (Peripheral Component Interconnect Express) physical layer. Based on the CXL protocol, CXL memory modules can expand the computer's memory. CXL memory modules usually include a CXL control chip and the memory chips it manages.

[0003] In practice, when a memory chip is manufactured, some of its memory cells may be unreliable. Memory chips need to be tested before leaving the factory to detect unreliable memory cells, replace them with predetermined redundant memory cells, and then burn the replacement information into the eFuse (one-time programmable) inside the chip.

[0004] However, since the stress accumulated inside the chip during the production of integrated circuits takes a long time to release, the first six months after the memory chip leaves the factory are the most prone to failures, and these hidden dangers cannot be detected on the production line. For application areas such as data centers that require high reliability of data storage, the failure of memory chips during use is a great problem, and since the servers in data centers need to run continuously, they are usually not shut down for years. Therefore, how to repair the memory while the server is running is an urgent problem to be solved. Summary of the invention

[0005] Embodiments of the present disclosure provide a CXL memory module, a memory repair method, a control chip, a medium, and a system.

[0006] In a first aspect, an embodiment of the present disclosure provides a CXL memory module, comprising a control chip and one or more memory chips managed by the control chip, wherein the available storage space of the one or more memory chips comprises multiple areas; the control chip is configured to: in a working process, sequentially use each of the multiple areas as an area to be detected to determine whether there is an unreliable storage unit in the area to be detected; when the area to be detected is in an idle state, directly perform a failure detection on the area to be detected; when the area to be detected is in use, copy the data in the area to be detected to a target sub-area, record the address mapping relationship between the area to be detected and the target area, and then perform a failure detection on the area to be detected; when there is an unreliable storage unit in the area to be detected, replace the unreliable storage unit with a predetermined redundant storage unit and record it.

[0007] In a second aspect, an embodiment of the present disclosure provides a memory repair method, which is applied to a CXL memory module. The CXL memory module includes a control chip and one or more memory chips managed by the control chip, and the available storage space of the one or more memory chips includes multiple areas; the method includes: during the operation of the CXL memory module, each sub-area in the multiple areas is taken as a to-be-detected area in turn to determine whether there is an unreliable storage unit in the to-be-detected area; when the to-be-detected area is in an idle state, directly performing a failure detection on the to-be-detected area; when the to-be-detected area is in use, copying the data in the to-be-detected area to the target area, and recording the address mapping relationship between the to-be-detected area and the target area, and then performing a failure detection on the to-be-detected area; when there is an unreliable storage unit in the to-be-detected area, replacing the unreliable storage unit with a predetermined redundant storage unit and recording it.

[0008] In a third aspect, an embodiment of the present disclosure provides a control chip applied to a CXL memory module. The CXL memory module also includes one or more memory chips managed by the control chip. The processor of the control chip is configured to execute the memory repair method in the above embodiment.

[0009] In a fourth aspect, a non-volatile computer storage medium is provided in an embodiment of the present disclosure, and the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the memory repair method in the above embodiment is implemented.

[0010] In a fifth aspect, an embodiment of the present disclosure provides a computer system, comprising a host and the CXL memory module in the above embodiment, wherein the host communicates with the CXL memory module via a CXL interface to achieve discovery, configuration and data transmission of the CXL memory module, and the CXL memory module is configured to repair unreliable storage cells in a memory chip during runtime.

[0011] The CXL memory module of the disclosed embodiment, during operation, sequentially uses each of the multiple areas included in the available storage space as a to-be-detected area to determine whether there is an unreliable storage unit in the to-be-detected area; when the to-be-detected area is in an idle state, the to-be-detected area is directly subjected to failure detection; when the to-be-detected area is in use, the data in the to-be-detected area is first copied to the target area, and the address mapping relationship between the to-be-detected area and the target area is recorded, and then the to-be-detected area is subjected to failure detection; when there is an unreliable storage unit in the to-be-detected area, the unreliable storage unit is replaced with a predetermined redundant storage unit and recorded. The memory chip can be repaired during the operation of the CXL memory module, which helps to improve the reliability of the CXL memory module in processing data.

[0012] Other features and advantages of the present disclosure will be described in the following description, and partly become clearer from the description, or understood by implementing the present disclosure. Other advantages of the present disclosure can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0014] Figure 1 A schematic diagram of the structure of an embodiment of a CXL memory module disclosed herein;

[0015] Figure 2 is a structural schematic diagram of another embodiment of the CXL memory module disclosed in the present invention;

[0016] Figure 3 A flowchart of an embodiment of the memory repair method disclosed in the present invention;

[0017] Figure 4 A flowchart of another embodiment of the memory repair method disclosed herein;

[0018] Figure 5 A schematic diagram of the structure of an embodiment of a control chip disclosed in the present invention;

[0019] Figure 6 A schematic diagram of the structure of a computer system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the present disclosure more clear, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present disclosure can be combined with each other arbitrarily without conflict.

[0021] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0022] In the present disclosure, ordinal numbers such as “first” and “second” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0023] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0024] like Figure 1 As shown, an embodiment of the present disclosure provides a CXL memory module, which may include a control chip 110 and one or more memory chips 120 managed by it. Generally, the control chip 110 may also be referred to as a CXL controller, on which a CXL interface based on the CXL protocol may be provided, so that the host CPU (Host CPU) interacts with the control chip 110 through the CXL interface. For example, based on the CXL.io protocol, the host CPU may send instructions to the control chip 110; based on the CXL.mem protocol, the host CPU may read data from the memory chip 120, and write external data to the memory chip 120. A DDR (Double Data Rate) controller is also provided on the control chip 110, so that the CPU of the control chip 110 manages the memory chip 120.

[0025] The memory chip 120 may be a DRAM (Dynamic Random Access Memory) chip, for example. The available storage space of one or more memory chips 120 may be configured to include multiple regions, each region corresponding to a physical storage address. An unreliable storage unit refers to a storage unit in the memory chip 120 that cannot work properly.

[0026] The control chip 110 can be configured as follows: during operation, each of the multiple areas is taken as an area to be detected in turn to determine whether there is an unreliable storage unit in the area to be detected; when the area to be detected is in an idle state, failure detection is directly performed on the area to be detected; when the area to be detected is in use, the data in the area to be detected is copied to the target area, and the address mapping relationship between the area to be detected and the target area is recorded, and then failure detection is performed on the area to be detected; when there is an unreliable storage unit in the area to be detected, the unreliable storage unit is replaced with a predetermined redundant storage unit and recorded.

[0027] In this embodiment, the control chip 110 may be pre-loaded with a failure detection algorithm, which may include, for example, repeated write and read tests. When the processor of the control chip 110 runs the failure detection algorithm, it may test the parameters of the storage unit in the memory chip 120 (such as data retention time, read and write timing, etc.) to determine whether the storage unit is an unreliable storage unit. For example, when some parameters of the storage unit do not have sufficient redundancy, the storage unit may be determined to be an unreliable storage unit.

[0028] The control chip 110 can determine one area from multiple areas as the area to be detected each time, and detect the area to be detected through a failure detection algorithm to determine whether there is an unreliable storage unit in the area to be detected. In the case where the area to be detected is stored in an unreliable storage unit, the unreliable storage unit is replaced with a redundant storage unit to repair the area to be detected. Then, a new area to be detected is determined from the remaining sub-areas, and the failure detection and repair operations are performed again until all areas are detected.

[0029] In some optional implementations of this embodiment, the control chip 110 may also be configured to: determine each of the multiple sub-areas as a to-be-detected area in turn at every preset period, so as to periodically perform failure detection and repair on the available storage space of the chip 120. In this way, failure detection and repair can be performed on the memory chip periodically.

[0030] In some optional implementations of this embodiment, the control chip may determine the area to be detected in the following manner: preferentially determine a sub-area in an idle state among multiple sub-areas as the area to be detected.

[0031] As an example, the control chip 110 may first detect whether all areas are in use. For example, the control chip 110 may determine whether an area is in use based on the access record of the area. An area that has no access operation within a predetermined time period may be regarded as an idle sub-area, and an area that has been accessed (including writing data or reading data) within a predetermined time period is in use. Then, a random area is selected from the idle area as the area to be detected. After the current area to be detected is repaired, the next area to be detected is selected from the remaining idle areas. When there is no sub-area in an idle state, the area to be detected is selected from the sub-area in use until all areas are detected and repaired.

[0032] In this embodiment, the control chip 110 may adopt different detection methods according to whether the area to be detected is in use.

[0033] When the area to be detected is in an idle state (ie, unused state), the control chip 110 may directly perform a failure detection on the area to be detected to determine whether there is an unreliable storage unit in the area to be detected.

[0034] When the area to be detected is in use, in order to avoid data loss in the area to be detected due to failure detection, the control chip 110 can first copy the data in the area to be detected to the target area, and then perform failure detection on the area to be detected. Here, the target area refers to an area used to store data in the area to be detected. Before starting the detection, an unused area can be determined from multiple areas in advance as the target area, or it can be selected from the detected area during the detection process.

[0035] After copying the data in the area to be detected to the target area, the control chip 110 may record the address mapping relationship between the area to be detected and the target area, for example, the mapping relationship between the physical storage address of the area to be detected in the memory chip 120 and the physical storage address of the target area in the memory chip 120. When the area to be detected is subsequently repaired, if an instruction to access the area to be detected is received, the control chip 110 may map the physical address carried in the instruction to the target area based on the address mapping relationship, and then access the data in the target area. In this way, the normal operation of the CXL memory module will not be affected during the process of repairing the memory chip 120.

[0036] In some embodiments, each memory chip 120 is provided with a redundant storage area and a replacement relationship table; the CXL memory module can implement the replacement processing of the unreliable storage unit in the following manner: the control chip 110 sends a replacement instruction to the memory chip 120 where the unreliable storage unit is located, and the replacement instruction carries the address information of the unreliable storage unit; the memory chip 120 is configured to: in response to the replacement instruction, replace the unreliable storage unit with the redundant storage unit in the redundant storage area, and record the address correspondence between the redundant storage unit and the unreliable storage unit in the replacement relationship table.

[0037] In this embodiment, under the control of the control chip, the memory chip itself can complete the replacement process of the unreliable storage unit, which helps to improve the repair efficiency of the CXL memory module.

[0038] In other embodiments, the plurality of memory chips 120 may also be provided with a first storage space outside the available storage space; the control chip 110 may implement the replacement processing of the unreliable storage unit in the following manner: replace the unreliable storage unit with the redundant storage unit in the first storage space, and record the address correspondence between the redundant storage unit and the unreliable storage unit.

[0039] As an example, after the control chip 110 detects an unreliable storage unit in the area to be detected, the unreliable storage unit in the area to be detected can be replaced with a redundant storage unit in the first storage space, and the address correspondence between the unreliable storage unit and the redundant storage unit can be recorded as a replacement relationship between the two, and stored in the eFuse or flash memory. When the unreliable storage unit is subsequently accessed, the control chip 110 can access the corresponding redundant storage unit according to the replacement relationship, thereby realizing the repair processing of the area to be detected.

[0040] In this embodiment, the redundant storage units in the first storage space are shared by multiple memory chips 120. Thus, the control chip 110 can replace unreliable storage units in multiple memory chips 120 with redundant storage units in the first storage space, facilitating centralized management and control of redundant storage units.

[0041] In some optional implementations of this embodiment, while the first storage space is set in the CXL memory module, each memory chip 120 may also be provided with a redundant storage area, and the control chip 110 may implement the replacement of unreliable storage units in any of the above two ways. As an example, the control chip 110 may preferentially replace unreliable storage units by repairing the memory chip 120 itself, and when the redundant storage area in the memory chip 120 is insufficient, the redundant storage unit in the first storage space may be used for replacement. This helps to improve the flexibility of the CXL memory module in repairing memory.

[0042] In one example, when redundant memory cells are used to replace unreliable memory cells in the area to be detected, the control chip 110 or the memory chip 120 can replace the rows or columns where the unreliable memory cells are located with rows or columns composed of redundant memory cells in units of rows or columns, and record the address correspondence between the rows or columns where the unreliable memory cells are located and the rows or columns composed of redundant memory cells as a replacement relationship, so that when the rows or columns where the unreliable memory cells are located are subsequently accessed, the rows or columns composed of redundant memory cells can be accessed according to the replacement relationship, thereby realizing the repair of the unreliable memory cells in the memory chip 120 in units of rows or columns.

[0043] In another example, the smallest unit for reading and writing data in the CXL memory module is a word (i.e., containing multiple bytes). The control chip 110 or the memory chip 120 can replace the word where the unreliable storage unit is located with a word composed of redundant storage units in units of words. At this time, the replacement relationship can be the address correspondence between the word where the unreliable storage unit is located and the word composed of redundant storage units.

[0044] The CXL memory module of the disclosed embodiment, during the operation of the CXL memory module, sequentially uses each of the multiple areas included in the available storage space of the memory chip as a to-be-detected area to determine whether there is an unreliable storage unit in the to-be-detected area; when the to-be-detected area is in an idle state, directly perform failure detection on the to-be-detected area; when the to-be-detected area is in use, first copy the data in the to-be-detected area to a predetermined target area, and record the address mapping relationship between the to-be-detected area and the target area, and then perform failure detection on the to-be-detected area; when there is an unreliable storage unit in the to-be-detected area, replace the unreliable storage unit with a predetermined redundant storage unit, and record the replacement relationship between the redundant storage unit and the unreliable storage unit. The memory chip can be repaired during the operation of the CXL memory module, which helps to improve the reliability of the CXL memory module in processing data.

[0045] In some embodiments, after copying the data in the area to be detected to a predetermined target area and recording the address mapping relationship between the area to be detected and the target area, the control chip is further configured to: access the target area based on the address mapping relationship when receiving an access instruction to access the area to be detected.

[0046] In this embodiment, after determining the address mapping relationship between the area to be detected and the target area, when the control chip 110 receives an access instruction to access the area to be detected, the address to be accessed carried in the access instruction can be converted into a corresponding address in the target area according to the address mapping relationship, and then the target area is accessed according to the converted address. Before the unreliable storage unit in the area to be detected is replaced with a redundant storage unit, the parallel processing of memory chip repair and memory access can be realized.

[0047] As an example, the address mapping relationship may include a correspondence between the memory address of the area to be detected and the memory address of the target area. The access instruction may be a read data instruction or a write data instruction sent by the host, which carries the external physical address to be accessed (i.e., the address carried in the instruction sent by the host CPU to the CXL module via the address bus). The control chip of the CXL module can extract the external physical address from the access instruction and convert the external physical address into a memory address (i.e., the physical address of the storage unit in the memory chip) through proprietary hardware (e.g., an address translator). Here, the converted memory address points to the area to be detected. Afterwards, the control chip can search for the memory address corresponding to the memory address in the address mapping relationship. Here, the corresponding memory address points to the target area. The control chip can access the corresponding memory address to implement access processing for the area to be detected.

[0048] In some embodiments, the CXL memory module can also use virtual memory to manage the memory usage of each task. In this case, the address information carried in the host-side memory access instruction is a virtual address, and the control chip can translate the virtual address into a physical address and then access the corresponding storage unit. Figure 2 As shown, the control chip 210 has a virtual address translation table 211, which may include a correspondence between virtual addresses and physical addresses. The control chip 210 may access multiple memory chips 220 according to the virtual addresses carried in the access instructions through translation hardware 212 (such as a virtual address manager).

[0049] In this embodiment, after copying the data in the area to be detected to a predetermined target area and recording the address mapping relationship between the area to be detected and the target area, the control chip 210 is also configured to: based on the address mapping relationship, modify the physical address of the area to be detected in the address translation table to the physical address of the target area.

[0050] In one example, the physical address in the virtual address translation table 211 may be an external physical address. After the control chip 110 translates the virtual address in the access instruction into the external physical address, it converts the external physical address into a memory address, and then accesses the memory chip 220 according to the memory address. At this time, the control chip 210 may modify the external physical address corresponding to the area to be detected in the virtual address translation table to the external physical address of the target area. In this way, when receiving an access instruction for the area to be detected during the process of repairing the area to be detected and after the repair is completed, the control chip 210 may translate the virtual address carried in the access instruction into the external physical address of the target area according to the virtual address translation table, and then map the memory access processing (for example, which may include writing data or reading data) for the area to be detected to the target area.

[0051] In another example, the physical address in the virtual address translation table 211 may be a memory address, and the control chip 210 may directly translate the virtual address in the access instruction into the memory address to access the memory chip 220. At this time, the control chip 210 may modify the memory address of the area to be detected in the virtual address translation table 211 into the memory address of the target area, so that when the access instruction for the area to be detected is received during the process of repairing the area to be detected and after the repair is completed, the control chip 210 may translate the virtual address carried in the access instruction into the memory address of the target area according to the virtual address translation table, and then map the memory access processing for the area to be detected to the target area.

[0052] In this embodiment, a virtual address translation table is stored in the control chip. Before repairing the area to be detected, the physical address of the area to be detected in the virtual address translation table is modified to the physical address of the target area. The virtual address can be used to switch and map the area to be detected and the target area, and then the memory access processing of the area to be detected during and after the repair process is mapped to the target area, which helps to improve the access efficiency of the memory during the memory repair process.

[0053] In some optional implementations of any of the above embodiments, after the data in the area to be detected is copied to the target area, when the failure detection or repair of the area to be detected is completed, the data may no longer be copied back to the area to be detected, but the target area is used as the storage location of the data, and subsequent access operations to the data are mapped to the target area. At this time, a new target area can be re-determined for subsequent other areas, so that the number of data copies in the memory chip can be reduced, which helps to reduce the energy consumption of the CXL memory module.

[0054] In this embodiment, the control chip is further configured to: during operation, always reserve one or more free areas in the available storage space as initial target areas for failure detection.

[0055] Here, the initial target area may be predetermined, and the control chip 211 may store data in the initial target area at the initial stage of failure detection, and may subsequently determine a new target area during the detection process.

[0056] In an optional example, when the control chip 211 is configured to sequentially use each of multiple areas as an area to be detected, the initial target area can be first used as the area to be detected; when there are no unreliable storage units in the initial target area, the initial target area is used as the target area for subsequent failure detection of other areas.

[0057] In this example, the initial target area can be first tested for failure, and the reliable initial target area that has passed the test can be used as the target area for failure detection in other areas. This can avoid storing data in the unreliable initial target area, which helps to further improve the reliability of the data.

[0058] In another optional example, the control chip 211 is further configured to: when there is no unreliable storage unit in the area to be detected, use the area to be detected as a target area for subsequent failure detection of other areas.

[0059] In this example, the detected reliable area (that is, the area without unreliable storage units) can be used as the target area for subsequent detection of other areas.

[0060] In some other optional implementations of any of the above embodiments, after replacing the unreliable storage unit with a redundant storage unit, the data in the target area can be copied back to the area to be detected to clear the target area. In this way, when other areas are detected subsequently, the target area can still be used to store data.

[0061] In an example of implementation, after replacing the unreliable storage unit with a predetermined redundant storage unit, the control chip 211 is further configured to copy the data in the target area back to the area to be detected and delete the address mapping relationship.

[0062] In this embodiment, in order to repair the memory chip during the operation of the CXL memory module, the memory access processing for the area to be detected during the repair process is mapped to the target area. After the repair of the area to be detected is completed, the data in the target area is copied to the area to be detected, which can ensure the timeliness of the data in the area to be detected and avoid the loss of data processing caused by repairing the memory chip. In another example of this embodiment, when the CXL memory module adopts a virtual address, after replacing the unreliable storage unit with a predetermined redundant storage unit, the control chip 211 can also be configured to: copy the data in the target area back to the area to be detected; based on the address mapping relationship, modify the physical address of the target area in the virtual address translation table to the physical address of the area to be detected.

[0063] In this embodiment, after the repair is completed (i.e., the unreliable storage unit is replaced), the control chip can modify the physical address of the target area of ​​the virtual address translation table to the physical address of the area to be detected, so that the repaired area to be detected can be directly accessed according to the virtual address.

[0064] The disclosed embodiment also provides a memory repair method, which is applied to a CXL memory module, wherein the CXL memory module includes a control chip and one or more memory chips managed by the control chip, and the available storage space of the one or more memory chips includes multiple areas. Figure 3 As shown, the method includes the following steps.

[0065] Step 310: During the operation of the CXL memory module, each of the plurality of regions is sequentially used as a region to be detected to determine whether there is an unreliable storage unit in the region to be detected.

[0066] In some optional implementations of this embodiment, step 310 may determine the area to be detected in the following manner: preferentially determine an area in an idle state among multiple areas as the area to be detected.

[0067] Step 320: When the area to be detected is in an idle state (ie, not in use), directly perform failure detection on the area to be detected.

[0068] Step 330: When the area to be detected is in use, copy the data in the area to be detected to a predetermined target area, record the address mapping relationship between the area to be detected and the target area, and then perform failure detection on the area to be detected.

[0069] Step 340: When there is an unreliable storage unit in the area to be detected, replace the unreliable storage unit with a predetermined redundant storage unit and record the replacement.

[0070] The memory repair method of the disclosed embodiment, during the operation of the CXL memory module, sequentially uses each of the multiple areas included in the available storage space as a to-be-detected area to determine whether there is an unreliable storage unit in the to-be-detected area; when the to-be-detected area is in an idle state, directly perform a failure detection on the to-be-detected area; when the to-be-detected area is in use, first copy the data in the to-be-detected area to the target area, and record the address mapping relationship between the to-be-detected area and the target area, and then perform a failure detection on the to-be-detected area; when there is an unreliable storage unit in the to-be-detected area, replace the unreliable storage unit with a predetermined redundant storage unit and record it. The memory chip can be repaired during the operation of the CXL memory module, which helps to improve the reliability of the CXL memory module in processing data.

[0071] In some optional implementations of this embodiment, the above step 310 may further include: taking each of the multiple areas as a to-be-detected area in turn at every preset period, so as to implement periodic detection and repair of the memory chip.

[0072] In some optional implementations of the present embodiment, each of the multiple memory chips is provided with a redundant storage area and a replacement relationship table; the above-mentioned step 340 includes: sending a replacement instruction to the memory chip where the unreliable storage unit is located to instruct the memory chip where the unreliable storage unit is located to replace the unreliable storage unit with the redundant storage unit in the redundant storage area, and recording the address correspondence between the redundant storage unit and the unreliable storage unit in the replacement relationship table; the replacement instruction carries the address information of the unreliable storage unit.

[0073] In some optional implementations of this embodiment, the plurality of memory chips further include a first storage space outside the available storage space; the above step 340 includes: replacing the unreliable storage unit with the redundant storage unit in the first storage space, and recording the address correspondence between the redundant storage unit and the unreliable storage unit.

[0074] In some other optional implementations, while the first storage space is set in the CXL memory module, each memory chip 120 may also be provided with a redundant storage area, and the above step 340 may adopt any of the above two methods to implement the replacement of the unreliable storage unit. As an example, the unreliable storage unit may be replaced by repairing the memory chip 120 itself. When the redundant storage area in the memory chip 120 is insufficient, the redundant storage unit in the first storage space may be used for replacement. This helps to improve the flexibility of the CXL memory module in repairing the memory.

[0075] In some embodiments, after the above step 320, the method may further include: upon receiving an access instruction to access the area to be detected, accessing the target area based on the address mapping relationship. In this embodiment, the address to be accessed carried in the access instruction can be converted into a corresponding address in the target area according to the address mapping relationship, and then the target area can be accessed according to the converted address, so as to achieve parallel processing of memory chip repair and memory access. In some optional implementations of this embodiment, after the data in the area to be detected is copied to the target area, when the failure detection or repair of the area to be detected is completed, the data may no longer be copied back to the area to be detected, but the target area may be used as the storage location of the data, and subsequent access operations to the data are mapped to the target area. At this time, a new target area can be re-determined for other subsequent areas, so that the number of data copies in the memory chip can be reduced, which helps to reduce the energy consumption of the CXL memory module.

[0076] In this embodiment, the method may further include: during operation, always reserving one or more free areas in the available storage space as initial target areas for failure detection.

[0077] Here, the initial target area may be predetermined. In the initial stage of failure detection, data may be stored in the initial target area, and a new target area may be determined later in the detection process.

[0078] In an optional example, the above step 310 may include: first using the initial target area as the area to be detected; if there is no unreliable storage unit in the initial target area, using the initial target area as the target area for subsequent failure detection of other areas.

[0079] In this example, the initial target area can be first tested for failure, and the reliable initial target area that has passed the test can be used as the target area for failure detection in other areas. This can avoid storing data in the unreliable initial target area, which helps to further improve the reliability of the data.

[0080] In another optional example, after the above step 330, the method may further include: in a case where there is no unreliable storage unit in the area to be detected, using the area to be detected as a target area for subsequent failure detection of other areas.

[0081] In this example, the detected reliable area (that is, the area without unreliable storage units) can be used as the target area for subsequent detection of other areas.

[0082] In some other implementations of this embodiment, after the above step 340, the method may further include: copying the data in the target area to the area to be detected, and deleting the address mapping relationship.

[0083] In this embodiment, in order to repair the memory chip during the operation of the CXL memory module, the memory access processing of the area to be detected is mapped to the target area during the repair process. After the repair of the area to be detected is completed, the data in the target area is copied to the area to be detected, which can ensure the timeliness of the data in the area to be detected and avoid the loss of data processing due to repairing the memory chip.

[0084] Figure 4 A flowchart of an embodiment of the memory repair method disclosed in the present invention is shown as follows: Figure 4 As shown, the process includes the following steps:

[0085] Step 410: During the operation of the CXL memory module, each of the plurality of regions is sequentially used as a region to be detected.

[0086] In this embodiment, a virtual address translation table is stored in the control chip so that the control chip can access multiple memory chips according to the virtual address carried in the access instruction. The virtual address translation table includes the correspondence between the virtual address and the physical address, and the physical address represents the storage address of the data in multiple memory chips.

[0087] Step 420: When the area to be detected is in use, copy the data in the area to be detected to a predetermined target area, and record the address mapping relationship between the area to be detected and the target area.

[0088] Step 430: Based on the address mapping relationship, modify the physical address of the area to be detected in the address translation table to the physical address of the target area.

[0089] Step 440: Perform failure detection on the area to be detected.

[0090] Step 450: When there are unreliable storage units in the area to be detected, replace the unreliable storage units with predetermined redundant storage units and record the replacement.

[0091] In this embodiment, before repairing the area to be detected, the physical address of the area to be detected in the virtual address translation table is modified to the physical address of the target area. The virtual address can be used to switch and map the area to be detected and the target area, and then the memory access processing of the area to be detected during and after the repair process is mapped to the target area, which helps to improve the access efficiency of the memory during the memory repair process.

[0092] In some optional implementations of this embodiment, after step 450, the above process may further include: step 460, copying the data in the target area back to the area to be detected.

[0093] Step 470: Based on the address mapping relationship, modify the physical address of the target area in the virtual address translation table to the physical address of the area to be detected.

[0094] The disclosed embodiment also provides a control chip, which is applied to a CXL memory module, such as Figure 5 As shown, the CXL memory module further includes a plurality of memory chips 520 managed by a control chip, and a processor 511 of the control chip 510 is configured to execute the memory repair method in the above embodiment.

[0095] The embodiments of the present disclosure also provide a non-transitory computer storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the memory repair method in the above embodiment is implemented.

[0096] The present disclosure also provides a computer system, such as Figure 6 As shown, the computer system includes a host 610 and a CXL memory module 620 in any of the above embodiments. The host 610 communicates with the CXL memory module 620 through a CXL interface to achieve discovery, configuration and data transmission of the CXL memory module 620; the CXL memory module 620 is configured to repair unreliable storage cells in the memory chip during operation.

[0097] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A CXL memory module, comprising a control chip and one or more memory chips managed by the control chip, characterized in that: The available storage space of the one or more memory chips includes multiple areas; the control chip is configured as follows: During the working process, each of the multiple areas is taken as the area to be detected in turn to determine whether there is an unreliable storage unit in the area to be detected; when the area to be detected is in an idle state, the area to be detected is directly subjected to failure detection; when the area to be detected is in use, the data in the area to be detected is copied to the target area, and the address mapping relationship between the area to be detected and the target area is recorded, and then the area to be detected is subjected to failure detection; when the unreliable storage unit exists in the area to be detected, the unreliable storage unit is replaced by a predetermined redundant storage unit.

2. The CXL memory module according to claim 1, characterized in that: The control chip is configured to sequentially use each of the multiple areas as a to-be-detected area, including: sequentially using each of the multiple areas as a to-be-detected area every preset period.

3. The CXL memory module according to claim 1, characterized in that: The control chip is configured to sequentially select each of the multiple regions as a to-be-detected region, including: preferentially determining a region in an idle state among the multiple regions as the to-be-detected region.

4. The CXL memory module according to claim 1, characterized in that: After copying the data in the to-be-detected area to the target area and recording the address mapping relationship between the to-be-detected area and the target area, the control chip is further configured to: When an access instruction to access the area to be detected is received, the target area is accessed based on the address mapping relationship.

5. The CXL memory module according to claim 1, characterized in that: A virtual address translation table is stored in the control chip so that the control chip can access the multiple memory chips according to the virtual address carried in the access instruction, and the virtual address translation table includes a correspondence between the virtual address and the physical address; and After copying the data in the area to be detected to the target area and recording the address mapping relationship between the area to be detected and the target area, the control chip is also configured to: based on the address mapping relationship, modify the physical address of the area to be detected in the address translation table to the physical address of the target area.

6. The CXL memory module according to claim 5, characterized in that: After replacing the unreliable storage unit with a predetermined redundant storage unit, the control chip is also configured to: copy the data in the target area to the area to be detected; based on the address mapping relationship, modify the physical address of the target area in the virtual address translation table to the physical address of the area to be detected.

7. The CXL memory module according to any one of claims 1 to 5, characterized in that: After replacing the unreliable storage unit with a predetermined redundant storage unit, the control chip is further configured to copy the data in the target area to the area to be detected and delete the address mapping relationship.

8. The CXL memory module according to any one of claims 1 to 5, characterized in that: The control chip is further configured to: during operation, always reserve one or more free areas in the available storage space as initial target areas for failure detection.

9. The CXL memory module according to claim 8, characterized in that: The control chip is configured to sequentially use each of the multiple areas as an area to be detected, including: first using the initial target area as the area to be detected; and when the unreliable storage unit does not exist in the initial target area, using the initial target area as the target area for subsequent failure detection of other areas.

10. The CXL memory module according to claim 9, characterized in that: The control chip is further configured to: when the unreliable storage unit does not exist in the area to be detected, use the area to be detected as a target area for subsequent failure detection of other areas.

11. The CXL memory module according to claim 1, characterized in that: Each of the one or more memory chips is provided with a redundant storage area and a replacement relationship table; The control chip is configured to replace the unreliable storage unit with a predetermined redundant storage unit, including: sending a replacement instruction to the memory chip where the unreliable storage unit is located, wherein the replacement instruction carries address information of the unreliable storage unit; Each of the one or more memory chips is configured to: in response to the replacement instruction, replace the unreliable storage unit with a redundant storage unit in the redundant storage area, and record the address correspondence between the redundant storage unit and the unreliable storage unit in the replacement relationship table.

12. The CXL memory module according to claim 1 or 11, characterized in that: The storage space of the one or more memory chips further includes a first storage space outside the available storage space; The control chip is configured to replace the unreliable storage unit with a predetermined redundant storage unit, including: replacing the unreliable storage unit with a redundant storage unit in the first storage space, and recording the address correspondence between the redundant storage unit and the unreliable storage unit.

13. A memory repair method, applied to a CXL memory module, wherein the CXL memory module comprises a control chip and one or more memory chips managed by the control chip, wherein the available storage space of the one or more memory chips comprises multiple areas; characterized in that: The method comprises: During the operation of the CXL memory module, each of the plurality of regions is sequentially used as a region to be detected to determine whether there is an unreliable storage unit in the region to be detected; When the area to be detected is in an idle state, directly performing failure detection on the area to be detected; When the area to be detected is in use, copying the data in the area to be detected to a predetermined target area, recording the address mapping relationship between the area to be detected and the target area, and then performing failure detection on the area to be detected; In the case that the unreliable storage unit exists in the area to be detected, the unreliable storage unit is replaced with a predetermined redundant storage unit and recorded.

14. The method according to claim 13, characterized in that Taking each of the multiple areas as the area to be detected in turn includes: every preset period, taking each of the multiple areas as the area to be detected in turn.

15. The method according to claim 13, characterized in that Sequentially taking each sub-area of ​​the multiple areas as the area to be detected includes: preferentially determining an area in an idle state among the multiple areas as the area to be detected.

16. The method according to claim 13, characterized in that After copying the data in the to-be-detected area to the target area and recording the address mapping relationship between the to-be-detected area and the target area, the method further includes: When an access instruction to access the area to be detected is received, the target area is accessed based on the address mapping relationship.

17. The method according to claim 13, characterized in that A virtual address translation table is stored in the control chip so that the control chip can access the multiple memory chips according to the virtual address carried in the access instruction, and the virtual address translation table includes a correspondence between the virtual address and the physical address; as well as, After copying the data in the area to be detected to the target area and recording the address mapping relationship between the area to be detected and the target area, the method further includes: based on the address mapping relationship, modifying the physical address of the area to be detected in the address translation table to the physical address of the target area.

18. The method according to claim 17, characterized in that After replacing the unreliable storage unit with a predetermined redundant storage unit, the method further includes: copying the data in the target area to the area to be detected; based on the address mapping relationship, modifying the physical address of the target area in the virtual address translation table to the physical address of the area to be detected.

19. The method according to any one of claims 13 to 17, characterized in that After replacing the unreliable storage unit with a predetermined redundant storage unit, the method further includes: copying the data in the target area to the area to be detected, and deleting the address mapping relationship.

20. The method according to any one of claims 13 to 17, characterized in that The method further includes: during operation, always reserving one or more free areas in the available storage space as initial target areas for failure detection.

21. The method according to claim 20, characterized in that Taking each of the multiple areas as the area to be detected in turn, including: first taking the initial target area as the area to be detected; and when the unreliable storage unit does not exist in the initial target area, taking the initial target area as the target area for subsequent failure detection of other areas.

22. The method according to claim 21, characterized in that The method further includes: when the unreliable storage unit does not exist in the area to be detected, using the area to be detected as a target area for subsequent failure detection of other areas.

23. The method according to claim 13, characterized in that Each of the one or more memory chips is provided with a redundant storage area and a replacement relationship table; Replacing the unreliable storage unit with a predetermined redundant storage unit includes: sending a replacement instruction to the memory chip where the unreliable storage unit is located to instruct the memory chip where the unreliable storage unit is located to replace the unreliable storage unit with a redundant storage unit in the redundant storage area, and recording the address correspondence between the redundant storage unit and the unreliable storage unit in the replacement relationship table; the replacement instruction carries the address information of the unreliable storage unit.

24. The method according to claim 13 or 23, characterized in that The storage space of the plurality of memory chips further includes a first storage space outside the available storage space; Replacing the unreliable storage unit with a predetermined redundant storage unit includes: replacing the unreliable storage unit with a redundant storage unit in the first storage space, and recording the address correspondence between the redundant storage unit and the unreliable storage unit.

25. A control chip, applied to a CXL memory module, the CXL memory module further comprising one or more memory chips managed by the control chip, characterized in that: The processor of the control chip is configured to execute the memory repair method described in any one of claims 13 to 24.

26. A non-transitory computer storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the memory repair method as described in any one of claims 13 to 24 is implemented.

27. A computer system comprising a host and the CXL memory module according to any one of claims 1 to 12, wherein the host communicates with the CXL memory module via a CXL interface to achieve discovery, configuration and data transmission of the CXL memory module, characterized in that: The CXL memory module is configured to repair unreliable memory cells in a memory chip during runtime.

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