Multi-chip stacked packaging structure and preparation method thereof

Abstract

The invention provides a multi-chip stacked packaging structure and a preparation method thereof.The packaging structure comprises a carrier frame, an upper stacked chip set, a lower stacked chip set, a plastic packaging layer and a rewiring layer, the carrier frame comprises at least one conductive column and a chip mounting area, the upper stacked chip set and the lower stacked chip set are longitudinally stacked in the chip mounting area, and the rewiring layer is arranged between the upper stacked chip set and the lower stacked chip set; the chip I / O interfaces are arranged on the edges of the two sides, and the carrier frame, the upper stacked chip set and the lower stacked chip set are wrapped by the plastic packaging layer; the top surface and the bottom surface of the plastic packaging layer are respectively provided with at least one rewiring layer, and the rewiring layers, the upper stacked chip set and the lower stacked chip set are electrically connected through the conductive columns. The invention further discloses a preparation method of the packaging structure. According to the 3D Fanout multi-chip packaging structure, three-dimensional stacking of a plurality of chips can be realized, so that the packaging density is greatly improved, and compared with an existing two-dimensional packaging mode, more space can be saved, and higher-density packaging can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of advanced packaging products, and more specifically to a multi-chip stacking packaging structure and a preparation method thereof. Background Art

[0002] As electronic chips develop towards miniaturization, high density, high reliability and low power consumption, the current market demand has put forward higher requirements for the chip packaging industry. 3D packaging, which integrates multiple chips and devices in the same package, has become a new direction to meet technological development. 3D packaging has become the focus of current industry attention. Compared with 2.5D packaging, the principle of 3D packaging is to make a transistor structure on the chip and use perforations to connect the electronic signals of different chips above and below, so as to directly stack memory or other chips vertically on it. 3D packaging has a smaller area and lower power consumption than 2D packaging, and is used for ultra-large bandwidth.

[0003] Among them, 3D Fanout is a new type of three-dimensional packaging technology, which can realize the three-dimensional stacking of multiple chips, thereby improving the packaging density, reducing the packaging size, and improving the packaging efficiency. The existing 3D Fanout packaging technology mainly makes multiple grooves on the silicon substrate, and then puts multiple chips into these grooves respectively, and finally connects these chips through metal wires to realize multi-chip packaging. Although this method can realize multi-chip packaging, its packaging density and packaging efficiency need to be improved. At the same time, there are still some problems with the existing 3D Fanout packaging technology.

[0004] The existing 3D Fanout packaging technology requires making multiple grooves on the silicon substrate, which undoubtedly increases the complexity and cost of the manufacturing process. Secondly, since multiple chips need to be connected through metal wires, this type of process will increase the size of the package, affecting the density and efficiency of the package. In addition, since this packaging method connects multiple chips together through physical connections, the reliability of the package still needs to be improved. Summary of the invention

[0005] In order to solve the above problems, the present invention provides a multi-chip stacking packaging structure and a preparation method thereof, which improves the density and efficiency of 3D Fanout packaging without increasing the complexity and cost of the manufacturing process; can realize three-dimensional stacking and efficient connection of multiple chips; and at the same time improves the reliability of 3D Fanout packaging and reduces potential reliability problems caused by physical connection methods.

[0006] In a first aspect, the present invention provides a multi-chip stacking packaging structure, comprising: A carrier frame, the carrier frame comprising at least one conductive column and a chip mounting area, the conductive column passes through the carrier frame and has pads at both ends; An upper stacked chipset and a lower stacked chipset, wherein the upper stacked chipset and the lower stacked chipset are stacked vertically in a chip mounting area, wherein the upper stacked chipset comprises a plurality of chips with functional surfaces facing upward, and two adjacent chips are vertically cross-stacked; wherein the lower stacked chipset comprises a plurality of chips with functional surfaces facing downward, and two adjacent chips are vertically cross-stacked; and wherein the chip I / O interfaces are arranged at the edges of both sides; The plastic sealing layer covers the carrier frame, the upper stacked chipset and the lower stacked chipset, so that the pads at both ends of the conductive pillars are exposed, and the chip I / O interfaces of the upper stacked chipset and the lower stacked chipset are exposed; The redistribution layer is provided on the top and bottom surfaces of the plastic packaging layer, respectively, and the electrical connection between the redistribution layer, the upper stacked chipset and the lower stacked chipset is achieved through the conductive pillars.

[0007] Preferably, the stacked chipset comprises a first chip and a second chip from bottom to top, and the first chip and the second chip are vertically crossed and stacked in a cross shape.

[0008] Preferably, the lower stacked chipset comprises a third chip and a fourth chip from top to bottom, and the third chip and the fourth chip are vertically crossed and stacked in a cross shape.

[0009] Preferably, when other chips are stacked vertically crosswise on the second chip, the chips do not block the I / O interfaces of the first chip and the second chip; when other chips are stacked under the fourth chip, the chips do not block the I / O interfaces of the third chip and the fourth chip.

[0010] In a second aspect, the present invention further provides a method for preparing the above-mentioned multi-chip stacking packaging structure, comprising the following steps: Prepare a single bare chip, lead the I / O interface to the edges of both sides of the chip, and then grind and scribing to obtain a single bare chip; A carrier frame is prepared, and a plurality of conductive columns penetrating the carrier frame are arranged on the carrier frame, and exposed pads are arranged at both ends of the conductive columns; a chip mounting area is formed by hollowing out the inside of the carrier frame for placing an upper stacked chipset and a lower stacked chipset; The carrier frame is temporarily bonded to the carrier board, and multiple single bare chips are mounted on the chip mounting area. Multiple chips with functional surfaces facing upward form an upper stacked chipset, and two adjacent chips are vertically cross-stacked; multiple chips with functional surfaces facing downward form a lower stacked chipset, and two adjacent chips are vertically cross-stacked; The carrier frame, the upper stacked chipset and the lower stacked chipset are plastic-sealed to form a plastic-sealed layer, which covers the carrier frame, the upper stacked chipset and the lower stacked chipset, and exposes the pads at both ends of the conductive pillars, opens holes at the I / O interface of the chip, exposes the I / O interface of the chip, and fills metal for double-sided electrical connection; after the plastic-sealing is completed, the carrier board is debonded; Rewiring layers are respectively arranged on the top and bottom surfaces of the plastic packaging layer, and interconnection between the redistribution layers, the upper stacked chipset and the lower stacked chipset is achieved through conductive pillars.

[0011] Preferably, a die-bonding film is provided between adjacent chips. Preferably, a photoresist is coated on the top or bottom surface of the plastic encapsulation layer, and a photolithography or laser process is performed using a mask to open a pattern opening to form a repassivation layer; a photoresist layer is coated again, and a photolithography or laser process is performed using a mask to open a metal layer pattern opening; and electroplating is performed in the metal layer pattern opening to form a redistribution layer; Alternatively, the same method is used to add multiple redistribution layers to realize a multi-layer redistribution layer interconnection structure.

[0012] Compared with the prior art, the present invention has the following beneficial effects: The 3D Fanout multi-chip packaging structure adopted by the present invention can realize three-dimensional stacking of multiple chips, thereby greatly improving the packaging density. Compared with the existing two-dimensional packaging method, it can save more space and realize higher density packaging.

[0013] The 3D Fanout multi-chip packaging structure of the present invention can realize the simultaneous packaging of multiple chips, thereby greatly improving the packaging efficiency and saving more time compared with the existing 3D Fanout packaging technology.

[0014] The 3D Fanout multi-chip packaging structure of the present invention can avoid connecting multiple chips together by physical connection through innovative design, thereby improving the reliability of packaging.

[0015] Due to the increase in packaging density and the realization of efficient interconnection between chips, the 3D Fanout multi-chip packaging structure of the present invention performs well in data transmission and power management, and can significantly reduce the overall power consumption of the system. By reducing the length of the signal transmission path and the physical connection points with high power consumption, the device can achieve a more energy-saving operation mode while maintaining high performance.

[0016] The 3D Fanout multi-chip packaging structure of the present invention allows for flexible adjustment of the number, type and arrangement of chips according to different application requirements, thereby quickly responding to market changes and meeting performance requirements in different scenarios.

[0017] Based on the invention, the packaging efficiency is improved, the packaging size is reduced, and the dependence on conventional substrates is reduced. The packaging structure can effectively reduce costs in the production and manufacturing stage. At the same time, higher packaging density and performance mean that more functions can be integrated into a single package, reducing the need for external components and further reducing the total cost of the terminal product. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic structural diagram of a carrier frame in Example 1 of the present invention; Figure 2 is a schematic diagram of a four-chip stacking packaging structure in Embodiment 1 of the present invention; Figure 3 is another schematic diagram of the four-chip stacking packaging structure in Embodiment 1 of the present invention; Figure 4 is a schematic diagram of the structure of a single bare chip in Embodiment 2 of the present invention; Figure 5 is a schematic structural diagram of a method of stacking four chips in Embodiment 2 of the present invention; Figure 6 yes Figure 5 A schematic diagram of a structure in which a first chip and a second chip are stacked; Figure 7 yes Figure 5 Structural diagram of subsequent plastic sealing and electrical connection; Figure 8 is a schematic structural diagram of another method of stacking four chips in Embodiment 2 of the present invention; Fig. 9 yes Figure 8 A schematic diagram of a structure in which a first chip and a second chip are stacked; Fig.10 yes Figure 8 Structural diagram of subsequent plastic sealing and electrical connection; Fig.11 It is a schematic diagram of the packaging structure of a single set of upper stacked chips and a lower stacked chips in the present invention.

[0019] Explanation of reference numerals: carrier frame-1, conductive pillar-101, chip mounting area-102, first chip-201, second chip-202, third chip-301, fourth chip-302, plastic encapsulation layer-4, redistribution layer-5, single bare chip-6, bump-7, metal pillar-401. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] Example 1 The present invention provides a multi-chip stacking packaging structure, comprising: Carrier frame 1, such as Figure 1 As shown, the carrier frame 1 includes at least one conductive column 101 and a chip mounting area 102. The conductive column 101 runs through the carrier frame 1 and has pads at both ends. The upper stacked chipset and the lower stacked chipset are stacked vertically in the chip mounting area 102. The upper stacked chipset includes a plurality of chips with functional surfaces arranged upward, and two adjacent chips are vertically cross-stacked; the lower stacked chipset includes a plurality of chips with functional surfaces arranged downward, and two adjacent chips are vertically cross-stacked; the chip I / O interfaces are arranged on the edges of both sides. On the one hand, during the chip stacking process, the I / O interfaces of each chip are not easily blocked; on the other hand, the I / O interfaces of each chip and the redistribution layer 5 can be connected in a linear manner, thereby increasing the stability and reliability of the connection.

[0023] like Figure 2 and Figure 3 As shown, in the multi-chip stacking packaging structure disclosed in this embodiment, the upper stacked chipset includes a first chip 201 and a second chip 202 from bottom to top, and the functional surfaces of the first chip 201 and the second chip 202 are arranged upward. The first chip 201 and the second chip 202 are vertically crossed and stacked in a cross shape. The lower stacked chipset includes a third chip 301 and a fourth chip 302 from top to bottom, and the functional surfaces of the third chip 301 and the fourth chip 302 are arranged downward, and the third chip 301 and the fourth chip 302 are vertically crossed and stacked in a cross shape.

[0024] The I / O interfaces of the first chip 201 , the second chip 202 , the third chip 301 and the fourth chip 302 are arranged on the edges of both sides, and the four chips may be of the same size or of different sizes.

[0025] In a specific implementation, the structure after four chips are stacked can be the following two structures: First, if Figure 2 As shown, the first chip 201 and the third chip 301 are arranged in the same direction, for example, both are arranged horizontally, the second chip 202 is vertically stacked in the middle of the first chip 201, and the fourth chip 302 is vertically stacked in the middle of the third chip 301.

[0026] Second, if Figure 3 As shown, the first chip 201 and the third chip 301 are arranged in directions perpendicular to each other. For example, if the first chip 201 is arranged horizontally, then the third chip 301 is arranged perpendicular to the middle position of the first chip 201; the second chip 202 is vertically stacked in the middle position of the first chip 201, and the fourth chip 302 is also vertically stacked in the middle position of the third chip 301. At this time, the second chip 202 and the third chip 301 have the same direction, and the fourth chip 302 and the first chip 201 have the same direction.

[0027] The plastic encapsulation layer 4 covers the carrier frame 1, the upper stacked chipset and the lower stacked chipset, so that the pads at both ends of the conductive column 101 are exposed, and the chip I / O interfaces of the upper stacked chipset and the lower stacked chipset are exposed. Holes are opened in the plastic encapsulation layer at the pads at both ends of the conductive column 101 and the I / O interface of the chip, so that the pads at both ends of the conductive column 101 and the I / O interface of the chip are exposed, and metal is filled to form a metal column 401, which is used for double-sided electrical connection with the redistribution layer 5. Through innovative design, it is possible to avoid connecting multiple chips together through physical connection, thereby improving the reliability of the package; by reducing the length of the signal transmission path and the physical connection points with high power consumption, the device can achieve a more energy-saving operation mode while maintaining high performance.

[0028] Rewiring layer 5: at least one layer of rewiring layer 5 is disposed on the top and bottom surfaces of the plastic layer 4, and the electrical connection between the rewiring layer 5, the upper stacked chipset and the lower stacked chipset is achieved through the conductive pillars 101. Finally, bumps 7 are prepared on the package to form a wafer-level multi-chip stacking package structure.

[0029] If chips are stacked on the basis of the above packaging structure, for example, when other chips are stacked vertically and crosswise on the second chip 202, these chips cannot block the I / O interfaces of the first chip 201 and the second chip 202; when other chips are stacked under the fourth chip 302, these chips cannot block the I / O interfaces of the third chip 301 and the fourth chip 302. In this way, the I / O interface of each chip can be electrically connected to the redistribution layer 5 in a straight line, the connection is stable, and the process is relatively simple.

[0030] Example 2 This embodiment provides a method for preparing the multi-chip stacking packaging structure described in Embodiment 1, comprising the following steps: Prepare a single bare chip 6, lead the I / O interface to the edges of both sides of the chip, and then grind and slice to obtain a single bare chip 6. The structural schematic diagram of the single bare chip 6 is as shown in Figure 4 shown.

[0031] Prepare carrier frame 1, such as Figure 1As shown, a plurality of conductive pillars 101 penetrating the carrier frame 1 are arranged on the carrier frame 1, and exposed pads are arranged at both ends of the conductive pillars 101; the carrier frame 1 is hollowed out to form a chip mounting area 102 for placing the upper stacked chipset and the lower stacked chipset.

[0032] like Figure 5 As shown, the carrier frame 1 is temporarily bonded to the carrier board 8 through a temporary bonding film 801, and then a plurality of single bare chips 6 are mounted on the chip mounting area 102, and a plurality of chips with functional surfaces arranged upward form an upper stacked chip group, in which two adjacent chips are vertically cross-stacked; a plurality of chips with functional surfaces arranged downward form a lower stacked chip group, in which two adjacent chips are vertically cross-stacked.

[0033] First, the fourth chip 302 is mounted on the carrier board 8, and then the third chip 301, the first chip 201 and the second chip 202 are vertically cross-stacked in sequence, that is, stacked in sequence from bottom to top. Adjacent chips are fixedly connected using a die bonding film.

[0034] like Figure 5 As shown, if the fourth chip 302 is mounted at 90 degrees, then the third chip 301 is mounted at 0 degrees (i.e., arranged horizontally), the first chip 201 is also mounted at 0 degrees (i.e., arranged horizontally), and the second chip 202 is mounted at 90 degrees, wherein another perspective structural schematic diagram of the stacking structure of the first chip 201 and the second chip 202 is as shown in FIG. Figure 6 After plastic sealing and electrical connection, it is formed as shown in Figure 2 The packaging structure shown. Among them, the carrier frame 1, the upper stacked chipset and the lower stacked chipset are plastic-sealed to form a plastic-sealed layer 4, the plastic-sealed layer 4 covers the carrier frame 1, the upper stacked chipset and the lower stacked chipset, and the pads at both ends of the conductive column 101 are exposed, and holes are opened at the I / O interface of the chip to expose the I / O interface of the chip, and metal is filled to form a metal column 401 for double-sided electrical connection. Through innovative design, it is possible to avoid connecting multiple chips together through physical connection, thereby improving the reliability of the package; by reducing the length of the signal transmission path and the physical connection points with high power consumption, the device can achieve a more energy-saving operation mode while maintaining high performance. After the plastic sealing is completed, the bonding carrier 8 is debonded; then the rewiring layer 5 is prepared, and the rewiring layer 5 is respectively set on the top and bottom surfaces of the plastic-sealed layer 4, and the interconnection between the chips of the rewiring layer 5, the upper stacked chipset and the lower stacked chipset is achieved through the conductive column 101. The top or bottom surface of the plastic encapsulation layer 4 is coated with photoresist, and a mask is used for photolithography or laser processing to open a pattern opening to form a repassivation layer; the photoresist layer is coated again, and a mask is used for photolithography or laser processing to open a metal layer pattern opening; electroplating is performed in the metal layer pattern opening to form a redistribution layer 5; or, multiple layers of redistribution layers 5 are added by the same method to realize a multi-layer redistribution layer 5 interconnection structure. The specific structural diagram of the plastic encapsulation and electrical connection is shown in FIG. Figure 7 Finally, a bump 7 is prepared on the package to form a wafer-level multi-chip stacking package structure.

[0035] like Figure 8 As shown, if the fourth chip 302 is mounted at 0 degrees (i.e., arranged horizontally), the third chip 301 is mounted at 90 degrees, the first chip 201 is mounted at 0 degrees (i.e., arranged horizontally), and the second chip 202 is mounted at 90 degrees, wherein another perspective schematic diagram of the stacking structure of the third chip 301 and the fourth chip 302 is as shown in FIG. Fig. 9 After plastic sealing and electrical connection, it is formed as shown in Figure 3 The specific plastic packaging and electrical connection structure diagram is as follows Fig.10 As shown, the related plastic packaging and electrical connection processes are the same as those described above and will not be repeated here. Finally, a bump 7 is prepared on the package to form a wafer-level multi-chip stacking package structure.

[0036] The 3D Fanout multi-chip packaging structure prepared by Examples 1 and 2 can realize three-dimensional stacking of multiple chips, thereby greatly improving the packaging density. Compared with the existing two-dimensional packaging method, it can save more space and achieve higher density packaging. Because multiple chips can be packaged at the same time, this also greatly improves the packaging efficiency and saves more time.

[0037] Due to the improvement of packaging density and the realization of efficient interconnection between chips, the 3D Fanout multi-chip packaging structure of the present invention performs well in data transmission and power management, and can significantly reduce the overall power consumption of the system.

[0038] The 3D Fanout multi-chip packaging structure of the present invention allows for flexible adjustment of the number, type and arrangement of chips according to different application requirements, thereby quickly responding to market changes and meeting performance requirements in different scenarios.

[0039] Based on the invention, the packaging efficiency is improved, the packaging size is reduced, and the dependence on conventional substrates is reduced. The packaging structure can effectively reduce costs in the production and manufacturing stage. At the same time, higher packaging density and performance mean that more functions can be integrated into a single package, reducing the need for external components and further reducing the total cost of the terminal product.

[0040] The multi-chip stacking packaging structure in the two embodiments of the present invention includes two groups of upper stacked chips and lower stacked chips. If only one group of upper stacked chips and lower stacked chips is needed, two rows of conductive pillars 101 can be set in the middle of the carrier frame 1, so that the conductive pillars 101 are arranged around the single group of upper stacked chips and the single group of lower stacked chips, so as to facilitate the subsequent electrical connection with the redistribution layer 5. Fig.11As shown, finally, a bump 7 is prepared on the package to form a wafer-level multi-chip stacking package structure, which is then cut into a package structure including a single group of upper stacked chips and a lower stacked chips.

[0041] The above are only some embodiments of the present invention. It should be pointed out that for ordinary technicians in this field, other modifications and improvements can be made without departing from the creative concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A multi-chip stacking packaging structure, characterized in that: include: A carrier frame, the carrier frame comprising at least one conductive column and a chip mounting area, the conductive column passes through the carrier frame and has pads at both ends; An upper stacked chipset and a lower stacked chipset, wherein the upper stacked chipset and the lower stacked chipset are stacked vertically in a chip mounting area, wherein the upper stacked chipset comprises a plurality of chips with functional surfaces facing upward, and two adjacent chips are vertically cross-stacked; wherein the lower stacked chipset comprises a plurality of chips with functional surfaces facing downward, and two adjacent chips are vertically cross-stacked; and wherein the chip I / O interfaces are arranged at the edges of both sides; The plastic sealing layer covers the carrier frame, the upper stacked chipset and the lower stacked chipset, so that the pads at both ends of the conductive pillars are exposed, and the chip I / O interfaces of the upper stacked chipset and the lower stacked chipset are exposed; The redistribution layer is provided on the top and bottom surfaces of the plastic packaging layer, respectively, and the electrical connection between the redistribution layer, the upper stacked chipset and the lower stacked chipset is achieved through the conductive pillars.

2. The multi-chip stacking packaging structure according to claim 1, characterized in that: The stacked chipset includes a first chip and a second chip from bottom to top, and the first chip and the second chip are vertically crossed and stacked in a cross shape.

3. The multi-chip stacking packaging structure according to claim 2, characterized in that: The lower stacked chipset includes a third chip and a fourth chip from top to bottom, and the third chip and the fourth chip are vertically crossed and stacked in a cross shape.

4. The multi-chip stacking packaging structure according to claim 3, characterized in that: When other chips are stacked vertically and crosswise on the second chip, the chips do not block the I / O interfaces of the first chip and the second chip; when other chips are stacked under the fourth chip, the chips do not block the I / O interfaces of the third chip and the fourth chip.

5. A method for preparing a multi-chip stacked packaging structure, for preparing the multi-chip stacked packaging structure as claimed in any one of claims 1 to 4, characterized in that: The steps include: Prepare a single bare chip, lead the I / O interface to the edges of both sides of the chip, and then grind and scribing to obtain a single bare chip; A carrier frame is prepared, and a plurality of conductive columns penetrating the carrier frame are arranged on the carrier frame, and exposed pads are arranged at both ends of the conductive columns; a chip mounting area is formed by hollowing out the inside of the carrier frame for placing an upper stacked chipset and a lower stacked chipset; The carrier frame is temporarily bonded to the carrier board, and multiple single bare chips are mounted on the chip mounting area. Multiple chips with functional surfaces facing upward form an upper stacked chipset, and two adjacent chips are vertically cross-stacked; multiple chips with functional surfaces facing downward form a lower stacked chipset, and two adjacent chips are vertically cross-stacked; The carrier frame, the upper stacked chipset and the lower stacked chipset are plastic-sealed to form a plastic-sealed layer, which covers the carrier frame, the upper stacked chipset and the lower stacked chipset, and exposes the pads at both ends of the conductive pillars, opens holes at the I / O interface of the chip, exposes the I / O interface of the chip, and fills metal for double-sided electrical connection; after the plastic-sealing is completed, the carrier board is debonded; Rewiring layers are respectively arranged on the top and bottom surfaces of the plastic packaging layer, and interconnection between the redistribution layers, the upper stacked chipset and the lower stacked chipset is achieved through conductive pillars.

6. The preparation method according to claim 5, characterized in that: A die pasting film is provided between adjacent chips.

7. The preparation method according to claim 6, characterized in that: Coating photoresist on the top or bottom surface of the plastic layer, performing photolithography or laser process with a mask plate to open a pattern opening to form a repassivation layer; coating the photoresist layer again, performing photolithography or laser process with a mask plate to open a metal layer pattern opening; electroplating in the metal layer pattern opening to form a redistribution layer; Alternatively, the same method is used to add multiple redistribution layers to realize a multi-layer redistribution layer interconnection structure.

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