Six-bit numerical control time delay circuit with high area efficiency and low amplitude error

Abstract

The invention belongs to the field of wireless communication systems, relates to a numerical control time delay circuit, and particularly provides a six-bit numerical control time delay circuit with high area efficiency and low amplitude error, which can realize six-bit numerical control time delay performance with the maximum range of 315ps and the minimum step of 5ps in the broadband range of 2-15GHz. The circuit comprises two single-pole double-throw switches, five double-pole double-throw switches, four fixed attenuation units and six time delay units, the time delay units adopt a novel circuit layout structure design, so that the core area of the circuit is only 1.87 * 0.385 mm < 2 >, and the corresponding area efficiency can reach 437.5 ps / mm < 2 >; meanwhile, the single-pole double-throw switch and the double-pole double-throw switch adopt the switch design with asymmetric amplitude response, amplitude fluctuation between different time delay states is greatly reduced, the amplitude error of the circuit is effectively reduced, and the maximum amplitude fluctuation of the time delay circuit between the different time delay states is limited within + / -2.4 dB.

Description

Technical Field

[0001] The invention belongs to the field of wireless communication systems, relates to a digitally controlled time delay circuit, and specifically provides a six-digit digitally controlled time delay circuit with high area efficiency and low amplitude error. Background Art

[0002] As a time delay control device, the delay circuit has very important applications in various broadband communications, detection and imaging systems. For example, in a broadband phased array system, the use of a delay circuit instead of a traditional phase shifter circuit can effectively solve the beam squint problem of the antenna array. In a broadband self-interference cancellation full-duplex system, the delay circuit is used to provide the necessary time delay for the reference signal to achieve a self-cancellation effect on the leakage signal of the transmission channel.

[0003] At present, among various types of delay circuits, digitally controlled delay circuits based on a switch delay line architecture are highly favored due to their advantages such as wide operating frequency band, wide applicable frequency, no power consumption, and high linearity; however, existing switch delay line digitally controlled delay circuits still have problems such as low circuit area efficiency and large amplitude error, which limit their application to a certain extent; to address this problem, the present invention provides a six-digit digitally controlled delay circuit with high area efficiency and low amplitude error. Summary of the invention

[0004] The purpose of the present invention is to propose a six-digit digital controlled delay circuit with high area efficiency and low amplitude error, which can achieve a six-digit digital controlled delay performance with a maximum range of 315ps and a minimum step of 5ps in a wide frequency range of 2 to 15GHz. The new circuit layout structure design is adopted to make the core area of ​​the circuit only 1.87×0.385mm 2 , the corresponding area efficiency can reach 437.5ps / mm 2 At the same time, a switch design with an asymmetric amplitude response is adopted to greatly reduce the amplitude fluctuation between different delay states, effectively reduce the amplitude error of the circuit, and limit the maximum amplitude fluctuation of the delay circuit between different delay states to within ±2.4dB.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is:

[0006] A six-digit digital controlled delay circuit with high area efficiency and low amplitude error comprises: two single-pole double-throw switches, five double-pole double-throw switches, four fixed attenuation units and six delay units; characterized in that the first single-pole double-throw switch, the first double-pole double-throw switch to the fifth double-pole double-throw switch and the second single-pole double-throw switch are arranged in sequence; the first delay unit to the sixth delay unit are connected in sequence to the delay path between adjacent switches, and provide time delays of τ, 2τ, 4τ, 8τ, 16τ, and 32τ respectively, τ being the minimum step; the first fixed attenuation unit to the fourth fixed attenuation unit are connected in sequence to the reference path corresponding to the delay path where the third delay unit to the sixth delay unit are located.

[0007] Further, the single-pole double-throw switch includes an A port, a B port and a C port, including a first signal path between the A port and the B port, a second signal path between the A port and the C port and a ground signal path from the A port to the signal ground, the A port serves as an input end or an output end, the B port is connected to a delay path, and the C port is connected to a reference path; the first signal path is composed of a MOS tube Ms1 connected in series and a MOS tube Ms2 connected in parallel to the ground, the second signal path is composed of a MOS tube Ms3 connected in series and a MOS tube Ms4 connected in parallel to the ground, and the ground signal path is composed of a MOS tube Ms5 connected in series, a capacitor Cs1 and a resistor Rs1 connected in series.

[0008] Furthermore, in the single-pole double-throw switch, the MOS tubes Ms1 and Ms4 are controlled by the control voltage V s1 Control, MOS tubes Ms2, Ms3 and Ms5 are controlled by the control voltage control, and the control voltage V s1 With control voltage The level is opposite; when the control voltage V s1 High level, control voltage When the control voltage V s1 Low level, control voltage When it is at a high level, the first signal path is cut off, and the second signal path and the ground signal path are both turned on.

[0009] Furthermore, the double-pole double-throw switch is composed of two single-pole double-throw switches connected back to back, specifically including a D port, an E port, an F port and a G port, the D port and the E port are respectively connected to the previous level delay path and the next level delay path, and the F port and the G port are respectively connected to the previous level reference path and the next level reference path.

[0010] Furthermore, in the single-pole double-throw switch and the double-pole double-throw switch, each port is respectively provided with a matching inductor to achieve port impedance matching, and the gate of each MOS tube is respectively connected to a large resistor to prevent leakage of radio frequency signals.

[0011] Furthermore, the first delay unit to the sixth delay unit are used to provide time delays of 5ps, 10ps, 20ps, 40ps, 80ps, and 160ps, respectively; the first fixed attenuation unit to the fourth fixed attenuation unit are used to compensate for the amplitude reference differences between the 20ps, 40ps, 80ps, and 160ps delay units and the corresponding reference states, respectively.

[0012] Furthermore, the 40ps delay unit is composed of a capacitive all-pass network and an inductive all-pass network, the capacitive all-pass network is composed of a series capacitor Ccs, mutually coupled inductors Lcs1 and Lcs2, and a ground capacitor Ccp, and the inductive all-pass network is composed of a series inductor Lis, two capacitors Cis1 and Cis2, and a ground inductor Lip; wherein the series inductor Lis adopts a winding inductor structure, and the ground inductor Lip adopts an S-type inductor structure, and in the CMOS process, the ground inductor Lip is arranged below the series inductor Lis to form a nested structure.

[0013] Furthermore, the 80ps delay unit and the 160ps delay unit are respectively formed by cascading two and four 40ps delay units.

[0014] Based on the above technical solution, the beneficial effects of the present invention are:

[0015] 1) The present invention proposes a six-digital controlled delay circuit based on a switch delay line architecture, which can achieve a digital controlled delay effect with a maximum adjustment range of 315ps and a minimum step of 5ps in a wide frequency range of 2 to 15GHz. At the same time, the circuit has the advantages of small size and low error, which provides a new idea for meeting the wide-band, large-range, low-error delay control requirements of various broadband systems such as broadband phased arrays and broadband self-interference cancellation full-duplex systems;

[0016] 2) The present invention proposes a novel nested layout structure design based on an S-type inductor structure, which utilizes the self-cancelling coupling characteristics of the S-type inductor to nest different inductors together, thereby avoiding the waste of layout area caused by the asymmetric layout structure of the all-pass network in the traditional design, thereby effectively improving the circuit area efficiency and promoting system miniaturization;

[0017] 3) The present invention adopts a new switching circuit with an asymmetric amplitude response to achieve targeted compensation for the frequency-dependent loss difference between the delay unit and the reference path, thereby greatly reducing the amplitude fluctuation level of the delay circuit between different delay states, and effectively reducing the amplitude error of the delay circuit during the delay control process. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a block diagram of the architecture of the six-digit digital controlled delay circuit with high area efficiency and low amplitude error in the present invention.

[0019] Figure 2 This is a circuit schematic diagram of the single-pole double-throw switch proposed in the present invention.

[0020] Figure 3 This is a circuit schematic diagram of the double-pole double-throw switch proposed by the present invention.

[0021] Figure 4 This is the layout structure of the 40ps basic delay unit proposed by the present invention.

[0022] Figure 5 1 is a test result diagram of a six-digit numerically controlled delay circuit with high area efficiency and low amplitude error in an embodiment of the present invention, wherein (a) is an S parameter test result and (b) is a relative delay test result.

[0023] Figure 6 This is a physical picture of a six-digit digital controlled delay circuit with high area efficiency and low amplitude error in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and beneficial effects of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0025] This embodiment provides a six-digit digital controlled delay circuit with high area efficiency and low amplitude error, such as Figure 1 As shown, the delay circuit includes: two single-pole double-throw switches, five double-pole double-throw switches, four fixed attenuation units and six delay units; wherein, the first single-pole double-throw switch, the first double-pole double-throw switch to the fifth double-pole double-throw switch, and the second single-pole double-throw switch are arranged in sequence; the first delay unit to the sixth delay unit are connected in sequence to the delay path between adjacent switches, and provide time delays of τ, 2τ, 4τ, 8τ, 16τ, and 32τ respectively, and τ is the minimum step; the first fixed attenuation unit to the fourth fixed attenuation unit are connected in sequence to the reference path corresponding to the delay unit where the third delay unit to the sixth delay unit are located.

[0026] Furthermore, the first delay unit to the sixth delay unit are used to provide time delays of 5ps, 10ps, 20ps, 40ps, 80ps, and 160ps, respectively; the first fixed attenuation unit to the fourth fixed attenuation unit are used to compensate for the amplitude reference differences between the 20ps, 40ps, 80ps, and 160ps delay units and the corresponding reference states, respectively.

[0027] Furthermore, the circuit structure of the single-pole double-throw switch is as follows: Figure 2 As shown, it includes an A port, a B port and a C port, including a first signal path between the A port and the B port, a second signal path between the A port and the C port and a ground signal path from the A port to the signal ground, the A port is used as an input end or an output end, the B port is connected to the delay path, and the C port is connected to the reference path; the first signal path is composed of a series MOS transistor Ms1 and a MOS transistor Ms2 connected in parallel to the ground, the second signal path is composed of a series MOS transistor Ms3 and a MOS transistor Ms4 connected in parallel to the ground, and the ground signal path is composed of a series MOS transistor Ms5, a capacitor Cs1 and a resistor Rs1 connected in sequence; the A port, the B port and the C port are respectively provided with matching inductors Ls1, Ls2 and Ls3 to achieve port impedance matching; and the gate of each MOS tube is respectively connected to a large resistor to prevent radio frequency signal leakage;

[0028] In the SPDT switch, MOS tubes Ms1 and Ms4 are controlled by a control voltage V s1 Control, MOS tubes Ms2, Ms3 and Ms5 are controlled by the control voltage control, and the control voltage V s1 With control voltage The level is opposite; when the control voltage V s1 High level, control voltage When the control voltage V is low, MOS tubes Ms1 and Ms4 are in the on state, the first signal path is on, MOS tubes Ms2, Ms3, and Ms5 are in the off state, the second signal path and the ground signal path are both off, and the input signal of port A will be transmitted to port B with low loss; when the control voltage V s1 Low level, control voltage When it is high level, MOS tubes Ms1 and Ms4 are in the cut-off state, the first signal path is cut-off, MOS tubes Ms2, Ms3, and Ms5 are in the on state, and the second signal path and the ground signal path are both on. At this time, part of the input signal of port A enters the ground path and is dissipated on the resistor Rs1, and the other part is transmitted to port C. Since part of the signal is dissipated in the ground path, the signal transmitted from port A to port C in this state will have a certain degree of loss, that is: asymmetric amplitude response, to achieve targeted compensation for the frequency-dependent loss difference between the delay path and the reference path, thereby greatly reducing the amplitude fluctuation level of the delay circuit between different delay states, and effectively reducing the amplitude error of the delay circuit in the delay control process; and, by matching and adjusting the size of capacitor Cs1 and resistor Rs1, the loss slope can be adjusted.

[0029] Furthermore, the circuit structure of the double-pole double-throw switch is as follows: Figure 3 As shown, it is composed of two single-pole double-throw switches connected in a back-to-back form, that is, the A ports are connected; specifically, it includes a D port, an E port, an F port and a G port, the D port and the E port are respectively connected to the previous level delay path and the next level delay path, the F port and the G port are respectively connected to the previous level reference path and the next level reference path, similarly, the D port, the E port, the F port, and the G port are respectively provided with matching inductors Ld1, Ld2, Ld3, and Ld4 to achieve port impedance matching, and the gate of each MOS tube is respectively connected to a large resistor to prevent RF signal leakage;

[0030] In the double-pole double-throw switch, MOS tubes Md1 and Md7 are controlled by the control voltage V d1 Control, MOS tubes Md3, Md5 and Md9 are controlled by the control voltage control, and the control voltage V d1 With control voltage The levels are opposite; MOS tubes Md2 and Md8 are controlled by the voltage V d2 Control, MOS tubes Md4, Md6 and Md10 are controlled by the control voltage control, and the control voltage V d2 With control voltage The level is opposite, the control voltage V d1 and Control voltage V d2 and The path control process is the same as that of a single-pole double-throw switch, and the combined control of two sets of control voltages can also achieve an asymmetric amplitude response.

[0031] Furthermore, the layout structure of the 40ps delay unit is as follows: Figure 4As shown, it is composed of a capacitive all-pass network and an inductive all-pass network; wherein, the capacitive all-pass network is composed of a series capacitor Ccs, mutually coupled inductors Lcs1 and Lcs2, and a ground capacitor Ccp, and the inductive all-pass network is composed of a series inductor Lis, two capacitors Cis1 and Cis2, and a ground inductor Lip; the series inductor Lis adopts a winding inductor structure, which is implemented by using metal layers M9 and M8 in the CMOS process, and the ground inductor Lip adopts an S-type inductor structure, which is implemented by using metal layers M8 and M7 in the CMOS process, and the ground inductor Lip is arranged below the series inductor Lis to form a nested structure, thereby effectively reducing the circuit size;

[0032] On this basis, the 80ps delay unit and the 160ps delay unit are realized by cascading two and four 40ps delay units respectively.

[0033] Specifically, the six-digit digital controlled delay circuit in this embodiment is implemented using a 65nm CMOS process. Figure 6 As shown; in the six-digital controlled delay circuit, the working states of all MOS tubes are controlled by an external control voltage. By changing the control voltage to a high level or a low level, the MOS tube can be made to work in an on or off state accordingly, so as to realize the signal path of the access circuit, thereby realizing the regulation of the overall delay level of the circuit; more precisely, by switching the working state of the MOS tube, each bit can be switched between the delay state and the reference state. Specifically, bit 1 can realize the switching of two relative states of 0ps / 5ps, bit 2 can realize the switching of two relative states of 0ps / 10ps, bit 3 can realize the switching of two relative states of 0ps / 20ps, bit 4 can realize the switching of two relative states of 0ps / 40ps, bit 5 can realize the switching of two relative states of 0ps / 80ps, bit 6 can realize the switching of two relative states of 0ps / 160ps, and through the arrangement and combination of the six bits, the delay regulation effect with a step of 5ps between 0 and 315ps is finally realized.

[0034] like Figure 5 FIG. 1 is a test result diagram of a six-digit digital controlled delay circuit with high area efficiency and low amplitude error in this embodiment. Figure 5 (a) is the S parameter test result. Figure 5 (b) is the relative delay test result; it can be seen from the figure that the present embodiment successfully achieves the discrete step digital control delay effect in the wide frequency range of 2 to 15 GHz, the maximum delay adjustment range is 315 ps, and the minimum step is 5 ps; under all delay states, the input return loss of the circuit remains better than 9 dB, and the output return loss remains better than 11 dB; at the same time, the maximum amplitude fluctuation of the circuit between different delay states is limited to within ±2.4 dB; and, as Figure 6 As shown, the core area of ​​the circuit is only 1.87×0.385mm 2 , the corresponding area efficiency can reach 437.5ps / mm 2 ; In summary, all test results have verified the correctness and superiority of the present invention.

[0035] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A six-digit digital controlled delay circuit with high area efficiency and low amplitude error, comprising: The invention is composed of two single-pole double-throw switches, five double-pole double-throw switches, four fixed attenuation units and six time delay units; the characteristics are that the first single-pole double-throw switch, the first double-pole double-throw switch to the fifth double-pole double-throw switch and the second single-pole double-throw switch are arranged in sequence; the first delay unit to the sixth delay unit are connected in sequence to the delay path between adjacent switches, and provide time delays of τ, 2τ, 4τ, 8τ, 16τ and 32v respectively, and τ is the minimum step; the first fixed attenuation unit to the fourth fixed attenuation unit are connected in sequence to the reference path corresponding to the delay path where the third delay unit to the sixth delay unit are located.

2. The six-digit digital controlled delay circuit with high area efficiency and low amplitude error according to claim 1, characterized in that: The single-pole double-throw switch includes an A port, a B port and a C port, including a first signal path between the A port and the B port, a second signal path between the A port and the C port and a ground signal path from the A port to the signal ground, the A port serves as an input end or an output end, the B port is connected to a delay path, and the C port is connected to a reference path; the first signal path is composed of a MOS transistor Ms1 connected in series and a MOS transistor Ms2 connected in parallel to the ground connected in sequence, the second signal path is composed of a MOS transistor Ms3 connected in series and a MOS transistor Ms4 connected in parallel to the ground connected in sequence, and the ground signal path is composed of a MOS transistor Ms5 connected in series, a capacitor Cs1 and a resistor Rs1 connected in sequence.

3. The six-digit digital controlled delay circuit with high area efficiency and low amplitude error according to claim 2, characterized in that: In the SPDT switch, MOS tubes Ms1 and Ms4 are controlled by a control voltage V s1 Control, MOS tubes Ms2, Ms3 and Ms5 are controlled by the control voltage control, and the control voltage V s1 With control voltage The level is opposite; when the control voltage V s1 High level, control voltage When the control voltage V s1 Low level, control voltage When it is at a high level, the first signal path is cut off, and the second signal path and the ground signal path are both turned on.

4. The six-digit digital controlled delay circuit with high area efficiency and low amplitude error according to claim 2, characterized in that: The double-pole double-throw switch is composed of two single-pole double-throw switches connected back to back, specifically including a D port, an E port, an F port and a G port. The D port and the E port are respectively connected to the previous level delay path and the next level delay path, and the F port and the G port are respectively connected to the previous level reference path and the next level reference path.

5. The six-digit digital controlled delay circuit with high area efficiency and low amplitude error according to claim 2 or 4, characterized in that: In the single-pole double-throw switch and the double-pole double-throw switch, each port is respectively provided with a matching inductor to achieve port impedance matching, and the gate of each MOS tube is respectively connected to a large resistor to prevent leakage of radio frequency signals.

6. The six-digit digital controlled delay circuit with high area efficiency and low amplitude error according to claim 1, characterized in that: The first delay unit to the sixth delay unit are used to provide time delays of 5ps, 10ps, 20ps, 40ps, 80ps, and 160ps, respectively; the first fixed attenuation unit to the fourth fixed attenuation unit are used to compensate for the amplitude reference differences between the 20ps, 40ps, 80ps, and 160ps delay units and the corresponding reference states, respectively.

7. The six-digit digital controlled delay circuit with high area efficiency and low amplitude error according to claim 6, characterized in that: The 40ps delay unit is composed of a capacitive all-pass network and an inductive all-pass network. The capacitive all-pass network is composed of a series capacitor Ccs, mutually coupled inductors Lcs1 and Lcs2, and a grounded capacitor Ccp. The inductive all-pass network is composed of a series inductor Lis, two capacitors Cis1 and Cis2, and a grounded inductor Lip. The series inductor Lis adopts a winding inductor structure, and the grounded inductor Lip adopts an S-type inductor structure. In the CMOS process, the grounded inductor Lip is arranged below the series inductor Lis to form a nested structure.

8. The six-digit digital controlled delay circuit with high area efficiency and low amplitude error according to claim 7, characterized in that: The 80ps delay unit and the 160ps delay unit are respectively formed by cascading two and four 40ps delay units.

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