A mainboard timing control circuit

Abstract

The present invention discloses a mainboard timing control circuit, the control circuit comprises a feedback unit, the feedback unit comprises a first shift register, a nineteenth resistor, a twentieth resistor, a twenty-second resistor, a twenty-third resistor, and a first connector; the present invention can automatically establish a response period after the first module is powered on, and detect the response speed of the module; within the response period, if the power-on completion signal feedback of the detected module is not received, the circuit will automatically limit the power-on signal of the next module, ensuring that all modules can be stably started in a preset order; when the response speed of any module is affected by the environmental temperature factor, the next module can be powered on and a delay period can be established for the detected module, thereby avoiding the occurrence of erroneous alarms, reset operations, and inaccurate power-on signal feedback time.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and in particular to a mainboard timing control circuit. Background Art

[0002] The voltage or current required to start each module in the motherboard is not the same, so power-on timing control is particularly important. A reasonable and stable power-on timing control solution can ensure that all components work together when the computer is turned on, effectively avoiding hardware conflicts or damage. However, although the existing timing control circuit can provide power-on signals to each module step by step based on the feedback of the clock signal and the preset power-on sequence after receiving the power-on signal, it is unable to automatically establish a response period after the first module is powered on and detect the response speed of the module based on this. It is unable to prevent the modules controlled by the entire timing circuit from encountering the problem of inaccurate power-on signal feedback time when the response speed of any module is affected by the ambient temperature. Therefore, a mainboard timing control circuit is proposed, which can automatically establish a response period after the first module is powered on and detect the response speed of the module. During the response period, if the power-on completion signal feedback of the detected module is not received, the circuit will automatically limit the power-on signal of the next module to ensure that all modules can be stably started according to the preset sequence. When the response speed of any module is affected by the ambient temperature, the circuit can limit the power-on of the next module and establish a delay period for the detected module, thereby avoiding erroneous alarms, reset operations, and inaccurate power-on signal feedback time. Summary of the invention

[0003] In view of the above technical problems, the object of the present invention is to provide a motherboard timing control circuit, the control circuit includes a feedback unit, the feedback unit includes a first shift register U1, a nineteenth resistor R19, a twentieth resistor R20, a twenty-second resistor R22, a twenty-third resistor R23, and a first connector P1;

[0004] The first pin of the first shift register U1, the second pin of the first shift register U1, and one end of the twentieth resistor R20 are connected to the power supply, the ninth pin of the first shift register U1 is connected to one end of the nineteenth resistor R19 and the other end of the twentieth resistor R20, the eighth pin of the first shift register U1 is connected to one end of the twenty-second resistor R22 and one end of the twenty-third resistor R23, the other end of the twenty-second resistor R22 is connected to the end of the first connector P1, and the other end of the nineteenth resistor R19 and the other end of the twenty-third resistor R23 are connected to the ground.

[0005] Further, the control circuit also includes a conversion unit, which includes a second transistor Q2, a third transistor Q3, a fourth field effect transistor Q4, a seventh transistor Q7, a third diode D3, a fifth diode D5, a first capacitor C1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a fourteenth resistor R14, a sixteenth resistor R16, and a seventeenth resistor R17;

[0006] The collector of the second transistor Q2 is connected to one end of the second resistor R2, one end of the fourth resistor R4, and one end of the sixth resistor R6. The base of the second transistor Q2 is connected to one end of the first resistor R1 and the source of the fourth field effect transistor Q4. The collector of the third transistor Q3 is connected to the other end of the first resistor R1 and one end of the third resistor R3. The base of the third transistor Q3 is connected to the other end of the fourth resistor R4. The drain of the fourth field effect transistor Q4 is connected to one end of the first capacitor C1 and the other end of the second resistor R2. The gate of the fourth field effect transistor Q4 is connected to the cathode of the third diode D3 and one end of the fifth resistor R5. The collector of the seventh transistor Q7 is connected to the third and The anode of the seventh triode Q7 is connected to the cathode of the fifth diode D5 and one end of the seventeenth resistor R17, the emitter of the seventh triode Q7 is connected to one end of the fourteenth resistor R14 and one end of the sixteenth resistor R16, the anode of the fifth diode D5 is connected to the end of the first connector P1, the other end of the third resistor R3, the other end of the sixth resistor R6, and the other end of the fourteenth resistor R14 are connected to the power supply, the emitter of the second triode Q2, the emitter of the third triode Q3, the other end of the first capacitor C1, the other end of the fifth resistor R5, the other end of the sixteenth resistor R16, and the other end of the seventeenth resistor R17 are connected to the ground.

[0007] Further, the control circuit further includes a limiting unit, which includes a second operational amplifier U2, a third operational amplifier U3, a first field effect transistor Q1, a second diode D2, an eighth resistor R8, a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12;

[0008] The in-phase end of the second operational amplifier U2 is connected to one end of the eighth resistor R8, one end of the tenth resistor R10, and the cathode of the second diode D2. The output end of the second operational amplifier U2 is connected to the gate of the first field effect transistor Q1. The in-phase end of the third operational amplifier U3 is connected to one end of the third resistor R3. The inverting end of the third operational amplifier U3 is connected to one end of the eleventh resistor R11 and one end of the twelfth resistor R12. The output end of the third operational amplifier U3 is connected to the anode of the second diode D2. The drain of the first field effect transistor Q1 is connected to the eighth pin of the first shift register U1. The other end of the eighth resistor R8 and the other end of the eleventh resistor R11 are connected to the power supply. The source of the first field effect transistor Q1, the other end of the tenth resistor R10, and the other end of the twelfth resistor R12 are connected to the ground.

[0009] Furthermore, the control circuit further includes a reset unit, which includes a ninth field effect transistor Q9, a sixth diode D6, a seventh resistor R7, a ninth resistor R9, and a second connector P2;

[0010] The gate of the ninth field effect transistor Q9 is connected to the anode of the sixth diode D6 and the end of the second connector P2, the cathode of the sixth diode D6 is connected to one end of the seventh resistor R7, one end of the ninth resistor R9, and the inverting end of the second operational amplifier U2, the other end of the ninth resistor R9 is connected to the power supply, and the other end of the seventh resistor R7, the source of the ninth field effect transistor Q9 and the ground are connected.

[0011] Further, the control circuit further includes a delay unit, which includes a fifth field effect transistor Q5, a sixth field effect transistor Q6, an eighth field effect transistor Q8, a first diode D1, a fourth diode D4, an eighteenth resistor R18, and a twenty-first resistor R21;

[0012] The gate of the fifth field effect transistor Q5 is connected to the anode of the first diode D1 and the gate of the first field effect transistor Q1, the source of the fifth field effect transistor Q5 is connected to the gate of the eighth field effect transistor Q8, one end of the twenty-first resistor R21, and the end of the third connector P3, the drain of the fifth field effect transistor Q5 is connected to the drain of the sixth field effect transistor Q6 and one end of the eighteenth resistor R18, the gate of the sixth field effect transistor Q6 is connected to the output end of the third operational amplifier U3, the source of the sixth field effect transistor Q6 is connected to the cathode of the fourth diode D4, the drain of the eighth field effect transistor Q8 is connected to the ninth pin of the first shift register U1, the cathode of the first diode D1 is connected to the in-phase end of the second operational amplifier U2, the anode of the fourth diode D4 is connected to the end of the first connector P1, and the source of the eighth field effect transistor Q8, the other end of the eighteenth resistor R18, the other end of the twenty-first resistor R21 and the ground end are connected.

[0013] Furthermore, the control circuit further includes a reset unit, and the reset unit further includes a twenty-fourth resistor R24;

[0014] One end of the twenty-fourth resistor R24 ​​is connected to the gate of the ninth field effect transistor Q9, and the other end of the twenty-fourth resistor R24 ​​is connected to the ground.

[0015] Furthermore, the control circuit further includes a delay unit, and the delay unit further includes a thirteenth resistor R13 and a fifteenth resistor R15;

[0016] One end of the thirteenth resistor R13 is connected to the gate of the sixth field effect transistor Q6, one end of the fifteenth resistor R15 is connected to the gate of the fifth field effect transistor Q5, and the other ends of the thirteenth resistor R13 and the fifteenth resistor R15 are connected to the ground.

[0017] The beneficial effects of the present invention compared with the prior art are:

[0018] The present invention can automatically establish a response period after the first module is powered on, and detect the response speed of the module. During the response period, if the power-on completion signal feedback of the detected module is not received, the circuit will automatically limit the power-on signal of the next module to ensure that all modules can be stably started in a preset order. When the response speed of any module is affected by environmental temperature factors, the power-on of the next module can be restricted while establishing a delay period for the detected module, thereby avoiding erroneous alarms, reset operations, and inaccurate power-on signal feedback time. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 This is a circuit structure diagram provided by the present invention.

[0021] Figure 2 An enlarged view of the first shift register provided by the present invention DETAILED DESCRIPTION

[0022] In order to make the objects and advantages of the present invention more clearly understood, the present invention is specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementations of the present invention, and does not strictly limit the scope of protection specifically requested by the present invention.

[0023] The present invention discloses a motherboard timing control circuit, the control circuit includes a feedback unit, the feedback unit includes a first shift register U1, a nineteenth resistor R19, a twentieth resistor R20, a twenty-second resistor R22, a twenty-third resistor R23, and a first connector P1;

[0024] The first pin of the first shift register U1, the second pin of the first shift register U1, and one end of the twentieth resistor R20 are connected to the power supply, the ninth pin of the first shift register U1 is connected to one end of the nineteenth resistor R19 and the other end of the twentieth resistor R20, the eighth pin of the first shift register U1 is connected to one end of the twenty-second resistor R22 and one end of the twenty-third resistor R23, the other end of the twenty-second resistor R22 is connected to the end of the first connector P1, and the other end of the nineteenth resistor R19 and the other end of the twenty-third resistor R23 are connected to the ground.

[0025] Specifically, the control circuit further includes a conversion unit, which includes a second transistor Q2, a third transistor Q3, a fourth field effect transistor Q4, a seventh transistor Q7, a third diode D3, a fifth diode D5, a first capacitor C1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a fourteenth resistor R14, a sixteenth resistor R16, and a seventeenth resistor R17;

[0026] The collector of the second transistor Q2 is connected to one end of the second resistor R2, one end of the fourth resistor R4, and one end of the sixth resistor R6. The base of the second transistor Q2 is connected to one end of the first resistor R1 and the source of the fourth field effect transistor Q4. The collector of the third transistor Q3 is connected to the other end of the first resistor R1 and one end of the third resistor R3. The base of the third transistor Q3 is connected to the other end of the fourth resistor R4. The drain of the fourth field effect transistor Q4 is connected to one end of the first capacitor C1 and the other end of the second resistor R2. The gate of the fourth field effect transistor Q4 is connected to the cathode of the third diode D3 and one end of the fifth resistor R5. The collector of the seventh transistor Q7 is connected to the third and The anode of the seventh triode Q7 is connected to the cathode of the fifth diode D5 and one end of the seventeenth resistor R17, the emitter of the seventh triode Q7 is connected to one end of the fourteenth resistor R14 and one end of the sixteenth resistor R16, the anode of the fifth diode D5 is connected to the end of the first connector P1, the other end of the third resistor R3, the other end of the sixth resistor R6, and the other end of the fourteenth resistor R14 are connected to the power supply, the emitter of the second triode Q2, the emitter of the third triode Q3, the other end of the first capacitor C1, the other end of the fifth resistor R5, the other end of the sixteenth resistor R16, and the other end of the seventeenth resistor R17 are connected to the ground.

[0027] Specifically, the control circuit further includes a limiting unit, which includes a second operational amplifier U2, a third operational amplifier U3, a first field effect transistor Q1, a second diode D2, an eighth resistor R8, a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12;

[0028] The in-phase end of the second operational amplifier U2 is connected to one end of the eighth resistor R8, one end of the tenth resistor R10, and the cathode of the second diode D2. The output end of the second operational amplifier U2 is connected to the gate of the first field effect transistor Q1. The in-phase end of the third operational amplifier U3 is connected to one end of the third resistor R3. The inverting end of the third operational amplifier U3 is connected to one end of the eleventh resistor R11 and one end of the twelfth resistor R12. The output end of the third operational amplifier U3 is connected to the anode of the second diode D2. The drain of the first field effect transistor Q1 is connected to the eighth pin of the first shift register U1. The other end of the eighth resistor R8 and the other end of the eleventh resistor R11 are connected to the power supply. The source of the first field effect transistor Q1, the other end of the tenth resistor R10, and the other end of the twelfth resistor R12 are connected to the ground.

[0029] Specifically, the control circuit further includes a reset unit, which includes a ninth field effect transistor Q9, a sixth diode D6, a seventh resistor R7, a ninth resistor R9, and a second connector P2;

[0030] The gate of the ninth field effect transistor Q9 is connected to the anode of the sixth diode D6 and the end of the second connector P2, the cathode of the sixth diode D6 is connected to one end of the seventh resistor R7, one end of the ninth resistor R9, and the inverting end of the second operational amplifier U2, the other end of the ninth resistor R9 is connected to the power supply, and the other end of the seventh resistor R7, the source of the ninth field effect transistor Q9 and the ground are connected.

[0031] Specifically, the control circuit further includes a delay unit, which includes a fifth field effect transistor Q5, a sixth field effect transistor Q6, an eighth field effect transistor Q8, a first diode D1, a fourth diode D4, an eighteenth resistor R18, and a twenty-first resistor R21;

[0032] The gate of the fifth field effect transistor Q5 is connected to the anode of the first diode D1 and the gate of the first field effect transistor Q1, the source of the fifth field effect transistor Q5 is connected to the gate of the eighth field effect transistor Q8, one end of the twenty-first resistor R21, and the end of the third connector P3, the drain of the fifth field effect transistor Q5 is connected to the drain of the sixth field effect transistor Q6 and one end of the eighteenth resistor R18, the gate of the sixth field effect transistor Q6 is connected to the output end of the third operational amplifier U3, the source of the sixth field effect transistor Q6 is connected to the cathode of the fourth diode D4, the drain of the eighth field effect transistor Q8 is connected to the ninth pin of the first shift register U1, the cathode of the first diode D1 is connected to the in-phase end of the second operational amplifier U2, the anode of the fourth diode D4 is connected to the end of the first connector P1, and the source of the eighth field effect transistor Q8, the other end of the eighteenth resistor R18, the other end of the twenty-first resistor R21 and the ground end are connected.

[0033] Specifically, the control circuit further includes a reset unit, and the reset unit further includes a twenty-fourth resistor R24;

[0034] One end of the twenty-fourth resistor R24 ​​is connected to the gate of the ninth field effect transistor Q9, and the other end of the twenty-fourth resistor R24 ​​is connected to the ground.

[0035] Specifically, the control circuit further includes a delay unit, and the delay unit further includes a thirteenth resistor R13 and a fifteenth resistor R15;

[0036] One end of the thirteenth resistor R13 is connected to the gate of the sixth field effect transistor Q6, one end of the fifteenth resistor R15 is connected to the gate of the fifth field effect transistor Q5, and the other ends of the thirteenth resistor R13 and the fifteenth resistor R15 are connected to the ground.

[0037] See attached Figure 1A clock unit is provided in the control circuit, and the first connector P1 end is used to receive a clock signal, and the clock signal is fed back by the clock unit. Pins 1 and 2 of the first shift register U1 are input pins, pins 3-6 and pins 10-13 are output pins, pin 8 is an input pin for the clock signal, and pin 9 is a reset pin. The signal at the first connector P1 end passes through the twenty-second resistor R22 and the twenty-third resistor R23 to the ground end, and the signal at the twenty-third resistor R23 end is fed back to pin 8 of the first shift register U1. When pin 8 of the first shift register U1 obtains a rising edge signal each time, the output pins of the first shift register U1 are output in sequence, and the sequence is pins 3, Pin 4, pin 5, pin 6, pin 10, pin 11, pin 12, pin 13, the signal of the output pin of the first shift register U1 is the power-on signal for controlling each module to obtain power. When the output pin is at a high level, the corresponding power-on module obtains the power signal. The power supply voltage of each module is adjusted and fed back by the DC-DC module. If too many modules need to control the timing of power-on, a shift register with a higher number of bits can be used. The power signal passes through the twentieth resistor R20 and the nineteenth resistor R19 to the ground terminal. The signal at the end of the nineteenth resistor R19 is fed back to pin 9 of the first shift register U1. When the end of the nineteenth resistor R19 is at a low level, the first shift register U1 is reset.

[0038] See attached Figure 1 In the initial state, the power supply signal is fed to the ground terminal through the fourteenth resistor R14 and the sixteenth resistor R16, the signal at the end of the sixteenth resistor R16 is fed to the ground terminal through the emitter of the seventh transistor Q7, the base of the seventh transistor Q7 and the seventeenth resistor R17, the emitter of the seventh transistor Q7 and the base of the seventh transistor Q7 are forward biased, the seventh transistor Q7 is turned on, the signal at the end of the sixteenth resistor R16 is fed back to the gate of the fourth field effect transistor Q4 through the seventh transistor Q7 and the third diode D3, the fifth resistor R5 is used to discharge the parasitic capacitance of the gate of the fourth field effect transistor Q4, the differential voltage between the gate of the fourth field effect transistor Q4 and the source of the fourth field effect transistor Q4 is higher than the turn-on threshold, the fourth field effect transistor Q4 is turned on, and the power supply signal is fed back to the gate of the fourth field effect transistor Q4 through the sixth resistor R6 and the second resistor R2. The potential of a capacitor C1 rises, and the power signal is fed back to the base of the second transistor Q2 via the third resistor R3 and the first resistor R1. Due to the capacitance characteristics of the first capacitor C1, the potential of the first capacitor C1 terminal is the same as the potential of the base terminal of the second transistor Q2. During the period when the potential of the first capacitor C1 terminal rises, the power signal passes through the sixth resistor R6, the fourth resistor R4, the base of the third transistor Q3, and the emitter of the third transistor Q3 to the ground terminal. The base of the third transistor Q3 and the emitter of the third transistor Q3 are forward biased, and the third transistor Q3 is turned on. The power signal passes through the third resistor R3, the collector of the third transistor Q3, and the emitter of the third transistor Q3 to the ground terminal. The potential of the collector terminal of the third transistor Q3 is low, and the collector terminal of the second transistor Q2 is high.

[0039] See attached Figure 1 When the first connector P1 receives the first clock signal, the signal at the first connector P1 is at the rising edge of the clock signal, the signal at the first connector P1 is connected to the ground via the fifth diode D5 and the seventeenth resistor R17, the base of the seventh transistor Q7 obtains the signal feedback from the first connector P1, the seventh transistor Q7 is turned off, the fourth field effect transistor Q4 is turned off, the potential at the first capacitor C1 continues to rise, and the potential at the collector end of the second transistor Q2 is pulled high. When the signal at the first connector P1 is at the falling edge of the first clock signal, the fourth field effect transistor Q4 is turned on, and the signal at the first capacitor C1 is connected to the ground via the drain of the fourth field effect transistor Q4, the source of the fourth field effect transistor Q4, the base of the second transistor Q2, and the emitter of the second transistor Q2. To the ground end, the second transistor Q2 is turned on, the potential of the first capacitor C1 drops to the potential of the base terminal of the second transistor Q2, the potential of the collector terminal of the second transistor Q2 is pulled low, the third transistor Q3 is turned off, and the potential of the collector terminal of the third transistor Q3 is pulled high. At this time, the first connector P1 end completes the reception of the first clock signal. When the signal at the first connector P1 end changes from the rising edge to the falling edge again, the potential of the collector terminal of the third transistor Q3 changes from high to low, and the conversion unit returns to the initial state. At this time, the first connector P1 end completes the reception of the second clock signal. Therefore, every time the first connector P1 end completes the reception of a clock signal, the collector terminal level of the third transistor Q3 is converted to provide a signal basis for the limiting unit and the delay unit.

[0040] See attached Figure 1, the power signal reaches the ground terminal through the eleventh resistor R11 and the twelfth resistor R12, the signal at the end of the twelfth resistor R12 is fed back to the inverting terminal of the third operational amplifier U3, the collector terminal signal of the third transistor Q3 is fed back to the non-inverting terminal of the third operational amplifier U3, the power signal reaches the ground terminal through the eighth resistor R8 and the tenth resistor R10, the signal at the end of the tenth resistor R10 is fed back to the non-inverting terminal of the second operational amplifier U2, when the first connector P1 completes the reception of the first clock signal, when the collector terminal of the third transistor Q3 is at a high level, the third operational amplifier U3 outputs, the output terminal signal of the third operational amplifier U3 is clamped on the non-inverting terminal voltage signal of the second operational amplifier U2 after passing through the second diode D2 and the tenth resistor R10, and at the same time the second The operational amplifier U2 outputs, and the output signal of the second operational amplifier U2 is fed back to the gate of the first field effect transistor Q1. The voltage difference between the gate of the first field effect transistor Q1 and the source of the first field effect transistor Q1 is higher than the conduction threshold, and the first field effect transistor Q1 is turned on. The signal at the end of the twenty-third resistor R23 passes through the drain of the first field effect transistor Q1 and the source of the first field effect transistor Q1 to the ground terminal, and the 8th pin of the first shift register U1 is pulled to the ground potential. Therefore, when the first connector P1 end is at the rising edge of the first clock signal, the output pin of the first shift register U1 can immediately feed back a power-on signal to a module in sequence, and at the same time, after the output pin of the first shift register U1 feeds back a power-on signal, the power-on signal of the next module is power-on restricted.

[0041] See attached Figure 1The second connector P2 end is used to receive the power-on completion signal fed back by the power-on module. Each module to be powered on will feed back a power-on completion signal to the control circuit after the power-on is completed. When the module that obtains the power-on signal does not feed back the power-on completion signal, the module is the detected module. The time from the power-on of the first module to the power-on of the second module is the response period of the power-on completion signal. When the second connector P2 end obtains the power-on completion signal feedback of the detected module before the first connector P1 end receives the second clock signal (within the response period), the second connector P2 end obtains the power-on completion signal feedback of the detected module. When the signal is obtained, it is a high level, otherwise it is a low level. The signal at the second connector P2 end is fed back to the gate of the ninth field effect tube Q9. The twenty-fourth resistor R24 ​​is used to discharge the parasitic capacitance of the gate of the ninth field effect tube Q9. When the second connector P2 end is at a high level, the voltage difference between the gate of the ninth field effect tube Q9 and the source of the ninth field effect tube Q9 is higher than the conduction threshold, the ninth field effect tube Q9 is turned on, and the collector terminal signal of the third transistor Q3 is connected to the ground terminal through the drain of the ninth field effect tube Q9 and the source of the ninth field effect tube Q9. The collector terminal signal of the third transistor Q3 is pulled low, and the conversion unit The first operational amplifier U2 is reset to the initial state, the third operational amplifier U3 is turned off, the power supply signal passes through the ninth resistor R9 and the seventh resistor R7 to the ground terminal, the signal at the seventh resistor R7 end is fed back to the inverting terminal of the second operational amplifier U2, and the signal at the second connector P2 end passes through the sixth diode D6 and the seventh resistor R7 to the ground terminal. When the second connector P2 end is at a high level, the seventh resistor R7 end clamps the voltage signal at the inverting terminal of the second operational amplifier U2 after passing through the sixth diode D6 and the seventh resistor R7. The signal at the seventh resistor R7 end is higher than the signal at the tenth resistor R10 end. At the same time, the second operational amplifier U2 is turned off, and the first field effect transistor Q1 is turned off. When the control circuit obtains the power-on completion signal of the detected module within the response period, the power-on signal of the next module is released from restriction, so that it can normally obtain the feedback of the power-on signal. In this way, the response period is automatically established after the first module is powered on, and the response speed of the module is detected. During the response period, if the power-on completion signal feedback of the detected module is not received, the circuit will automatically limit the power-on signal of the next module to ensure that all modules can be stably started in a preset order.

[0042] See attached Figure 1, considering that when the response speed of any module is affected by the ambient temperature, the module controlled by the entire timing circuit will encounter the problem of inaccurate power-on signal feedback time. Therefore, it is necessary to establish a delay period for the detected module while limiting the power-on of the next module, so as to avoid erroneous alarms, reset operations, and the problem of inaccurate power-on signal feedback time. When the first connector P1 completes the reception of the first clock signal, the third operational amplifier U3 outputs, the second operational amplifier U2 outputs, and the output signal of the third operational amplifier U3 is fed back to the gate of the sixth field effect transistor Q6. The thirteenth resistor R13 is used to discharge the parasitic capacitance of the gate of the sixth field effect transistor Q6. The gate of the sixth field effect transistor Q6 and The voltage difference between the source of the sixth field effect tube Q6 is higher than the conduction threshold, the sixth field effect tube Q6 is turned off, and at the same time, the output end signal of the second operational amplifier U2 is fed back to the gate of the fifth field effect tube Q5, the fifteenth resistor R15 is used to discharge the parasitic capacitance of the gate of the fifth field effect tube Q5, the voltage difference between the gate of the fifth field effect tube Q5 and the source of the fifth field effect tube Q5 is higher than the conduction threshold, the fifth field effect tube Q5 is turned on, when the first connector P1 end completes the reception of the second clock signal, the third operational amplifier U3 is turned off, the output end signal of the second operational amplifier U2 is clamped to its in-phase end through the first diode D1 and the tenth resistor R10 so that the second operational amplifier U2 can always output, at this time the sixth field effect tube Q6 is turned on, the fifth field effect tube Q5 is turned on, and the fifth field effect tube Q5 is turned on. The effect tube Q5 is turned on, and the time from the rising edge of the second clock signal to the rising edge of the third clock signal is the delay period. During the delay period, if the second connector P2 end obtains signal feedback, the third operational amplifier U3 and the second operational amplifier U2 will be in the cut-off state, and the conversion unit and the limiting unit will be reset to the initial state. At this time, when the first connector P1 end receives the clock signal again, the next module can normally obtain the power-on signal. During the delay period, if the second connector P2 end still does not obtain signal feedback, when the first connector P1 end obtains the clock signal again, at this time, the signal at the first connector P1 end is at the rising edge of the clock signal, and the signal at the first connector P1 end is transmitted through the fourth diode D4, the source of the sixth field effect tube Q6, and the sixth field The drain of the field effect transistor Q6 and the eighteenth resistor R18 are connected to the ground terminal. The signal at the end of the eighteenth resistor R18 is connected to the ground terminal via the drain of the fifth field effect transistor Q5, the source of the fifth field effect transistor Q5 and the twenty-first resistor R21. The signal at the end of the twenty-first resistor R21 is fed back to the gate of the eighth field effect transistor Q8. The voltage difference between the gate of the eighth field effect transistor Q8 and the source of the eighth field effect transistor Q8 is higher than the turn-on threshold. The eighth field effect transistor Q8 is turned on. The signal at the end of the nineteenth resistor R19 is pulled down to the ground potential. The first shift register U1 is reset. An alarm unit is also provided in the control circuit. The signal at the end of the twenty-first resistor R21 is fed back to the clock unit and the alarm unit via the third connector P3. The clock unit stops feeding back the clock signal, and the alarm unit gives an alarm.

[0043] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations within the meaning and scope of the equivalent elements of the claims be included in the invention. Any marking in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A motherboard timing control circuit, characterized in that: The control circuit includes a feedback unit, and the feedback unit includes a first shift register, a nineteenth resistor, a twentieth resistor, a twenty-second resistor, a twenty-third resistor, and a first connector; The first pin of the first shift register, the second pin of the first shift register, and one end of the twentieth resistor are connected to the power supply, the ninth pin of the first shift register is connected to one end of the nineteenth resistor and the other end of the twentieth resistor, the eighth pin of the first shift register is connected to one end of the twenty-second resistor and one end of the twenty-third resistor, the other end of the twenty-second resistor is connected to the first connector end, and the other end of the nineteenth resistor and the other end of the twenty-third resistor are connected to the ground end; The control circuit also includes a conversion unit, which includes a second triode, a third triode, a fourth field effect transistor, a seventh triode, a third diode, a fifth diode, a first capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a fourteenth resistor, a sixteenth resistor, and a seventeenth resistor; The collector of the second triode is connected to one end of the second resistor, one end of the fourth resistor, and one end of the sixth resistor, the base of the second triode is connected to one end of the first resistor and the source of the fourth field effect transistor, the collector of the third triode is connected to the other end of the first resistor and one end of the third resistor, the base of the third triode is connected to the other end of the fourth resistor, the drain of the fourth field effect transistor is connected to one end of the first capacitor and the other end of the second resistor, the gate of the fourth field effect transistor is connected to the cathode of the third diode and one end of the fifth resistor, the collector of the seventh triode is connected to the anode of the third diode, the base of the seventh triode is connected to the cathode of the fifth diode and one end of the seventeenth resistor, the emitter of the seventh triode is connected to one end of the fourteenth resistor and one end of the sixteenth resistor, the anode of the fifth diode is connected to the end of the first connector, the other end of the third resistor, the other end of the sixth resistor, the other end of the fourteenth resistor are connected to the power supply, and the emitter of the second triode, the emitter of the third triode, the other end of the first capacitor, the other end of the fifth resistor, the other end of the sixteenth resistor, and the other end of the seventeenth resistor are connected to the ground terminal; The control circuit further includes a limiting unit, which includes a second operational amplifier, a third operational amplifier, a first field effect transistor, a second diode, an eighth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor; The in-phase end of the second operational amplifier is connected to one end of the eighth resistor, one end of the tenth resistor, and the cathode of the second diode. The output end of the second operational amplifier is connected to the gate of the first field effect transistor. The in-phase end of the third operational amplifier is connected to one end of the third resistor. The inverting end of the third operational amplifier is connected to one end of the eleventh resistor and one end of the twelfth resistor. The output end of the third operational amplifier is connected to the anode of the second diode. The drain of the first field effect transistor is connected to the eighth pin of the first shift register. The other end of the eighth resistor and the other end of the eleventh resistor are connected to the power supply. The source of the first field effect transistor, the other end of the tenth resistor, the other end of the twelfth resistor and the ground are connected.

2. The motherboard timing control circuit according to claim 1, characterized in that: The control circuit further includes a reset unit, which includes a ninth field effect transistor, a sixth diode, a seventh resistor, a ninth resistor, and a second connector; The gate of the ninth field effect tube is connected to the anode of the sixth diode and the second connector end, the cathode of the sixth diode is connected to one end of the seventh resistor, one end of the ninth resistor, and the inverting end of the second operational amplifier, the other end of the ninth resistor is connected to the power supply, and the other end of the seventh resistor, the source of the ninth field effect tube and the ground end are connected.

3. The motherboard timing control circuit according to claim 1, characterized in that: The control circuit further includes a delay unit, which includes a fifth field effect transistor, a sixth field effect transistor, an eighth field effect transistor, a first diode, a fourth diode, an eighteenth resistor, and a twenty-first resistor; The gate of the fifth field effect transistor is connected to the anode of the first diode and the gate of the first field effect transistor, the source of the fifth field effect transistor is connected to the gate of the eighth field effect transistor, one end of the twenty-first resistor, and the third connector end, the drain of the fifth field effect transistor is connected to the drain of the sixth field effect transistor and one end of the eighteenth resistor, the gate of the sixth field effect transistor is connected to the output end of the third operational amplifier, the source of the sixth field effect transistor is connected to the cathode of the fourth diode, the drain of the eighth field effect transistor is connected to the ninth pin of the first shift register, the cathode of the first diode is connected to the in-phase end of the second operational amplifier, the anode of the fourth diode is connected to the first connector end, and the source of the eighth field effect transistor, the other end of the eighteenth resistor, the other end of the twenty-first resistor, and the ground end are connected.

4. The motherboard timing control circuit according to claim 2, characterized in that: The control circuit further includes a reset unit, and the reset unit further includes a twenty-fourth resistor; One end of the twenty-fourth resistor is connected to the gate of the ninth field effect transistor, and the other end of the twenty-fourth resistor is connected to the ground.

5. The motherboard timing control circuit according to claim 3, characterized in that: The control circuit further includes a delay unit, and the delay unit further includes a thirteenth resistor and a fifteenth resistor; One end of the thirteenth resistor is connected to the gate of the sixth field effect transistor, one end of the fifteenth resistor is connected to the gate of the fifth field effect transistor, and the other ends of the thirteenth resistor and the fifteenth resistor are connected to the ground end.

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