Data storage method and device and computer readable medium

Abstract

The invention provides a data storage method, data is stored in a storage module comprising a plurality of RAMs, each RAM comprises a plurality of physical rows, and the method comprises the following steps: determining a logic address used for storing target data to be stored according to the occupation condition of the storage module; each logic address represents a logic row and a position in the logic row, and each logic row is composed of a plurality of physical rows from different RAMs respectively; determining a real address of the to-be-stored target data according to the determined logic address; the real address is a physical address of a storage space corresponding to the logic address in the RAM; and storing the target data to be stored in the storage module according to the determined real address. The invention further provides data storage equipment and a computer readable medium.

Description

Technical Field

[0001] The present disclosure relates to the technical field of data storage, and in particular to a method and device for data storage, and a computer-readable medium. Background Art

[0002] Part of the content of the routing entry can be stored in a random access memory (RAM).

[0003] However, in the existing method, the RAM for storing routing entries may have large holes, resulting in a waste of resources. Summary of the invention

[0004] The present disclosure provides a data storage method and device, and a computer-readable medium.

[0005] In a first aspect, an embodiment of the present disclosure provides a method for storing data, wherein the data is stored in a storage module including a plurality of RAMs, each of the RAMs including a plurality of physical rows; the method of the embodiment of the present disclosure includes:

[0006] Determine a logical address for storing the target data to be stored according to the occupancy of the storage module; each of the logical addresses represents a logical row and a position in the logical row, and each of the logical rows is composed of a plurality of physical rows from different RAMs;

[0007] Determine the real address of the target data to be stored according to the determined logical address; the real address is the physical address of the storage space corresponding to the logical address in the RAM;

[0008] According to the determined real address, the target data to be stored is stored in the storage module.

[0009] In a second aspect, an embodiment of the present disclosure provides a data storage device, comprising:

[0010] A storage module, comprising a plurality of RAMs, each of the RAMs comprising a plurality of physical rows;

[0011] An address mapping unit, which is used to determine a real address according to a logical address of the target data; each of the logical addresses represents a logical row and a position in the logical row, each of the logical rows is composed of a plurality of physical rows from different RAMs, and the real address is a physical address of a storage space corresponding to the logical address in the RAM;

[0012] The splicing unit is used to splice different parts of the same target data read from different physical rows to obtain the target data.

[0013] In a third aspect, an embodiment of the present disclosure provides a computer-readable medium having a computer program stored thereon, and when the computer program is executed by a processor, any one of the data storage methods of the embodiments of the present disclosure is implemented.

[0014] In the embodiment of the present disclosure, multiple physical rows are "joined" into a "large" logical row, and each target data is stored in a logical row (of course, each logical row can store multiple target data); and because different physical rows in each logical row come from different RAMs, each target data can be stored in one physical row or in physical rows of multiple different RAMs, that is, all physical rows (that is, logical rows) where each target data is located can be read at the same time; therefore, while ensuring that each target data can be read "all at once", the embodiment of the present disclosure no longer requires that each target data must be stored in one physical row, but one target data can be divided into different physical rows (of course, they must be physical rows of different RAMs), so when the remaining space in a physical row is not enough to store another target data, it can still be used to store part of the target data, thereby reducing holes and improving resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In the accompanying drawings of the embodiments of the present disclosure:

[0016] Figure 1 A flowchart of a data storage method provided by an embodiment of the present disclosure;

[0017] Figure 2 A flowchart of another data storage method provided by an embodiment of the present disclosure;

[0018] Figure 3 A block diagram of a data storage device provided in an embodiment of the present disclosure;

[0019] Figure 4 A block diagram of another data storage device provided in an embodiment of the present disclosure;

[0020] Figure 5 A schematic diagram of a routing entry processing process in a data storage method provided by an embodiment of the present disclosure;

[0021] Figure 6 A schematic diagram of a process of storing target data in a logical row in a data storage method provided by an embodiment of the present disclosure;

[0022] Figure 7 A schematic diagram of a process of reading target data in a data storage method provided by an embodiment of the present disclosure;

[0023] Figure 8 A block diagram of a computer-readable medium provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the data storage method and device, and computer-readable medium provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0025] The present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as being limited to the embodiments set forth below. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete, and will enable those skilled in the art to fully understand the scope of the present disclosure.

[0026] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification, and are used together with the detailed embodiments to explain the present disclosure, and do not constitute a limitation of the present disclosure. By describing the detailed embodiments with reference to the accompanying drawings, the above and other features and advantages will become more apparent to those skilled in the art.

[0027] The present disclosure may be described with reference to plan views and / or cross-sectional views by means of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0028] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0029] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure. The term "and / or" as used in the present disclosure includes any and all combinations of one or more related enumerated items. The singular forms "one" and "the" as used in the present disclosure are also intended to include plural forms, unless the context clearly indicates otherwise. The terms "including", "made of..." as used in the present disclosure specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this disclosure.

[0031] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0032] Routing service is a mandatory function of network processor chips. To support this function, it is necessary to store the routing entries issued by users (i.e. the mapping relationship between prefix routing and egress). Therefore, it is desirable to use the minimum storage resources to store these routing entries (routing tables) while ensuring the correctness of the routing function.

[0033] In some related technologies, routing entries may be stored in the form of a trie (prefix tree), where the prefix tree includes a plurality of nodes, wherein the child nodes of any node have the same prefix.

[0034] For example, the routing forwarding system is divided into a control plane and a forwarding plane. The control plane (software) receives the user's routing entries and sends them to the routing storage system through the routing storage algorithm. The forwarding plane (hardware) receives the routing search request key, matches based on the routing entries sent by the control plane, and outputs the longest prefix matching result.

[0035] In order to reduce the forwarding plane delay and storage resource overhead, the entire prefix tree can be split into multiple smaller subtrees and a multi-level storage architecture can be used. For example, in a two-level storage architecture, the first-level storage structure can use a ternary content addressable memory (TCAM) and a HASH table to store the root node of the subtree; while the second-level storage structure can use a random access memory (RAM) to reduce costs and store the child nodes of the subtree (nodes storing actual rules).

[0036] When searching for routing entries on the forwarding plane, a match is usually performed in the first-level storage structure first, and then the longest prefix match is used in the subtree of the hit root node to further search for matching rules. However, due to the principle limitation of RAM, it can only read one row (physical row) of data at a time, so the data of all child nodes of each subtree should be stored in one physical row to ensure that all child nodes can be read out and matched at the same time when the root node is matched. However, since the prefix tree is established based on a set of rules, the prefix tree is usually sparse and very unbalanced, that is, the sizes of different subtrees may vary greatly, resulting in that if the largest subtree can be stored in one physical row, there may be a lot of free space in the physical row storing other smaller subtrees, and the holes are large, resulting in a waste of resources.

[0037] First, refer to Figures 1 to 7An embodiment of the present disclosure provides a method for storing data, wherein the data is stored in a storage module including a plurality of random access memories RAM, each RAM including a plurality of physical rows.

[0038] The disclosed embodiments are used to store (and of course read) data in a storage module composed of a plurality of random access memories (RAMs), and are specifically used to store and read "target data".

[0039] In some embodiments, each target data is data of all child nodes of a subtree of the prefix tree of the routing entry.

[0040] The target data stored in the embodiment of the present disclosure may specifically be the data of all child nodes of a subtree of a prefix tree (trie) of the routing entry.

[0041] Please refer to Figure 5 After the routing entry is constructed in the form of a prefix tree, it is split into multiple subtrees according to the subtrie selection algorithm, and the first-level storage algorithm is used to determine how the root node of each subtree is stored in the TCAM, HASH table, etc., and the second-level storage algorithm is used to determine how the child nodes of each subtree are stored in the RAM; therefore, the embodiment of the present disclosure is the above "second-level storage algorithm".

[0042] It should be understood that how the target data is processed in the embodiments of the present disclosure has no necessary relationship with how the prefix tree is established, how the subtrees are split, how the root nodes of the subtrees are stored, etc.

[0043] It should be understood that the embodiments of the present disclosure are not limited to the storage of data of the sub-nodes of the sub-tree, and any data that meets the requirements of the embodiments of the present disclosure can be used as target data.

[0044] Reference Figure 1 , the method of the embodiment of the present disclosure includes:

[0045] S101. Determine a logical address for storing target data to be stored according to the occupancy of a storage module.

[0046] Each logical address represents a logical row and a position in the logical row, and each logical row is composed of a plurality of physical rows from different RAMs.

[0047] Reference Figure 6 The storage module used in the embodiment of the present disclosure includes multiple RAMs, and each RAM includes a storage space composed of multiple physical rows.

[0048] Reference Figure 6When storing data, the disclosed embodiment "regards" multiple physical rows from different RAMs as one logical row (any logical row includes multiple physical rows of different RAMs), or in other words, each logical row is equivalent to a "big row" "spliced" from multiple physical rows of different RAMs.

[0049] Therefore, each target data may be stored in a logical row, so the target data has a corresponding logical address in the "logical storage space", and the logical address represents that the target data is stored at a certain position in a certain logical row.

[0050] It should be understood that the specific forms of the above logical addresses are various, such as including start and end addresses, or including the start address and the length of the target data (of course, the target data must be continuous), which will not be described in detail here.

[0051] Since each logical row includes multiple physical rows of different RAMs, Figure 6 , the target data stored in a logical row may be actually stored in one physical row (such as target data 1), or may be actually stored in multiple physical rows (such as target data 2), but the above multiple physical rows must be physical rows of different RAMs, that is, the embodiment of the present disclosure can ensure that one target data cannot be stored in different physical rows of a RAM.

[0052] It should be understood that to ensure that the target data can be stored in a logical row, the length of the target data must be less than or equal to the maximum possible length of the logical row (i.e., the number of RAMs * the physical row width). Further, the length of the target data can be less than or equal to the width of the physical row.

[0053] Among them, the length of the above target data can be limited by the algorithm that generates the target data, such as setting the above sub-tree selection algorithm to ensure that the total data volume of all child nodes (target data) of any subtree split out is less than the width of a physical row.

[0054] S102. Determine the real address of the target data to be stored according to the determined logical address.

[0055] The real address is the physical address of the storage space corresponding to the logical address in the RAM.

[0056] It can be seen that the logical address represents the position in the "logical storage space", but the actual storage space is the space located in the physical rows of the RAM, that is, the storage space corresponding to each logical address is actually located in one or more physical rows, and the physical address of the above storage space is the real address corresponding to the logical address, that is, a certain position in a certain physical row of a certain RAM.

[0057] It should be understood that the specific forms of the above real addresses are also diverse, such as including start and end addresses, or including the start address and the length of the target data (of course, the target data must be continuous), which will not be described in detail here.

[0058] In this step, the corresponding real address is determined based on the above logical address.

[0059] S103. Store the target data to be stored in a storage module according to the determined real address.

[0060] After the real address corresponding to each target data is determined, the target data is stored in the storage space according to the real address, that is, different parts of the target data are respectively stored at the real address position of one or more physical rows corresponding to the logical address.

[0061] In the embodiment of the present disclosure, multiple physical rows are "joined" into a "large" logical row, and each target data is stored in a logical row (of course, each logical row can store multiple target data); and because different physical rows in each logical row come from different RAMs, each target data can be stored in one physical row or in physical rows of multiple different RAMs, that is, all physical rows (that is, logical rows) where each target data is located can be read at the same time; therefore, while ensuring that each target data can be read "all at once", the embodiment of the present disclosure no longer requires that each target data must be stored in one physical row, but one target data can be divided into different physical rows (of course, they must be physical rows of different RAMs), so when the remaining space in a physical row is not enough to store another target data, it can still be used to store part of the target data, thereby reducing holes and improving resource utilization.

[0062] In some embodiments, reference Figure 2 According to the determined real address, storing the target data to be stored in the storage module (S103) includes:

[0063] S1031 . In response to the determined real address corresponding to multiple physical rows, the target data to be stored is stored sequentially and continuously in the multiple physical rows.

[0064] Reference Figure 6 When a target data in a logical row is actually to be stored in multiple physical rows, it can be stored in each physical row "continuously" and "sequentially", that is, the content of the target data is written from the first physical row (such as physical row 0), and when the physical row is used up, the remaining content of the target data is continued to be written from the beginning of the next physical row (such as physical row 1).

[0065] In this way, it can be ensured as much as possible that the target data is stored in a logically continuous space, which makes it easier to correspond the real address and the logical address.

[0066] In some embodiments, reference Figure 2 The data storage method of the embodiment of the present disclosure further includes:

[0067] S104 . Determine a real address for storing the target data to be read according to the logical address of the target data to be read.

[0068] S105 . Read the target data to be read from the storage module according to the real address of the target data to be read.

[0069] S106 . In response to different parts of the target data to be read being located in different physical rows, the different parts are spliced ​​to obtain the target data to be read.

[0070] Reference Figure 2 After writing part of the target data into the storage module in the above manner, if there is a requirement to read a certain target data therefrom (such as the root node of the corresponding subtree matches), the logical address of the target data is directly obtained; therefore, the real address corresponding to the logical address should be further determined, and the target data should be actually read from the corresponding physical row according to the real address.

[0071] Among them, if the target data is stored in multiple physical rows, what is read from each physical row is a part of the target data, that is, the target data directly read out is divided into multiple parts, rather than a whole, so it is also necessary to "splice" the different parts read out to obtain the complete target data.

[0072] In some embodiments, reference Figure 2 , reading the target data to be read from the storage module according to the real address of the target data to be read (S105) includes:

[0073] S1051. Read all data of all physical rows corresponding to the real addresses from the storage module.

[0074] In response to different parts of the target data to be read being located in different physical rows, splicing the different parts to obtain the target data to be read (S106) includes:

[0075] S1061. In response to different parts of the target data to be read being located in different physical rows, the data of multiple physical rows read are sequentially spliced ​​to form data to be intercepted, and according to the real address of the target data to be read, an interception segment including the target data to be read is obtained from the data to be intercepted.

[0076] RAM usually directly reads out "all" the data of a physical row at a time, so when reading the above target data, the data of all the physical rows in which it is located can be read out at the same time.

[0077] Furthermore, if the content of the target data is distributed in multiple physical rows, the data of the multiple physical rows will be read out at the same time.

[0078] Therefore, we can refer to Figure 7 , the data of these physical rows are "joined" together in sequence to form a "data to be intercepted (which can be a logical row, or a part of a logical row)"; then, according to the real address of the target data to be read, a part of the data to be intercepted is intercepted as a "intercepted segment", which includes the required target data (such as target data 2), so obtaining the intercepted segment is equivalent to obtaining the target data.

[0079] In some embodiments, the intercepted segment starts from the starting position of the target data to be read; the length of the intercepted segment is equal to the width of the physical line.

[0080] Reference Figure 7 As one method of an embodiment of the present disclosure, it is possible to start from the starting position of the target data (such as start_ptr) and intercept data with a length equal to the physical line width (such as W) as the intercepted segment.

[0081] In the related art, when the target data is needed, all the data of a physical row is usually read, and the target data is located at the beginning of the read data (segment). According to the above method, the form of the segment obtained is exactly the same as the data read in the related art (that is, the data length is also W, and the target data is also located at the beginning of the data), so that the subsequent processing of the data is convenient.

[0082] It should be understood that the length of the above-obtained intercepted segment may be greater than the target data, that is, it also includes other content that does not belong to the target data. At this time, the irrelevant content in the intercepted segment can be invalidated through relevant technical means, so as to further obtain the target data that actually works.

[0083] It should be understood that when the real address of the target data corresponds to only one physical row (ie, the target data is located in only one physical row), it is sufficient to read the data of the physical row.

[0084] It should be understood that the specific reading method in the embodiment of the present disclosure is not limited thereto. For example, the portion corresponding to the target data may be directly read from the physical row, and the portions from different physical rows may be spliced ​​when necessary.

[0085] In some embodiments, the number of physical rows in all RAMs is the same, and the width of all physical rows is the same.

[0086] As one embodiment of the present disclosure, from the perspective of simplicity, all RAMs may include the same number of physical rows, and all RAM physical rows may have the same width.

[0087] For example, it can be a reference Figure 6 There are two RAMs (RAM0 and RAM1), the two RAMs include the same number of physical rows, and the width of all physical rows is the same (all W).

[0088] In some embodiments, according to the occupancy of the storage module, determining the logical address for storing the target data to be stored (S101) includes:

[0089] S1011. According to the occupancy of the storage module, a segment tree algorithm is used to determine a logical address for storing the target data to be stored.

[0090] As one method of the embodiment of the present disclosure, a "segment tree algorithm" can be specifically used to determine the logical address of the target data. For example, the length of the segment of the target data to be stored can be determined, and the idle segments whose length is greater than or equal to the length of the segment of the target data can be found from the segment tree, and the logical address for storing the target data can be determined from the idle segments with the smallest length, and then the segment of the target data can be subtracted from the idle segments, and the segment tree can be updated.

[0091] In some embodiments, the method of the present disclosure further includes:

[0092] S1001, multiple RAMs are used as a logical storage space, and a mapping relationship between physical addresses of the multiple RAMs and logical addresses of the logical storage space is determined;

[0093] S1002. Record each unoccupied continuous free storage space in the logical storage space as a free address line segment represented by a start point and an end point.

[0094] The starting point of the free address segment is the logical address of the starting position of the free storage space in the logical storage space, and the ending point of the free address segment is the logical address of the ending position of the free storage space in the logical storage space.

[0095] According to the occupancy of the storage module, determining the logical address for storing the target data to be stored by using the segment tree algorithm (S1011) includes:

[0096] S1011A1, searching the recorded free address segments, and determining the free address segments whose free storage space is greater than or equal to the size of the target data to be stored;

[0097] S1011A2, determining the free storage space corresponding to the determined free address line segment as the storage space for the target data to be stored, and determining the logical address of the target data to be stored according to the free address line segment;

[0098] S1011A3. Determining the real address of the target data to be stored according to the determined logical address includes:

[0099] S1011A4. According to the mapping relationship, the determined logical address is converted into a physical address of the RAM as a real address of the target data to be stored.

[0100] As one method of an embodiment of the present disclosure, each RAM can be regarded as a logical storage space as a whole. For example, when there are two RAMs (RAM0 and RAM1), the parity rows of the logical storage space can be the physical rows in the two RAMs respectively, and the adjacent parity rows constitute the logical rows, that is, each target data can be stored in at most two adjacent parity rows respectively.

[0101] Therefore, the free storage space in the logical storage space can be represented by the “free segments”, and the target data to be stored can be stored in the appropriate free segments through the segment tree algorithm.

[0102] In some embodiments, reference Figure 2 , according to the occupancy of the storage module, determining the logical address for storing the target data to be stored (S1011) includes:

[0103] S1011 B1. In response to failure to determine the logical address of the target data to be stored, perform space compression on the storage module.

[0104] S1011 B2. Determine a logical address for storing target data to be stored according to the occupancy of the storage module after space compression.

[0105] In some cases, the actual free storage space may be enough to store the target data, but because the stored target data is relatively scattered, it is impossible to find space in a logical row to store the target data (such as it is impossible to find a free line segment of sufficient length in a logical row). For this reason, space compression can be performed, that is, part of the target data (such as part of the target data separated by the free line segment) is moved together, so that the original multiple free storage spaces (such as free line segments) are "connected" to form a larger free storage space. Therefore, after the space backlog, a larger free storage space appears, so you can try to determine (such as using the segment tree algorithm) the logical address of the target data again.

[0106] It should be understood that since the embodiment of the present disclosure requires that one target data be stored in one logical row, in the above process of moving the target data, the target data can be moved within one logical row, or one target data can be moved to another logical row, but it is not allowed to move the target data to be scattered in multiple logical rows.

[0107] It should be understood that the specific methods of the above segment tree algorithm and space compression are various and will not be described in detail here.

[0108] Second, refer to Figures 1 to 7 , an embodiment of the present disclosure provides a data storage device, comprising:

[0109] A storage module including a plurality of RAMs, each RAM including a plurality of physical rows;

[0110] An address mapping unit is used to determine a real address according to a logical address of target data; each logical address represents a logical row and a position in the logical row, each logical row is composed of a plurality of physical rows from different RAMs, and the real address is a physical address of a storage space corresponding to the logical address in the RAM;

[0111] The splicing unit is used to splice different parts of the same target data read from different physical rows to obtain the target data.

[0112] Reference Figure 3 The data storage device includes a storage module composed of multiple RAMs, and is provided with an address mapping unit for converting a logical address into a real address. At the same time, a splicing unit is provided to splice different parts of a target data from different physical rows, so that the data storage device can implement the above data storage method.

[0113] In some embodiments, reference Figure 4 The data storage device of the embodiment of the present disclosure further includes:

[0114] A logical address storage unit, which is used to store the logical address of the target data;

[0115] and / or,

[0116] The logic address determination unit is used to determine the logic address for storing the target data to be stored according to the occupancy of the storage module.

[0117] Reference Figure 4 The data storage device may further include a logical address storage unit, in which the logical address of the target data may be stored, so that the address mapping unit may obtain the required logical address from the logical address storage unit and convert it. Figure 4 , the logical address storage unit can also be RAM.

[0118] Reference Figure 4 The data storage device may also include a logical address determination unit. When target data needs to be written into the storage module, the logical address determination unit may calculate its logical address according to the above method, for example, writing the logical address into the above logical address storage unit.

[0119] It should be understood that it is also feasible if the above logical address storage unit and logical address determination unit are implemented by hardware or software located outside the data storage device.

[0120] It should be understood that the data storage device of the embodiment of the present disclosure may also include other functional units.

[0121] For example, refer to Figure 4 When each target data is the data of all child nodes of a subtree of the prefix tree of the routing entry, the splicing unit can also be connected to a matching unit to perform the longest prefix match on the read target data (rule) to obtain the matching routing entry, that is, the data storage device can be equivalent to a device that implements the routing forwarding function.

[0122] In some embodiments, the number of RAMs is two.

[0123] Reference Figure 4 As one embodiment of the present disclosure, the storage module may specifically include two RAMs (RAM0 and RAM1).

[0124] Thirdly, refer to Figure 8 An embodiment of the present disclosure provides a computer-readable medium on which a computer program is stored. When the computer program is executed by a processor, any data storage method of the embodiment of the present disclosure is implemented.

[0125] Among them, the processor is a device with data processing capabilities, including but not limited to the central processing unit (CPU); the memory is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface (read-write interface) is connected between the processor and the memory, and can realize information exchange between the memory and the processor, including but not limited to the data bus (Bus), etc.

[0126] For example, the following uses reference Figure 4 The process of storing data in a storage module including two RAMs (RAM0 and RAM1) is described in detail.

[0127] Among them, each RAM includes N / 2 rows (physical rows), each row width is W (unit byte, the same below), so the size of the entire storage space is N (total depth) * W (width), and the addresses (real addresses) of the rows in RAM0 and RAM1 are numbered consecutively with even numbers (even) and odd numbers (odd) respectively.

[0128] Therefore, each logical row is composed of two adjacent rows (one even row and one odd row) in the entire storage space, so when writing, it is necessary to ensure that each target data (such as a subsequent child node) is located in at most two adjacent rows and cannot occupy three or more rows.

[0129] (1) Therefore, the address stored in each entry can be represented as a line segment [start_byte_index, end_byte_index], and the storage space is managed by a line segment tree. Initially, the line segment tree contains only one line segment [0, N*W-1]

[0130] (2) When a child node (target data) of a subtree is to be written, if the subtree includes Nr child nodes, the total bit width occupied by it is Rw=m*Nr.

[0131] Assuming that the total bit width of each child node (rule) of the routing entry prefix tree is k, each child node requires m=k+1 storage space, wherein the additional 1 indicates the prefix length through the set position.

[0132] (3) Search for free segments, select a segment whose length is closest to Rw and greater than or equal to Rw, subtract Rw from the segment and update the free segment, and record the segment start_byte_index as the abstract starting address Addrs (the starting address in the logical address).

[0133] If no suitable idle line segment can be found in step (3), the following space compression process is performed:

[0134] (3-11) First find the longest segment a among the current free segments, then find its nearest free segment b, and determine whether a+b has reached the space length required for this space compression. If not, continue to find the nearest free segment c, and determine whether a+b+c has reached the space length required for this space compression, and so on.

[0135] (3-12) Move the target data between multiple selected idle line segments as a whole. Assuming the starting position is a and the ending position is b, move the target data corresponding to position b-1 to position b, and the target data corresponding to position b-2 to position b-1, and so on, until the target data corresponding to position a+1 is moved away and merged with a to form a larger idle line segment, ending the idle address squeezing process and returning to step (3).

[0136] (4) Calculate the RAM addresses (i.e., the real addresses) of two pieces of secondary storage rules based on the abstract starting address in the following manner:

[0137] Addr2nd0 = ((Addrs % 2W) < W)? ROUNDDOWN(Addrs / 2W, 0) : (ROUNDDOWN(Addrs / 2W, 0) + 1);

[0138] Offset2nd0 = ((Addrs % 2W) < W)? (Addrs % W) : 0;

[0139] Addr2nd1 = (ROUNDDOWN(Addrs / 2W, 0)):

[0140] Offset2nd1 = ((Addrs % 2W) >= W)? (Addrs % W) : 0

[0141] Among them, "%" represents taking the remainder; "(Addrs % 2W) < W" determines whether the address is in RAM0, "ROUNDDOWN" represents rounding down, " ？ : <c>" means if A is true, return B, otherwise return C; Addr2ndx corresponds to the RAM row address, Offset2ndx corresponds to the RAM bit offset, where x is 0 or 1, indicating RAM0 or RAM1, respectively.

[0142] Therefore, refer to< / c> Figure 6 In the above method, the real address (i.e., the position of which row in which RAM) of the target data can be calculated according to its logical address (i.e., the address in the entire storage space).

[0143] (5) Based on Addr2nd0, Offset2nd0, Addr2nd1, and Offset2nd1, the data of each child node is written into RAM0 and RAM1, and Addrs is stored in the logical address determination unit.

[0144] (6) When the target data is to be deleted, write 0 to the corresponding position information of Addr2nd0 and Addr2nd1, and release the corresponding line segment to the free line segment.

[0145] (7) When the target data is to be read, the logical address of the subtree to be read is determined from the logical address storage unit according to the matching of the root node, and the RAM0 and RAM1 addresses (real addresses) are mapped in the following manner:

[0146] Addr2nd0 = ((Addrs%2W) <W)?ROUNDDOWN(Addrs / 2W,0):(ROUNDDOWN(Addrs / 2W,0)+1);

[0147] Addr2nd1=(ROUNDDOWN(Addrs / 2W,0));

[0148] Offset2nd=Addrs%W

[0149] That is, refer to Figure 7 , read out all the data of the rows involved in the target data.

[0150] (8) The entry concatenation unit receives the information transmitted by RAM0 and RAM1 and the abstract address information Addrs, recorded as Info0 and Info1, and obtains the concatenated target data in the following manner:

[0151] bitmap=(((Addrs%2W) <W)?[I nfo0][I nfo1]:[I nfo1][I nfo0])<<Offset2nd;

[0152] That is, refer to Figure 7 , splice the rows of RAM0 and RAM1 together to get the intercepted data, and then intercept the first W bits of data from the starting position start_ptr of the target data as the intercepted segment.

[0153] (9) The sub-node format of the matching unit is rule_num rule0_bitmap rule1_bitmap...., so based on the fixed field of each entry, first find the position where the last bit is 1, determine the prefix length as preffix_len = rule_len-bit_index, and match based on the prefix length to obtain the matching sub-node (rule).

[0154] For the above intercepted segments, the target data (sub-nodes) therein are further matched, for example, the part after the target data is invalidated.

[0155] Those skilled in the art will appreciate that all or some of the steps, systems, and functional modules / units in the apparatus disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0156] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation.

[0157] Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-temporary medium) and a communication medium (or temporary medium). As known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only compact disk (CD-ROM), digital versatile disk (DVD) or other optical disk storage; magnetic cassettes, magnetic tapes, disk storage or other magnetic storage; any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0158] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A method for storing data, wherein: The data is stored in a storage module including a plurality of random access memories RAM, each of the RAMs including a plurality of physical rows, and the method comprises: Determine a logical address for storing the target data to be stored according to the occupancy of the storage module; each of the logical addresses represents a logical row and a position in the logical row, and each of the logical rows is composed of a plurality of physical rows from different RAMs; Determine the real address of the target data to be stored according to the determined logical address; the real address is the physical address of the storage space corresponding to the logical address in the RAM; According to the determined real address, the target data to be stored is stored in the storage module.

2. The method according to claim 1, wherein: According to the determined real address, storing the target data to be stored in the storage module comprises: In response to the determined real address corresponding to the plurality of physical rows, the target data to be stored is stored sequentially and continuously in the plurality of physical rows.

3. The method according to claim 1, wherein: Also includes: Determine the real address where the target data to be read is stored according to the logical address of the target data to be read; Reading the target data to be read from the storage module according to the real address of the target data to be read; In response to different parts of the target data to be read being located in different physical rows, the different parts are spliced ​​to obtain the target data to be read.

4. The method according to claim 3, wherein: The step of reading the target data to be read from the storage module according to the real address of the target data to be read comprises: Reading all data of all the physical rows corresponding to the real address from the storage module; In response to different parts of the target data to be read being located in different physical rows, splicing the different parts to obtain the target data to be read includes: In response to different parts of the target data to be read being located in different physical rows, the data of the multiple physical rows read are sequentially spliced ​​to form data to be intercepted, and according to the real address of the target data to be read, an interception segment including the target data to be read is obtained from the data to be intercepted.

5. The method according to claim 4, wherein: The intercepted segment starts from the starting position of the target data to be read; The length of the truncated segment is equal to the width of the physical line.

6. The method according to claim 1, wherein: The determining, according to the occupancy of the storage module, a logical address for storing the target data to be stored comprises: According to the occupancy of the storage module, a segment tree algorithm is used to determine a logical address for storing the target data to be stored.

7. The method according to claim 1, wherein: The method further comprises: The plurality of RAMs are used as a logical storage space, and a mapping relationship between physical addresses of the plurality of RAMs and logical addresses of the logical storage space is determined; Recording each unoccupied continuous free storage space in the logical storage space as a free address line segment represented by a start point and an end point; the start point of the free address line segment is a logical address of a starting position of the free storage space in the logical storage space, and the end point of the free address line segment is a logical address of an ending position of the free storage space in the logical storage space; Determining the logical address for storing the target data to be stored according to the occupancy of the storage module includes: determining the logical address for storing the target data to be stored by using a segment tree algorithm according to the occupancy of the storage module; Determining the logical address for storing the target data to be stored by using a segment tree algorithm according to the occupancy of the storage module includes: Searching for the recorded free address segments, and determining the free address segments whose free storage space is greater than or equal to the size of the target data to be stored; Determine the free storage space corresponding to the determined free address line segment as the storage space for the target data to be stored, and determine the logical address of the target data to be stored according to the free address line segment; Determining the real address of the target data to be stored according to the determined logical address includes: According to the mapping relationship, the determined logical address is converted into a physical address of the RAM as a real address of the target data to be stored.

8. The method according to claim 1, wherein: The determining, according to the occupancy of the storage module, a logical address for storing the target data to be stored comprises: In response to failure to determine the logical address of the target data to be stored, performing space compression on the storage module; According to the occupancy of the storage module after space compression, a logical address for storing the target data to be stored is determined.

9. The method according to any one of claims 1 to 8, wherein: Each of the target data is data of all child nodes of a subtree of the prefix tree of the routing entry.

10. A data storage device, wherein: include: A storage module, comprising a plurality of RAMs, each of the RAMs comprising a plurality of physical rows; An address mapping unit, which is used to determine a real address according to a logical address of target data; Each of the logical addresses represents a logical row and a position in the logical row, each of the logical rows is composed of a plurality of physical rows from different RAMs, and the real address is a physical address of a storage space corresponding to the logical address in the RAM; The splicing unit is used to splice different parts of the same target data read from different physical rows to obtain the target data.

11. The device according to claim 10, wherein: Also includes: A logical address storage unit, which is used to store the logical address of the target data; and / or, A logical address determination unit is used to determine a logical address for storing target data to be stored according to the occupancy status of the storage module.

12. A computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the data storage method according to any one of claims 1 to 9.

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