Microcontroller power-on self-test method, storage medium and electronic equipment

Abstract

The invention provides a microcontroller power-on self-test method, a storage medium and electronic equipment. The microcontroller power-on self-test method comprises the steps that 1, a chip is powered on; step 2, executing a built-in self-test of the memory; 3, judging whether the built-in self-test of the memory is passed or not; 4, normally starting the chip; 5, judging whether the fault can be repaired or not; step 6, repairing the fault; and step 7, fault alarm. According to the microcontroller power-on self-test method, the storage medium and the electronic equipment, the built-in self-test of the memory is carried out after the chip is powered on, and if a fault is found in the test, the fault is repaired, so that the chip can still be immediately and normally started for use instead of waiting for the intervention of external force at present, and the reliability of the chip is improved. And the use convenience of the chip is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a microcontroller power-on self-test method, a storage medium and an electronic device. Background Art

[0002] A high-functional safety MCU (microcontroller, also called chip) needs to perform fault detection (also called self-test) after power-on. For example, MBIST (memory built-in self-test) is used to detect faults in the embedded RAM (random access memory). However, the shortcoming of this self-test method is that it has no ability to repair the detected faults. Therefore, even if the microcontroller detects a fault, it can only wait for external intervention, and cannot provide timely help for the current use needs of the chip. Summary of the invention

[0003] Based on the above-mentioned defects of the prior art, the present invention provides a microcontroller power-on self-test method, a storage medium and an electronic device, which can immediately repair the detected fault so that the chip can continue to be used immediately.

[0004] In order to achieve the above object, the present invention provides a microcontroller power-on self-test method, comprising: Step 1: Power on the chip; Step 2, executing a memory built-in self-test to test whether each memory cell of the memory is faulty, and issuing a test result. If no memory cell is faulty, the test result will indicate that the memory built-in self-test has passed, and if a memory cell is faulty, the test result will record the fault. Step 3, determining whether the memory built-in self-test passes, if passed, executing step 4, if not, executing step 5; Step 4: The chip starts normally; Step 5: Determine whether the fault can be repaired. If it can be repaired, go to step 6; if it cannot be repaired, go to step 7; Step 6: Repair the fault; Step seven, fault alarm.

[0005] In one implementation, step five includes determining whether the following two conditions are met simultaneously, if both conditions are met, it indicates that the fault can be repaired, otherwise it cannot be repaired: Condition 1: the test result indicates that the failed storage unit can be repaired; Condition 2: The repair information stored in the repair information unit storing the repair information indicates that the redundant unit used for repair has not been used for repair.

[0006] In one embodiment, step six includes updating the repair information stored in the repair information unit, wherein the updated repair information indicates an association relationship between the failed storage unit and the corresponding redundant unit for repairing the failure.

[0007] In one embodiment, the step six further includes: Step 8, re-execute the memory built-in self-test to test whether each memory unit of the memory is faulty, and issue a test result. If no memory unit is faulty, the test result will indicate that the memory built-in self-test has passed, and if a memory unit is faulty, the test result will record the fault. Step nine, determining whether the memory built-in self-test passes, if passed, executing step four, if not, executing step seven.

[0008] In one embodiment, after step 1 and before step 2, the method further includes: Step ten: read the repair information from the repair information unit.

[0009] In one embodiment, the step 2 further includes: performing a logic built-in self-test.

[0010] In one embodiment, after step 2 and before step 3, the method further includes: Step 11, determine whether the logic built-in self-test passes, if passed, execute step 3, if not, execute step 7.

[0011] In one implementation, the repair information unit uses a non-volatile memory.

[0012] The present invention also provides a storage medium on which a computer program is stored. When the computer program is read and executed by a processor, the microcontroller power-on self-test method as described above is executed.

[0013] The present invention also provides an electronic device, comprising: a processor, a memory and a communication bus, wherein the processor is connected to the memory via the communication bus for communication so as to execute the microcontroller power-on self-test method as described above.

[0014] The microcontroller power-on self-test method, storage medium and electronic device of the present invention perform a built-in self-test of the memory after the chip is powered on. If a fault is found in the test, the fault is repaired so that the chip can still be started normally and used immediately, instead of having to wait for external intervention as it does now, thereby improving the convenience of chip use. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are only for explanation purposes and are not intended to limit the scope of the present invention in any way. In addition, the shapes and proportional dimensions of the components in the drawings are only for illustration purposes and are used to help understand the present invention. They do not specifically limit the shapes and proportional dimensions of the components of the present invention. Under the guidance of the present invention, those skilled in the art can select various possible shapes and proportional dimensions to implement the present invention according to specific circumstances. In the drawings: Figure 1 A schematic flow chart of a microcontroller power-on self-test method provided in a first embodiment of the present invention. DETAILED DESCRIPTION

[0016] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0017] See also Figure 1 As shown, the first embodiment of the present invention provides a microcontroller power-on self-test method, comprising: Step 1: Power on the chip; Step 2, executing a memory built-in self-test to test whether each memory cell of the memory is faulty, and issuing a test result. If no memory cell is faulty, the test result will indicate that the memory built-in self-test has passed, and if a memory cell is faulty, the test result will record the fault. Step 3, determining whether the memory built-in self-test passes, if passed, executing step 4, if not, executing step 5; Step 4: The chip starts normally; Step 5: Determine whether the fault can be repaired. If it can be repaired, go to step 6; if it cannot be repaired, go to step 7; Step 6: Repair the fault; Step seven, fault alarm.

[0018] The microcontroller power-on self-test method of the present invention can repair the fault when a memory fault is detected, so that the chip can immediately continue to start normally for use. Among them, in the test result issued after the memory built-in self-test (MBIST) is completed, if no memory unit has a fault, the test result will directly give information indicating that the memory built-in self-test has passed. Correspondingly, if any memory unit has a fault, the test result will give information indicating that the memory built-in self-test has not passed, and the test result will record the fault.

[0019] Of course, before repairing after detecting a fault, it is necessary to first determine whether the fault can be repaired. To determine whether the fault can be repaired, in one embodiment, step five includes determining whether the following two conditions are met at the same time. If they are met at the same time, it indicates that the fault can be repaired, otherwise it cannot be repaired: Condition 1: the test result indicates that the failed storage unit can be repaired; Condition 2: The repair information stored in the repair information unit storing the repair information indicates that the redundant unit used for repair has not been used for repair.

[0020] Among them, regarding condition one, when recording the fault, the test result will also directly provide information indicating whether the failed storage unit can be repaired. Therefore, through the test result, it can be determined whether the failed storage unit can be repaired.

[0021] When it is determined that the failed storage unit can be repaired, a corresponding redundant unit is also required to repair it, so judgment condition 2 is required. Because with the development of high performance of MCU, the capacity demand for its embedded RAM is also increasing. For large-capacity RAM, redundant storage units (hereinafter referred to as redundant units) will be added to the RAM array to improve the chip yield. During the chip manufacturing process, the RAM will be tested by MBIST. When the RAM fails and can be repaired, the MBIST control module will generate repair information, which will be written to a non-volatile memory such as flash at one time. This non-volatile memory is the repair information unit described in this article. After the chip leaves the factory, each time the chip is powered on and used, the repair information will be read and the failed storage unit will be replaced with a redundant unit based on the repair information. For the relatively mature process at present, the probability of manufacturing failure is low. At the same time, for cost considerations, only one redundant unit is generally set for each RAM on a chip. However, only a few individual RAMs of chips will generally fail during the manufacturing process, so only a very small number of individual redundant units on the chips will be used. Therefore, for most chips, there are redundant units that are not used for repair, but are idle, so they can be used. Therefore, it is necessary to determine whether the repair information stored in the repair information unit storing the repair information indicates that the redundant unit used for repair has not been used for repair. If the redundant unit has been used for repair, there are no extra redundant units that can be used for repair, so the newly discovered fault can no longer be repaired at this time. If the redundant unit is not used for repair, the redundant unit can be used to repair the fault discovered at this time. Of course, under the teaching of the present invention, technicians in the field can also equip each RAM with multiple redundant unit settings (relaxing or releasing the cost limit) during hardware design. In this way, even if a fault has been found during the manufacturing process and some redundant units are used for repair, there can still be other redundant units used to repair the newly discovered fault during the use of the chip, and even different faults found in different use processes before and after can be repaired differently.

[0022] As for repairing the fault, in one embodiment, step six includes updating the repair information stored in the repair information unit, and the updated repair information indicates the association between the failed storage unit and the corresponding redundant unit for repairing the fault. Because, as mentioned above, the repair information unit stores the repair information for the fault found in the manufacturing process (of course, there may be no repair, and the actual content is empty); therefore, at this time, the repair information for the repair of the found fault is also updated in the repair information unit (not overwritten, but added). In this way, when the chip is used later (powered on), the corresponding failed storage unit is also replaced with a redundant unit through the repair information, and the memory in the entire microcontroller can still be considered as a complete component for use.

[0023] After the fault is repaired in step 6, step 4 can be executed and the chip starts normally. In one embodiment, the step 6 further includes: Step 8, re-execute the memory built-in self-test to test whether each memory unit of the memory is faulty, and issue a test result. If no memory unit is faulty, the test result will indicate that the memory built-in self-test has passed, and if a memory unit is faulty, the test result will record the fault. Step nine, determining whether the memory built-in self-test passes, if passed, executing step four, if not, executing step seven.

[0024] Because the redundant unit used to repair the fault may also have a fault itself, and the redundant unit was not tested in the previous test process, it is necessary to verify whether the repair is successful. Therefore, after the repair, the memory built-in self-test should be re-executed. If the retest passes, it means that the memory is no longer faulty and can be used safely, so it can be started normally at this time. If the retest still fails, it means that the fault still exists, and a fault alarm is issued.

[0025] Of course, in order to determine whether the fault needs to be repaired in step 5, in one embodiment, the process after step 1 and before step 2 further includes: Step ten: read the repair information from the repair information unit.

[0026] As mentioned above, in one embodiment, the repair information unit uses a non-volatile memory, so that the information stored therein can be read and used later. The repair information may be empty, which means that the memory has not been repaired, or it may have data. This data may be a repair performed during testing during the manufacturing process as mentioned above, or it may be a repair performed for a fault found during the previous power-on use. In this way, each time the power is turned on and used, it is tested and used based on the results of the previous repair. If a fault is detected again, as long as there are enough redundant units, the fault can be repaired, thereby ensuring the normal use of the memory (and the microcontroller).

[0027] In one embodiment, the step 2 further includes: executing a logic built-in self-test (LBIST). The logic built-in self-test is used to detect faults in digital logic in the microcontroller, thereby ensuring that key components of the entire microcontroller are free of faults.

[0028] Thus, accordingly, after step 2 and before step 3, the following steps are also included: Step 11, determine whether the logic built-in self-test passes, if passed, execute step 3, if not, execute step 7.

[0029] Of course, in other embodiments, the order of step 3 and step 11 can be interchanged. By the way, the numbers in the steps of the present invention are only used to number the steps respectively, and do not represent the order of execution. Under the guidance of the present invention, those skilled in the art can adjust the order of the steps according to actual needs.

[0030] A second embodiment of the present invention provides a storage medium having a computer program stored thereon. When the computer program is read and executed by a processor, the microcontroller power-on self-test method as described above is executed.

[0031] A third embodiment of the present invention provides an electronic device, comprising: a processor, a memory and a communication bus, wherein the processor is connected to the memory via the communication bus for communication, so as to execute the microcontroller power-on self-test method as described above.

[0032] The microcontroller power-on self-test method, storage medium and electronic device of the present invention perform a built-in self-test of the memory after the chip is powered on. If a fault is found in the test, the fault is repaired so that the chip can still be started normally and used immediately, instead of having to wait for external intervention as it does now, thereby improving the convenience of chip use.

[0033] It should be understood that the above description is for illustration and not for limitation. Many embodiments and many applications beyond the examples provided will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of the present teachings should not be determined with reference to the above description, but rather with reference to the foregoing claims and the full scope of equivalents to which such claims are entitled. For the purpose of comprehensiveness, all articles and references, including disclosures of patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended to be a waiver of such subject matter, nor should it be considered that the applicant has not considered such subject matter to be part of the disclosed application subject matter.

Claims

1. A microcontroller power-on self-test method, characterized in that: include: Step 1: Power on the chip; Step 2, executing a memory built-in self-test to test whether each memory cell of the memory is faulty, and issuing a test result. If no memory cell is faulty, the test result will indicate that the memory built-in self-test has passed, and if a memory cell is faulty, the test result will record the fault. Step 3, determining whether the memory built-in self-test passes, if passed, executing step 4, if not, executing step 5; Step 4: The chip starts normally; Step 5: Determine whether the fault can be repaired. If it can be repaired, go to step 6; if it cannot be repaired, go to step 7; Step 6: Repair the fault; Step seven, fault alarm.

2. The microcontroller power-on self-test method according to claim 1, characterized in that: The step 5 includes determining whether the following two conditions are met at the same time. If they are met at the same time, it indicates that the fault can be repaired; otherwise, it cannot be repaired: Condition 1: the test result indicates that the failed storage unit can be repaired; Condition 2: The repair information stored in the repair information unit storing the repair information indicates that the redundant unit used for repair has not been used for repair.

3. The microcontroller power-on self-test method as claimed in claim 2, characterized in that: The step six includes updating the repair information stored in the repair information unit, wherein the updated repair information indicates the association between the failed storage unit and the corresponding redundant unit for repairing the failure.

4. The microcontroller power-on self-test method as claimed in claim 3, characterized in that: The step six further includes: Step 8, re-execute the memory built-in self-test to test whether each memory unit of the memory is faulty, and issue a test result. If no memory unit is faulty, the test result will indicate that the memory built-in self-test has passed, and if a memory unit is faulty, the test result will record the fault. Step nine, determining whether the memory built-in self-test passes, if passed, executing step four, if not, executing step seven.

5. The microcontroller power-on self-test method according to claim 1, characterized in that: After step one and before step two, the following further comprises: Step ten: read the repair information from the repair information unit.

6. The microcontroller power-on self-test method as claimed in claim 5, characterized in that: The step 2 also includes: executing a logic built-in self-test.

7. The microcontroller power-on self-test method as claimed in claim 6, characterized in that: After step 2 and before step 3, the following steps are also included: Step 11, determine whether the logic built-in self-test passes, if passed, execute step 3, if not, execute step 7.

8. The microcontroller power-on self-test method as claimed in claim 2, characterized in that: The repair information unit adopts a non-volatile memory.

9. A storage medium, characterized in that: A computer program is stored thereon, and when the computer program is read and executed by a processor, the microcontroller power-on self-test method as claimed in any one of claims 1 to 8 is executed.

10. An electronic device, characterized in that: include: A processor, a memory and a communication bus, wherein the processor is connected to the memory via the communication bus to communicate with each other so as to execute the microcontroller power-on self-test method as claimed in any one of claims 1 to 8.

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