Information sending device

Abstract

The embodiment of the invention provides an information sending device, and belongs to the technical field of communication. The device comprises a host, a first slave, a second slave, a diode D1, a digital transistor Q1, a triode Q2 and a triode Q3, an input end of the diode D1 is connected with an instruction input port of a host, an output end of the diode D1 is connected with a slave selection port of the host and a first input end of the digital transistor Q1, and a second input end of the digital transistor Q1 is connected with an instruction output port of the host, a base electrode of the triode Q2 and a base electrode of the triode Q3. The output end of the digital transistor Q1 is connected with the input end of the first slave and is grounded, the collector electrode of the triode Q2 is connected with the bus port of the first slave, and the emitter electrode of the triode Q2 is connected with the input end of the second slave and is grounded. According to the method provided by the invention, the problem that the data processing duration is increased due to the fact that each slave needs to verify the request sent by the host is solved.

Description

Technical Field

[0001] The present invention belongs to the field of communication technology, and in particular relates to an information sending device. Background Art

[0002] With the continuous development of communication technology, the public's demand for computing speed is gradually increasing. In addition to the computing speed of the processing unit itself, the communication in the device is also an important factor affecting the computing speed.

[0003] In the prior art, in a system, when a host and a slave communicate, the host needs to send a request to each slave, and each slave verifies the request before communication between the host and the slave can be performed.

[0004] However, the inventors have discovered that the prior art has at least the following technical problems: each slave needs to verify the received request, which increases the data processing time. Summary of the invention

[0005] The present application provides an information sending device to solve the problem of increasing data processing time due to the need for each slave to verify the received request.

[0006] In a first aspect, the present application provides an information sending device, comprising: a host, a first slave, a second slave, a diode D1, a digital transistor Q1, a triode Q2 and a triode Q3; the input end of the diode D1 is connected to the command input port of the host, the output end of the diode D1 is connected to the slave selection port of the host and the first input end of the digital transistor Q1, the second input end of the digital transistor Q1 is connected to the command output port of the host, the base of the triode Q2 and the base of the triode Q3, the output end of the digital transistor Q1 is connected to the command output port of the host, the base of the triode Q2 and the base of the triode Q3, and the output end of the digital transistor Q1 is connected to the command output port of the host, the base of the triode Q2 and the base of the triode Q3. The output end is connected to the input end of the first slave and is grounded, the collector of the transistor Q2 is connected to the bus port of the first slave, and the emitter of the transistor Q2 is connected to the input end of the second slave and is grounded; the host is used to input a voltage corresponding to the first slave or the second slave to the slave selection port, and input information to be sent to the instruction input port to control the voltage of the second input end of the digital transistor Q1, so that the transistor Q2 or the transistor Q3 is turned on, so that the information to be sent is sent to the first slave or the second slave via the transistor Q2 or the transistor Q3.

[0007] In a possible implementation, the digital transistor Q1 includes: a resistor R1, a resistor R2 and a transistor Q11; one end of the resistor R1 serves as the base of the digital transistor Q1, and the other end is connected to the base of the transistor Q11 and one end of the resistor R2; the other end of the resistor R2 is connected to the emitter of the transistor Q11 and grounded, and the collector of the transistor Q11 serves as the second input end of the digital transistor Q1.

[0008] In a possible implementation, the information sending device also includes: a resistor R3, a resistor R4 and a resistor R5; one end of the resistor R3 is connected to the instruction input port and one end of the resistor R5, the other end of the resistor R3 is connected to the input end of the diode D1 and one end of the resistor R4, the other end of the resistor R4 is connected to the base of the transistor Q2, and the other end of the resistor R5 is connected to the first input end of the digital transistor Q1.

[0009] In a possible implementation, the information sending device also includes: a resistor R6 and a resistor R7; one end of the resistor R6 is connected to the instruction input port, and the other end of the resistor R6 is connected to the emitter of the transistor Q2; one end of the resistor R7 is connected to the instruction input port, and the other end of the resistor R7 is connected to the emitter of the transistor Q3.

[0010] In a possible implementation, the information sending device further includes: a digital transistor Q4, a transistor Q5, a transistor Q6, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12 and a resistor R13; one end of the resistor R9 is connected to the signal output end of the first slave, one end of the resistor R8 and the emitter of the transistor Q5, the other end of the resistor R9 is connected to the bus port of the first slave and the collector of the transistor Q2, the other end of the resistor R8 is connected to one end of the resistor R10 and the base of the transistor Q5, the other end of the resistor R10 is connected to the bus port of the first slave and the collector of the transistor Q2, the collector of the transistor Q5 is connected to the first end of the digital transistor Q4 and the collector of the transistor Q6. The host is connected to the signal output terminal of the second slave, one end of the resistor R12 is connected to the signal output terminal of the second slave, one end of the resistor R11 and the emitter of the transistor Q6, the other end of the resistor R12 is connected to the bus port of the second slave and the collector of the transistor Q3, the other end of the resistor R11 is connected to one end of the resistor R13 and the base of the transistor Q6, the other end of the resistor R13 is connected to the bus port of the second slave and the collector of the transistor Q3, the collector of the transistor Q6 is connected to the first end of the digital transistor Q4 and the collector of the transistor Q5, the second end of the digital transistor Q4 is grounded, and the third end is connected to the power supply and the signal receiving port of the host; the host is also used to use the signal receiving port to receive signals sent by the first slave and / or the second slave.

[0011] In a possible implementation, the information sending device also includes: a resistor R14 and a resistor R15; one end of the resistor R14 is connected to the bus port of the first slave machine and the other end of the resistor R9, the other end of the resistor R14 is connected to the other end of the resistor R10 and the collector of the transistor Q2, one end of the resistor R15 is connected to the bus port of the second slave machine and the other end of the resistor R12, and the other end of the resistor R15 is connected to the other end of the resistor R13 and the collector of the transistor Q3.

[0012] In a possible implementation, the information sending device also includes: a capacitor C1 and a capacitor C2; one end of the capacitor C1 is connected to one end of the resistor R8, the collector of the transistor Q5, one end of the resistor R9 and the signal output end of the first slave, the other end of the capacitor C1 is connected to the base of the transistor Q5, one end of the resistor R8 and one end of the resistor R10, one end of the capacitor C2 is connected to one end of the resistor R11, the collector of the transistor Q6, one end of the resistor R12 and the signal output end of the first slave, and the other end of the capacitor C2 is connected to the base of the transistor Q6, one end of the resistor R11 and one end of the resistor R13.

[0013] In a possible implementation, the digital transistor Q4 includes: a resistor R16, a resistor R17 and a transistor Q41; one end of the resistor R16 is connected to the collector of the transistor Q5, and the other end is connected to one end of the resistor R17 and the base of the transistor Q41, the other end of the resistor R17 is connected to the emitter of the transistor Q41 and grounded, and the collector of the transistor Q41 is connected to the power supply and the signal receiving port of the host.

[0014] In a possible implementation, the information sending device further includes a resistor R18; one end of the resistor R18 is connected to the third end of the digital transistor Q4 and the signal receiving port of the host, and the other end is connected to the power supply.

[0015] In a possible implementation, the information sending device also includes: a first circuit protection module D2 and a second circuit protection module D3; one end of the circuit protection module D2 is connected to the bus port of the first slave and the collector of the transistor Q2, the second end of the circuit protection module D2 is connected to the emitter of the transistor Q2 and the input end of the first slave and is grounded, the third end of the circuit protection module D2 is connected to the power supply, one end of the circuit protection module D3 is connected to the bus port of the second slave and the collector of the transistor Q3, the second end of the circuit protection module D3 is connected to the emitter of the transistor Q3 and the input end of the second slave and is grounded, and the third end of the circuit protection module D3 is connected to the power supply.

[0016] The present application provides an information sending device, which controls the voltage of the digital transistor Q1 through the host to realize the conduction control of the transistor Q2 and the transistor Q3, so that the signal of the input instruction output port is sent to the first slave or the second slave through the transistor Q2 or the transistor Q3, thereby sending the signal to the slave in a direction, preventing other irrelevant slaves from receiving the signal, reducing the amount of calculation of other slaves, and increasing the calculation speed of other slaves. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 A schematic diagram of the inventive concept provided for an embodiment of the present application;

[0019] Figure 2 A schematic diagram of the structure of the information sending device provided in the embodiment of the present application Figure 1 ;

[0020] Figure 3 A schematic diagram of the structure of a digital transistor Q1 provided in an embodiment of the present application;

[0021] Figure 4 A schematic diagram of the structure of the information sending device provided in the embodiment of the present application Figure 2 ;

[0022] Figure 5 A schematic diagram of the structure of the information sending device provided in the embodiment of the present application Figure 3 ;

[0023] Figure 6 A schematic diagram of the structure of the information sending device provided in the embodiment of the present application Figure 4 ;

[0024] Figure 7 A schematic diagram of the structure of a digital transistor Q4 provided in an embodiment of the present application;

[0025] Figure 8 A schematic diagram of the structure of the information sending device provided in the embodiment of the present application Figure 5 . DETAILED DESCRIPTION

[0026] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0027] With the continuous development of computing and communication technologies, people have put forward higher requirements on the speed of data processing. In addition to the improvement of the computing unit itself, the communication between units also has an important impact on the computing speed.

[0028] When information is currently processed between processing units, the host and slave are distinguished. When the host sends information to the slave, it uses broadcasting. The host adds the identifier of the slave that needs to receive the information to the information. After receiving the information, each slave checks whether the identifier in the information is the same as its own identifier. If they are the same, it responds to achieve communication between the host and the slave. If they are not the same, the information is ignored. Sending information to the specified slave is achieved.

[0029] However, this method will cause slaves that do not need to receive information to receive redundant information, increasing the data processing time of these slaves and consuming redundant energy.

[0030] In response to the above technical problems, the inventors proposed the following technical concept for the situation of one host and two slaves: adding a slave selection unit between the host and the two slaves, the host's processing unit inputs information to the slave selection unit, and the slave selection unit sends the information to the corresponding slaves.

[0031] Figure 1 This is a schematic diagram of the invention concept provided in the embodiment of this application. Figure 1 As shown, the processing unit of the host is connected to the slave selection circuit, and the slave selection circuit sends information to the corresponding slave.

[0032] The host may include a processing unit, which may contain a communication protocol, and the slave may be the same or different electronic components containing the communication protocol. The host knows the different identities and functions of the slaves, and the slaves do not need to know their own identities and functions. For example, if the host is going to communicate with slave 1, the host needs to send an instruction to the slave selection circuit to select slave 1. The slave selection unit will directly transmit the instruction to slave 1. After receiving the instruction, slave 1 performs relevant operations and gives feedback. Other slaves do not participate in the above process.

[0033] The slave selection unit may include: a diode D1, a digital transistor Q1, a triode Q2 and a triode Q3. The host controls the base voltage of the digital transistor Q1, thereby controlling the voltage of the triode Q2 and the triode Q3, so that the triode Q2 or the triode Q3 is turned on, and at the same time, the information to be sent is input to the triode Q2 and the triode Q3, thereby controlling the information to be sent to the corresponding slave via the triode Q2 or the triode Q3.

[0034] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0035] Figure 2 A schematic diagram of the structure of the information sending device provided in the embodiment of the present application Figure 1 .like Figure 2 As shown, the information sending device includes: a host, a first slave, a second slave, a diode D1, a digital transistor Q1, a triode Q2 and a triode Q3.

[0036] The input end of the diode D1 is connected to the command input port of the host, the output end of the diode D1 is connected to the slave selection port of the host and the first input end of the digital transistor Q1, the second input end of the digital transistor Q1 is connected to the command output port of the host, the base of the transistor Q2 and the base of the transistor Q3, the output end of the digital transistor Q1 is connected to the input end of the first slave and is grounded, the collector of the transistor Q2 is connected to the bus port of the first slave, and the emitter of the transistor Q2 is connected to the input end of the second slave and is grounded;

[0037] The host is used to input the voltage corresponding to the first slave or the second slave to the slave selection port, and input the information to be sent to the instruction input port to control the voltage of the second input terminal of Q1, so that the transistor Q2 or the transistor Q3 is turned on, so that the information to be sent is sent to the first slave or the second slave via the transistor Q2 or the transistor Q3.

[0038] The host can search for the correspondence between the slave identifier and the voltage to obtain the voltage corresponding to the first slave or the second slave. Inputting the information to be sent to the command input port can be inputting different voltages to the command input port to input the information to be sent. The correspondence between the slave identifier and the voltage can be calibrated by the staff, and its storage format can be a table, a key-value pair, etc.

[0039] For example, if the current host wants to communicate with the first slave, the voltage corresponding to the first slave is input to the digital transistor Q1. If the voltage corresponding to the first slave is 0, no voltage is input to the digital transistor Q1. If the voltage corresponding to the first slave is 1, a voltage with a preset value is input to the digital transistor Q1, where the preset value is a high-level voltage pre-calibrated by the staff or preset by the host. In the specific implementation process, it can also be: if the first slave corresponds to a low level, the second slave corresponds to a high level; if the first slave corresponds to a high level, the second slave corresponds to a low level. The embodiment of the present application does not specifically limit the voltage values ​​of the high level voltage and the low level.

[0040] The transistor Q2 and the transistor Q3 mentioned above can be NPN transistors.

[0041] From the description of the above embodiments, it can be seen that the embodiment of the present application controls the voltage of the digital transistor Q1 through the host to realize the conduction control of the transistor Q2 and the transistor Q3, so that the signal of the input instruction output port is sent to the first slave or the second slave through the transistor Q2 or the transistor Q3, thereby sending the signal to the slave in a direction, preventing other irrelevant slaves from receiving the signal, reducing the amount of calculation of other slaves, and increasing the calculation speed of other slaves.

[0042] Figure 3 A schematic diagram of the structure of the digital transistor Q1 provided in an embodiment of the present application. like Figure 3As shown, the digital transistor Q1 includes:

[0043] Resistor R1, resistor R2 and transistor Q11.

[0044] One end of the resistor R1 serves as the base of the digital transistor Q1, and the other end is connected to the base of the transistor Q11 and one end of the resistor R2. The other end of the resistor R2 is connected to the emitter of the transistor Q11 and grounded. The collector of the transistor Q11 serves as the second input end of the digital transistor Q1.

[0045] Specifically, the collector of Q11 can also be connected to the base of transistor Q2. When the host inputs a high level from the slave selection port, the digital transistor Q1 is turned on, the base voltage of transistor Q3 is pulled down and cannot be turned on, and the second slave cannot receive the signal sent by the instruction input port. On the contrary, when the host inputs a low level from the slave selection port, the digital transistor Q1 is not turned on, and the base voltage of transistor Q2 is pulled down through diode D1, so that transistor Q2 cannot be turned on, and the first slave cannot receive the signal sent by the instruction input port.

[0046] It can be seen from the description of the above embodiments that the embodiments of the present application can increase the stability of the transistor Q11 by adding a resistor between the base of the transistor Q11 and the base and emitter of the transistor Q11, thereby improving the stability of the entire circuit.

[0047] Figure 4 A schematic diagram of the structure of the information sending device provided in the embodiment of the present application Figure 2 .like Figure 4 As shown, the information sending device further includes: a resistor R3, a resistor R4 and a resistor R5;

[0048] One end of resistor R3 is connected to the instruction input port and one end of resistor R5, the other end of resistor R3 is connected to the input end of diode D1 and one end of resistor R4, the other end of resistor R4 is connected to the base of transistor Q2, and the other end of resistor R5 is connected to the first input end of digital transistor Q1.

[0049] From the description of the above embodiments, it can be seen that the embodiment of the present application can adjust the voltage reduction amplitude from the instruction input port to the two transistors by setting a resistor between the instruction input port and the transistors Q2 and Q3, thereby increasing the stability of data transmission.

[0050] Continue to refer Figure 4 .like Figure 4 As shown, the signal sending device further includes: a resistor R6 and a resistor R7;

[0051] One end of the resistor R6 is connected to the instruction input port, and the other end of the resistor R6 is connected to the emitter of the transistor Q2. One end of the resistor R7 is connected to the instruction input port, and the other end of the resistor R7 is connected to the emitter of the transistor Q3.

[0052] It can be seen from the description of the above embodiments that the embodiments of the present application increase the operating stability of the transistors Q2 and Q3 by setting a resistor between the base and the emitter of the transistors Q2 and Q3.

[0053] Figure 5 A schematic diagram of the structure of the information sending device provided in the embodiment of the present application Figure 3 .like Figure 5 As shown, the information sending device further includes: a digital transistor Q4, a triode Q5, a triode Q6, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12 and a resistor R13;

[0054] One end of the resistor R9 is connected to the signal output end of the first slave, one end of the resistor R8 and the emitter of the transistor Q5, the other end of the resistor R9 is connected to the bus port of the first slave and the collector of the transistor Q2, the other end of the resistor R8 is connected to one end of the resistor R10 and the base of the transistor Q5, the other end of the resistor R10 is connected to the bus port of the first slave and the collector of the transistor Q2, the collector of the transistor Q5 is connected to the first end of the digital transistor Q4 and the collector of the transistor Q6, and one end of the resistor R12 is connected to the signal output end of the second slave. The first end of the digital transistor Q4 is connected to the first end of the digital transistor Q5, the second end of the digital transistor Q4 is connected to the ground, and the third end of the digital transistor Q4 is connected to the power supply and the signal receiving port of the host;

[0055] The host is further configured to receive signals sent by the first slave and / or the second slave using a signal receiving port.

[0056] like Figure 5 As shown in the figure, the slave has three ports. From top to bottom, the first port is the signal output port of the slave, the second port is the bus port, and the third port is the signal receiving port of the slave. The signal output port and bus port of the slave can send signals to the host, and the bus port and signal receiving port of the slave can receive signals sent by the host. Therefore, the bus port can both input and output signals. The power supply voltage connected to the signal output port of the slave can be 11V, 12V, 13V, etc.

[0057] From the description of the above embodiments, it can be seen that the embodiments of the present application form a data transmission channel from the slave to the host by adding digital transistor Q4, transistor Q5, transistor Q6, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12 and resistor R13 in the circuit, thereby realizing the function of sending information from the slave to the host.

[0058] Figure 6 A schematic diagram of the structure of the information sending device provided in the embodiment of the present application Figure 4 .like Figure 6 As shown, the information sending device further includes: a resistor R14 and a resistor R15;

[0059] One end of resistor R14 is connected to the bus port of the first slave and the other end of resistor R9, the other end of resistor R14 is connected to the other end of resistor R10 and the collector of transistor Q2, one end of resistor R15 is connected to the bus port of the second slave and the other end of resistor R12, and the other end of resistor R15 is connected to the other end of resistor R13 and the collector of transistor Q3.

[0060] By adding resistors R14 and R15, the voltage difference between the bus port and the signal output port of the slave can be adjusted.

[0061] Continue to refer Figure 6 .like Figure 6 The information sending device shown also includes: a capacitor C1 and a capacitor C2;

[0062] One end of the capacitor C1 is connected to one end of the resistor R8, the collector of the transistor Q5, one end of the resistor R9 and the signal output end of the first slave machine, the other end of the capacitor C1 is connected to the base of the transistor Q5, one end of the resistor R8 and one end of the resistor R10, one end of the capacitor C2 is connected to one end of the resistor R11, the collector of the transistor Q6, one end of the resistor R12 and the signal output end of the first slave machine, and the other end of the capacitor C2 is connected to the base of the transistor Q6, one end of the resistor R11 and one end of the resistor R13.

[0063] Connecting a capacitor between the base and emitter of a transistor can increase the stability of the transistor's operation and reduce the impact of current such as static electricity.

[0064] Figure 7 This is a schematic diagram of the structure of the digital transistor Q4 provided in the embodiment of the present application. Figure 7 As shown, the digital transistor Q4 includes: a resistor R16, a resistor R17 and a transistor Q41;

[0065] One end of resistor R16 is connected to the collector of transistor Q5, and the other end is connected to one end of resistor R17 and the base of transistor Q41. The other end of resistor R17 is connected to the emitter of transistor Q41 and grounded. The collector of transistor Q41 is connected to the power supply and the signal receiving port of the host.

[0066] The voltage of the power supply can be 5V, 6V, 7V, etc.

[0067] The effect of the resistor in the digital transistor Q4 is similar to that of the resistor in the digital transistor Q1, both of which increase the stability of the triode in the digital transistor and reduce the influence of static electricity on the operation of the triode.

[0068] Figure 8 A schematic diagram of the structure of the information sending device provided in the embodiment of the present application Figure 5 .like Figure 8 As shown, the information sending device further includes a resistor R18;

[0069] One end of the resistor R18 is connected to the third end of the digital transistor Q4 and the signal receiving port of the host, and the other end of the resistor R18 is connected to the power supply.

[0070] It can be seen from the description of the above embodiment that the embodiment of the present application forms a voltage drop between the power supply and the digital transistor Q4 by adding a resistor R18 between the digital transistor Q4 and the power supply, thereby facilitating signal transmission.

[0071] Continue to refer Figure 8 .like Figure 8 As shown, in the information sending device, it also includes: a first circuit protection module D2 and a second circuit protection module D3;

[0072] One end of the circuit protection module D2 is connected to the bus port of the first slave and the collector of the transistor Q2, the second end of the circuit protection module D2 is connected to the emitter of the transistor Q2 and the input end of the first slave and is grounded, the third end of the circuit protection module D2 is connected to the power supply, one end of the circuit protection module D3 is connected to the bus port of the second slave and the collector of the transistor Q3, the second end of the circuit protection module D3 is connected to the emitter of the transistor Q3 and the input end of the second slave and is grounded, and the third end of the circuit protection module D3 is connected to the power supply.

[0073] The first protection circuit module D2 and the second protection circuit module D3 are both composed of two diodes. Taking the first protection circuit module D2 as an example, the input end of the first diode in the first protection circuit module D2 is connected to the emitter of the transistor Q2 and one end of the resistor R6, and the output end is connected to the base of the transistor Q2, one end of the resistor R10, one end of the resistor R14 and the input end of the second diode in the first protection circuit, and the output end of the second diode in the first protection circuit is connected to the power supply. The second protection circuit is similar, and will not be described here. The power supply voltage connected here can be 11V, 12V, 13V, etc.

[0074] It can be seen from the description of the above embodiments that the embodiments of the present application increase the stability of the information sending device and reduce the impact of static electricity or signal disturbance on information transmission by adding a protection circuit module in the information sending device.

[0075] In a possible implementation, the diode D1 may be a Schottky diode, and its model may be "BAT54WS", the model of the digital transistor Q1 may be "DTC143XCA", the model of the transistor Q2 and the transistor Q3 may be "2SC2412K", the model of the resistors R3, R4, R6, R7, R8, R9, R11, and R12 may be "2K-J-6023", the model of the resistors R5 and R18 may be "4K7-J-0603", and the model of the resistors R6, R7, R8, R9, R11, and R12 may be "2K-J-6023". The model of resistors R10 and R13 can be "10K-J-0603", the model of resistors R14 and R15 can be "22R-J-1206", the model of capacitors C1 and C2 can be "102K-50V-X7R", the model of transistors Q5 and Q6 can be "2SA1037AK", the model of the first circuit protection module D2 and the second circuit protection module D3 can be "BAV99", and the model of the digital transistor Q4 can be "DTC114ECA".

[0076] The models of the above-mentioned diodes, transistors, and resistors may also be other models, and replacing the above-mentioned models with other models should also be within the protection scope of this application.

[0077] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

[0078] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes the common knowledge in the art or the precise structure shown by the conventional techniques not disclosed in the present application, and various modifications and changes can be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. An information sending device, It is characterized in that include: A host, a first slave, a second slave, a diode D1, a digital transistor Q1, a triode Q2 and a triode Q3; The input end of the diode D1 is connected to the command input port of the host, the output end of the diode D1 is connected to the slave selection port of the host and the first input end of the digital transistor Q1, the second input end of the digital transistor Q1 is connected to the command output port of the host, the base of the transistor Q2 and the base of the transistor Q3, the output end of the digital transistor Q1 is connected to the input end of the first slave and is grounded, the collector of the transistor Q2 is connected to the bus port of the first slave, and the emitter of the transistor Q2 is connected to the input end of the second slave and is grounded; The host is used to input a voltage corresponding to the first slave or the second slave to the slave selection port, and input information to be sent to the instruction input port, so as to control the voltage of the second input terminal of the digital transistor Q1, so that the transistor Q2 or the transistor Q3 is turned on, so that the information to be sent is sent to the first slave or the second slave via the transistor Q2 or the transistor Q3.

2. The device according to claim 1, It is characterized in that The digital transistor Q1 includes: a resistor R1, a resistor R2 and a transistor Q11; One end of the resistor R1 serves as the base of the digital transistor Q1, and the other end is connected to the base of the transistor Q11 and one end of the resistor R2. The other end of the resistor R2 is connected to the emitter of the transistor Q11 and grounded. The collector of the transistor Q11 serves as the second input end of the digital transistor Q1.

3. The device according to claim 1, It is characterized in that Also includes: Resistor R3, resistor R4 and resistor R5; One end of the resistor R3 is connected to the instruction input port and one end of the resistor R5, the other end of the resistor R3 is connected to the input end of the diode D1 and one end of the resistor R4, the other end of the resistor R4 is connected to the base of the transistor Q2, and the other end of the resistor R5 is connected to the first input end of the digital transistor Q1.

4. The device according to claim 1, It is characterized in that Also includes: a resistor R6 and a resistor R7; One end of the resistor R6 is connected to the instruction input port, and the other end of the resistor R6 is connected to the emitter of the transistor Q2. One end of the resistor R7 is connected to the instruction input port, and the other end of the resistor R7 is connected to the emitter of the transistor Q3.

5. The device according to any one of claims 1 to 4, It is characterized in that Also includes: Digital transistor Q4, transistor Q5, transistor Q6, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12 and resistor R13; One end of the resistor R9 is connected to the signal output end of the first slave, one end of the resistor R8 and the emitter of the transistor Q5, the other end of the resistor R9 is connected to the bus port of the first slave and the collector of the transistor Q2, the other end of the resistor R8 is connected to one end of the resistor R10 and the base of the transistor Q5, the other end of the resistor R10 is connected to the bus port of the first slave and the collector of the transistor Q2, the collector of the transistor Q5 is connected to the first end of the digital transistor Q4 and the collector of the transistor Q6, one end of the resistor R12 is connected to the signal output end of the second slave The output end, one end of the resistor R11 and the emitter of the transistor Q6 are connected, the other end of the resistor R12 is connected to the bus port of the second slave and the collector of the transistor Q3, the other end of the resistor R11 is connected to one end of the resistor R13 and the base of the transistor Q6, the other end of the resistor R13 is connected to the bus port of the second slave and the collector of the transistor Q3, the collector of the transistor Q6 is connected to the first end of the digital transistor Q4 and the collector of the transistor Q5, the second end of the digital transistor Q4 is grounded, and the third end is connected to the power supply and the signal receiving port of the host; The host is further configured to use the signal receiving port to receive signals sent by the first slave and / or the second slave.

6. The device according to claim 5, It is characterized in that Also includes: Resistor R14 and resistor R15; One end of the resistor R14 is connected to the bus port of the first slave machine and the other end of the resistor R9, the other end of the resistor R14 is connected to the other end of the resistor R10 and the collector of the transistor Q2, one end of the resistor R15 is connected to the bus port of the second slave machine and the other end of the resistor R12, and the other end of the resistor R15 is connected to the other end of the resistor R13 and the collector of the transistor Q3.

7. The device according to claim 5, It is characterized in that Also includes: Capacitor C1 and capacitor C2; One end of the capacitor C1 is connected to one end of the resistor R8, the collector of the transistor Q5, one end of the resistor R9 and the signal output end of the first slave machine, the other end of the capacitor C1 is connected to the base of the transistor Q5, one end of the resistor R8 and one end of the resistor R10, one end of the capacitor C2 is connected to one end of the resistor R11, the collector of the transistor Q6, one end of the resistor R12 and the signal output end of the first slave machine, and the other end of the capacitor C2 is connected to the base of the transistor Q6, one end of the resistor R11 and one end of the resistor R13.

8. The device according to claim 5, It is characterized in that The digital transistor Q4 includes: a resistor R16, a resistor R17 and a transistor Q41; One end of the resistor R16 is connected to the collector of the transistor Q5, and the other end is connected to one end of the resistor R17 and the base of the transistor Q41. The other end of the resistor R17 is connected to the emitter of the transistor Q41 and grounded. The collector of the transistor Q41 is connected to the power supply and the signal receiving port of the host.

9. The device according to claim 5, It is characterized in that Also includes: Resistor R18; One end of the resistor R18 is connected to the third end of the digital transistor Q4 and the signal receiving port of the host, and the other end is connected to the power supply.

10. The device according to any one of claims 1 to 4, It is characterized in that Also includes: A first circuit protection module D2 and a second circuit protection module D3; One end of the circuit protection module D2 is connected to the bus port of the first slave machine and the collector of the transistor Q2, the second end of the circuit protection module D2 is connected to the emitter of the transistor Q2 and the input end of the first slave machine and is grounded, the third end of the circuit protection module D2 is connected to a power supply, one end of the circuit protection module D3 is connected to the bus port of the second slave machine and the collector of the transistor Q3, the second end of the circuit protection module D3 is connected to the emitter of the transistor Q3 and the input end of the second slave machine and is grounded, and the third end of the circuit protection module D3 is connected to a power supply.

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