Processor area evaluation method, system and equipment

Abstract

The invention provides a processor area evaluation method, system and equipment, and relates to the field of processor evaluation. The method comprises the following steps: extracting all configuration item information of a processor; selecting a configuration item influencing the area of the processor, and analyzing a function relationship between the configuration item influencing the area of the processor and the area of each functional module; based on a configured sample table, determining a processor area evaluation formula based on configuration items according to the function relationship; determining a processor area evaluation formula based on the dominant frequency according to the function relation on the basis of a sample table defined by the dominant frequency; and evaluating processor areas under different configurations and different dominant frequencies according to the processor area evaluation formula based on the configuration items and the processor area evaluation formula based on the dominant frequencies. According to the invention, the processor area can be rapidly evaluated.

Description

Technical Field

[0001] The present invention relates to the field of processor evaluation, and in particular to a method, system and device for evaluating processor area. Background Art

[0002] The processor area assessment solution relies on the processor fconfig information, and divides the processor into multiple configuration items according to its functions and possible application requirements of customers. Different combinations of configuration items can reach tens of millions of levels, and different processors are suitable for different application requirements. In the past, processor area assessments were done by using tools to generate area reports after the processor design was completed. This process usually took dozens of hours, which greatly delayed the formulation of the processor assessment solution. Summary of the invention

[0003] The purpose of the present invention is to provide a method, system and device for evaluating processor area, so as to solve the problem that processor area evaluation takes a long time.

[0004] To achieve the above object, the present invention provides the following solutions:

[0005] A processor area estimation method, comprising:

[0006] Extract all configuration item information of the processor;

[0007] Selecting configuration items that affect the processor area, and analyzing the functional relationship between the configuration items that affect the processor area and the area of ​​each functional module; the functional modules include an instruction fetch unit, a memory access unit, a decoding execution unit, a pipeline control and internal timer unit and other units; the other units include a direct memory access unit, an interrupt controller, a debug tracking unit and a memory protection unit;

[0008] Based on the sample table of configurations, determining a processor area evaluation formula based on the configuration items according to the functional relationship;

[0009] Based on the sample table defined by the main frequency, determining a processor area evaluation formula based on the main frequency according to the functional relationship;

[0010] The processor areas under different configurations and different main frequencies are evaluated according to the processor area evaluation formula based on the configuration items and the processor area evaluation formula based on the main frequency.

[0011] Optionally, based on the configured sample table, determining the configuration item-based processor area evaluation formula of each of the functional modules according to the functional relationship specifically includes:

[0012] Based on the configured sample table, configuring processors of multiple different configuration items according to the functional relationship;

[0013] According to the processors of different configuration items configured, sample data reports under different configuration items are comprehensively generated by digital circuits to extract the required first area data; the first area data includes the total area of ​​the entire processor under the corresponding configuration and the area of ​​each functional module;

[0014] A processor area evaluation formula based on configuration items of each of the functional modules is generated according to the first area data; the processor area evaluation formula based on configuration items is a processor area evaluation formula that combines piecewise function, linear fitting and switch function.

[0015] Optionally, based on the sample table defined by the main frequency, a processor area evaluation formula based on the main frequency is determined according to the functional relationship, specifically including:

[0016] Based on the sample table of main frequency definition, multiple processors with different main frequency powers are configured according to the functional relationship;

[0017] According to the configured processors with different main frequencies and powers, a comprehensive data report under different frequencies is comprehensively generated by a digital circuit to extract the required second area data; the second area data includes the total area of ​​the entire processor under the corresponding configuration;

[0018] A linear fitting function is generated according to the second area data to determine a processor area evaluation formula based on the main frequency; the independent variable of the linear fitting function is the main frequency of the processor, and the dependent variable is the comprehensive area difference.

[0019] Optionally, the processor area evaluation formula based on the configuration item is:

[0020] f1=lsu_size+ifu_size+udl_size+misc_size+others_size

[0021] Among them, f1 is the processor area based on the configuration item; ifu_size is the instruction fetch unit area; lsu_size is the storage access unit area; udl_size is the decoding execution unit area; misc_size is the pipeline control and internal timer unit area; others_size is the area of ​​other units.

[0022] Optionally, the processor area evaluation formula based on main frequency is:

[0023] f2=coef_frequency_a0×core_frequency+coef_frequency_a1

[0024]

[0025]

[0026] Among them, f2 is the processor area based on the main frequency; coef_frequency_a0 and coef_frequency_a1 are the coefficients of linear fitting for sample data; core_frequency is the main frequency of the processor.

[0027] Optionally, evaluating the processor area under different configurations and different main frequency frequencies according to the processor area evaluation formula based on the configuration item and the processor area evaluation formula based on the main frequency specifically includes:

[0028] The formula fest=f1×f2 is used to evaluate the processor area under different configurations and different main frequency; where fest is the processor area under different configurations and different main frequency; f1 is the processor area based on the configuration item; and f2 is the processor area based on the main frequency.

[0029] A processor area estimation system, comprising:

[0030] Configuration item information extraction module, used to extract all configuration item information of the processor;

[0031] A function relationship analysis module, used for selecting configuration items that affect the processor area, and analyzing the function relationship between the configuration items that affect the processor area and the area of ​​each functional module; the functional modules include an instruction fetch unit, a storage access unit, a decoding execution unit, a pipeline control and internal timer unit and other units; the other units include a direct memory access unit, an interrupt controller, a debug tracking unit and a memory protection unit;

[0032] A processor area evaluation formula determination module based on configuration items, used for determining a processor area evaluation formula based on configuration items according to the functional relationship based on the configured sample table;

[0033] A processor area evaluation formula determination module based on main frequency, used to determine the processor area evaluation formula based on main frequency according to the functional relationship based on the sample table defined by the main frequency;

[0034] The processor area evaluation module under different configurations and different main frequency is used to evaluate the processor area under different configurations and different main frequency according to the processor area evaluation formula based on the configuration item and the processor area evaluation formula based on the main frequency.

[0035] Optionally, a processor area evaluation formula determination module based on a configuration item specifically includes:

[0036] A configuration unit, configured to configure processors of a plurality of different configuration items according to the functional relationship based on the configuration sample table;

[0037] A first area data extraction unit is used to generate sample data reports under different configuration items through digital circuits according to the processors of different configuration items configured, and extract the required first area data; the first area data includes the total area of ​​the entire processor under the corresponding configuration and the area of ​​each functional module;

[0038] A processor area assessment formula determination unit based on configuration items is used to generate a processor area assessment formula based on configuration items for each of the functional modules according to the first area data; the processor area assessment formula based on configuration items is a processor area assessment formula that combines piecewise function, linear fitting and switch function.

[0039] An electronic device includes a memory and a processor, wherein the memory is used to store a computer program, and the processor runs the computer program to enable the electronic device to execute the processor area evaluation method.

[0040] A computer-readable storage medium stores a computer program, wherein the computer program implements the processor area evaluation method when executed by a processor.

[0041] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects: the present invention provides a processor area evaluation method, system and device, which analyzes the functional relationship between the configuration items that affect the processor area and the area of ​​each functional module based on all configuration item information of the processor, and determines the processor area evaluation formula based on the configuration items and the processor area evaluation formula based on the main frequency based on the configuration sample table and the sample table defined based on the main frequency. According to the above two formulas, the processor area under different configurations and different main frequencies can be quickly evaluated to obtain the processor area evaluation result, so as to quickly determine the processor PPA (performance / power consumption / area) data under the corresponding configuration.

[0042] In addition, since the processor area synthesized by the present invention has a relatively definite linear relationship with the area after the final chip tape-out, and the chip area also has a relatively definite relationship with power consumption and performance, the present invention allows users to quickly determine the PPA data of the processor under different configurations, thereby providing a scientific basis for customers to make quick decisions. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0044] Figure 1 A flow chart of a processor area estimation method provided by the present invention;

[0045] Figure 2 A schematic diagram of the syn_data directory provided by the present invention;

[0046] Figure 3 A schematic diagram of the syn_rpts directory provided by the present invention;

[0047] Figure 4 This is a schematic diagram of the first area data provided by the present invention;

[0048] Figure 5 A schematic diagram of the first part of the LSU area provided by the present invention;

[0049] Figure 6 It is a schematic diagram of the second part of the LSU area provided by the present invention;

[0050] Figure 7 A schematic diagram of the third part of the LSU area provided by the present invention;

[0051] Figure 8 This is a schematic diagram of the first area data provided by the present invention. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] The purpose of the present invention is to provide a processor area evaluation method, system and device, which can quickly evaluate the processor area.

[0054] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0055] Embodiment 1

[0056] like Figure 1As shown, the present invention provides a processor area evaluation method, comprising:

[0057] Step 101: Extract all configuration item information of the processor.

[0058] In actual applications, all configuration item information of the processor is extracted based on FARMTOOLS (a special processor generation tool invented by Xinyihui) fconfig. The configuration item information is listed in detail as follows:

[0059] max_inst_size (maximum instruction width): 32 / 64 bits; dpif_width (data bus width): 64 / 128 / 256 / 512 / 1024 bits; ipif_width (instruction bus width): 0 / 64 bits, 0 means disable instruction bus function; dp_width (data path width): 32 / 64 / 128 / 256 / 512 / 1024 bits; load0 (read unit 0): value range 1 / 2, 1: can only read internal memory, 2: read external or internal memory; store0 (write unit 0): value range 1 / 2, 1: can only write to internal memory, 2: write to external or internal memory; load1 (read unit 1): value range 0 / 1 / 2, 0: disable, 1: can only read internal memory, 2: load1 reads external or internal memory; store_buff_depth (write cache depth): 2 / 4 / 8 dp_width data; bus_buff_depth (bus cache depth): 2 / 4 / 8 dp_width data; dtcm_size (data tightly coupled memory size): 0 or 4 to 512 (power of 2) KB, 0 means disable dtcm; dtcm_width (bit width of data tightly coupled memory): 32 / 64 / 128 / 256 / 512 / 1024 bits; dtcm_region (region where data tightly coupled memory is located): 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 / 8 / 9 / 10 / 11 / 12 / 13 / 14 / 15; dtcm_offset (starting address of data tightly coupled memory): multiple of dtcm_size; dcache_size (data cache size): 0 / 16 / 32 / 64 / 128 / 256KB, 0 means disable data cache function; itcm_size (instruction tightly coupled memory size): 0 or 4 to 512 (power of 2) KB, 0 means disable itcm; itcm_width (bit width of instruction tightly coupled memory): 32 / 64 bits; itcm_region (region where instruction tightly coupled memory is located): 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 / 8 / 9 / 10 / 11 / 12 / 13 / 14 / 15; itcm_offset (starting address of instruction tightly coupled memory): multiple of itcm_size; icache_size (instruction cache size): 0 / 16 / 32 / 64 / 128 / 256KB, 0 means disable data cache function; pic_cycle (number of execution cycles of programmable interrupt controller): 1 / 2cycles;pic_region (region where the PLC is located): 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 / 8 / 9 / 10 / 11 / 12 / 13 / 14 / 15; pic_offset (starting address of the PLC): multiple of 256KB; pic_count (number of PLC interrupts): 1 to 255 interrupt sources; num_timer (number of internal counters): 0 / 2, 0: no internal counter, 2: contains 2 internal counters; mpu (memory inclusion unit): 0 / 1, 0: no mpu, 1: with mpu; bp (instruction branch prediction): 0 / 1, 0: no bp, 1: with bp; debug (processor debug trace unit): 0 / 1, 0: no debug, 1: with debug; Trace (processor trace unit): 0 / 1, 0: no trace, 1: with trace; pmu (performance monitoring unit): 0 / 1, 0: no pmu, 1: with pmu; mpc (multi-processor communication support function): 0 / 1, 0: no mpc, 1: with mpc; slave_port (external access processor slave interface unit): 0 / 1, 0: no slave_port, 1: with slave_port; clock_g ating (clock gating function): 0 / 1, 0: do not support clock switch, 1: support clock switch; vendor_id (vendor ID information): custom vendor ID information; crv32i (RISC-V32biti integer instruction set): non-optional, crv32i value is fixed to 1; crv32m (RISC-V32bit multiplication instruction extension): 0 / 1, 0: do not support multiplication instructions, 1: support multiplication instructions; crv32a (RISC-V32bit atomic instruction extension): 0 / 1, 0: do not support atomic instructions, 1: support atomic instructions; crv32b (RISC-V32b it displacement instruction extension): 0 / 1, 0: do not support shift instructions, 1: support shift instructions; crv32c (RISC-V 32bit compression instruction extension): 0 / 1, 0: do not support compression instructions, 1: support compression instructions; crv32f (RISC-V 32bit single-precision floating-point instruction extension): 0 / 1, 0: do not support floating-point instructions, 1: support floating-point instructions; crv32zicsr (RISC-V 32bit CSR instruction extension): non-optional, crv32zicsr value fixed bit 1; core_frequency (processor main frequency): 0~1000MHz optional. ;

[0060] Step 102: Select configuration items that affect the processor area, and analyze the functional relationship between the configuration items that affect the processor area and the area of ​​each functional module; the functional modules include an instruction fetch unit, a storage access unit, a decoding execution unit, a pipeline control and internal timer unit and other units; the other units include a direct memory access unit, an interrupt controller, a debug tracking unit and a memory protection unit.

[0061] In actual applications, all configuration items that affect the processor area are selected based on the hardware design of the Xinyihui processor, and the functional relationship between these configuration items and the area of ​​each functional module is analyzed in detail according to the design. By viewing and analyzing the design, we can obtain which configuration items exist in the processor design, that is, the configuration items that cause changes in the processor design logic are the configuration items to be selected.

[0062] The modular configurable design of the processor can be configured for the following functional modules, namely: IFU (instruction fetch unit), LSU (memory access unit), UDL (decoding execution unit), MISC (pipeline control and internal timer units), OTHERs (including DMA, interrupt controller, DEBUG debugging, TRACE tracking unit, memory protection unit).

[0063] Select the configuration items that affect the area of ​​the functional module LSU:

[0064] The six configuration items dp_width, load1, store_buff_depth, bus_buff_depth, dtcm_size, and dcache_size affect the area of ​​the functional module LSU.

[0065] In order to further decompose the coupling relationship between configuration items, dp_width is used as a piecewise function factor, that is, the LSU area is evaluated in 6 cases according to different dp_width configurations (corresponding to dp_width = 32 / 64 / 128 / 256 / 512 / 1024 respectively); store_buff_depth and dtcm_size have a strong coupling relationship in the design, so these two parameters are introduced as linear fitting factor items; bus_buff_depth and dcache have a strong coupling relationship in the design, so these two parameters are introduced as linear fitting factor items; load1 is introduced as a switch function factor in the design.

[0066] Select the configuration items that affect the area of ​​the functional module IFU:

[0067] The four configuration items ipif_width, itcm_size, icache_size, and bp affect the area of ​​the functional module IFU.

[0068] Among them, itcm_size and icache_size have multiple options in the design, so these two configuration items can be used as linear fitting function factors separately; ipif_width and bp are used as switch function factors.

[0069] Select the configuration items that affect the area of ​​the UDL:

[0070] The five configuration items crv32m, crv32a, crv32b, crv32c, and crv32f act as switch function factors to affect the UDL area.

[0071] Select the configuration items that affect the MISC area of ​​the functional module:

[0072] The four configuration items num_timer, trace, pmu, and mpc act as switch function factors to affect the MISC area of ​​the functional module.

[0073] Select the configuration items that affect the area of ​​the functional module OTHERs:

[0074] The five configuration items, pic_count, mpu, debug, slave_port, and dp_width, are used in the evaluation scheme to affect the area of ​​the functional modules OTHERs.

[0075] There are 255 options for pic_count (interrupt sources can be configured from 1 to 255), so pic_count is used as a factor for linear fitting; slave_port and dp_width have a strong couple relationship in the design, so these two parameters are introduced as linear fitting factors; mpu and debug are used as switch function factors.

[0076] Step 103: Based on the configured sample table, determine a processor area evaluation formula based on the configuration item according to the functional relationship.

[0077] In actual applications, the step 103 specifically includes: based on the configured sample table, configuring a plurality of processors with different configuration items according to the functional relationship; based on the configured processors with different configuration items, generating sample data reports under different configuration items through digital circuit synthesis, and extracting the required first area data; the first area data includes the total area of ​​the entire processor and the area of ​​each functional module under the corresponding configuration; generating a processor area evaluation formula based on the configuration item for each functional module according to the first area data; the processor area evaluation formula based on the configuration item is a processor area evaluation formula that combines piecewise function, linear fitting and switching function.

[0078] In actual applications, a sample table based on configuration is defined to configure multiple processors.

[0079] To define a configuration-based sample table, all you need to do is define new processor samples based on each configuration item.

[0080] The following rules are followed in terms of method: 1. Processor area = IFU area + LSU area + UDL area + MISC area + OTHERs area; 2. The module area evaluation method is base area + area increment introduced when the associated configuration items in the module are turned on; 3. The module base area is the area of ​​the module when no associated configuration items in the module are turned on, and the area increment introduced by the associated configuration items in the module is calculated by the difference method, that is, the area difference between the two processors after the switch configuration items are turned on is the area increment brought by the configuration items; 4. In order to minimize the introduced error, when calculating the area of ​​a certain module, other module configuration items are uniformly processed according to the default values; 5. The area increment introduced by the configuration items generates a linear fitting function and a switch function based on the actual characteristics of the specific design analysis; 6. When encountering three configuration items couple during the linear fitting process, the three configuration items couple will be decomposed and processed in a combination of piecewise function and linear fitting, that is, one of the configuration items is used as an option of the piecewise function, and the other two configuration items with a couple relationship are linearly fitted. This method is used to decompose three configuration items with a couple relationship into two configuration items with a couple relationship, thereby improving the accuracy of the evaluation formula.

[0081] A sample data report is generated by digital circuit synthesis based on the sample table 1 based on the configuration (139 processors are configured).

[0082] The digital circuit synthesis process is parallelized and automated through scripting.

[0083] Digital circuit synthesis is an important step in the process of digital circuit implementation. After the synthesis is completed, the tool will generate the following data:

[0084] 1)synthesis.log: records the execution process of the synthesis tool to facilitate tracking and debugging of the synthesis process.

[0085] 2)syn_data directory: The synthesis tool converts the design format to generate data files in gtechfile, postnetlist, postddc, svf and other formats, such as Figure 2 shown.

[0086] 3)syn_rpts directory: The synthesis tool generates various data reports after analyzing the design. The data reports include area reports, timing reports, power consumption reports, resource usage reports, etc. Figure 3 shown.

[0087] Collect the generated sample data report, that is, extract the required first area data from the comprehensive report area.rpt. The extraction method is to use a python script to extract the required area data from the processor comprehensive directory. The area data includes the total area of ​​the entire processor under the corresponding configuration and the area of ​​each functional module, as shown in the following figure. Figure 4 shown.

[0088] The first area data is analyzed to obtain a processor area evaluation formula f1 that combines a piecewise function, a linear fit, and a switch function.

[0089] The LSU area is as follows Figure 5-Figure 7 The procedure shown is calculated.

[0090] The IFU area was calculated using the following formula:

[0091] ifu_size=coef_ifu_base+itcm_size0+icache_size0+bp_size+ipif_wid th_size

[0092] Among them, coef_* is the fitted constant.

[0093] itcm_size0=coef_ifu_a0×itcm_size+coef_ifu_a1

[0094] icache_size0=coef_ifu_a2×icache_size+coef_ifu_a3

[0095]

[0096]

[0097] coef_ifu_base=491.526

[0098] coef_ifu_a0=-0.11124048389544972

[0099] coef_ifu_a1=12985.583711724681

[0100] coef_ifu_a2=108.18312705443506

[0101] coef_ifu_a3=13841.88728171881

[0102] coef_ifu_a4=117.5579999999728

[0103] coef_ifu_a5=12074.95779999995

[0104] The UDL area is calculated using the following formula:

[0105] udl_size=coef_isa_base+coef_isa_a0×crv32m+coef_isa_a1×crv32a+coef_isa_a2×crv32c+coef_isa_a3×crv32b+coef_isa_a4×crv32f

[0106] coef_isa_base=9807

[0107] coef_isa_a0=4722

[0108] coef_isa_a1=3493

[0109] coef_isa_a2=3572

[0110] coef_isa_a3=4135

[0111] coef_isa_a4=19194

[0112] The MISC area is calculated using the following formula:

[0113] misc_size=coef_misc_base+coef_misc_a0×num_timer / 2+coef_misc_a1×trace+coef_misc_a2×pmu+coef_misc_a3×mpc

[0114] coef_misc_base=9248

[0115] coef_misc_a0=903

[0116] coef_misc_a1=1576

[0117] coef_misc_a2=2881

[0118] coef_misc_a3=1216

[0119] The OTHERs area is calculated using the following formula:

[0120] others_size=coef_other_a0×pic_count+coef_other_a1+coef_other_a2×debug+coef_other_a3×mpu+(coef_other_a4×dp_width+coef_other_a5)×slave_port

[0121] coef_other_a0=98.85112821884762

[0122] coef_other_a1 = -239.87169

[0123] coef_other_a2=5145

[0124] coef_other_a3=7384

[0125] coef_other_a4=33.92852

[0126] coef_other_a5=1633

[0127] The processor area based on configuration items f1 = LSU area + IFU area + UDL area + MISC area + OTHERs area.

[0128] That is, the processor area evaluation formula based on configuration items is:

[0129] f1=lsu_size+ifu_size+udl_size+misc_size+others_size

[0130] Among them, f1 is the processor area based on the configuration item; ifu_size is the instruction fetch unit area; lsu_size is the storage access unit area; udl_size is the decoding execution unit area; misc_size is the pipeline control and internal timer unit area; others_size is the area of ​​other units.

[0131] In practical applications, the area assessment formula f1 based on the configuration item is compared with the actual comprehensive report (the report is the report after the sample data is integrated) to further analyze and validate the accuracy of the area assessment method and process.

[0132] Step 104: Based on the sample table of main frequency definitions, determine a processor area evaluation formula based on the main frequency according to the functional relationship.

[0133] In actual applications, step 104 specifically includes: configuring a plurality of processors with different main frequency powers based on a sample table defined based on the main frequency according to the functional relationship; generating a comprehensive data report at different frequencies through a digital circuit based on the configured processors with different main frequency powers, and extracting the required second area data; the second area data includes the total area of ​​the entire processor under the corresponding configuration; generating a linear fitting function based on the second area data, and determining a processor area evaluation formula based on the main frequency; the independent variable of the linear fitting function is the main frequency of the processor, and the dependent variable is the comprehensive area difference.

[0134] In actual applications, the sample table based on the definition of main frequency follows the following two rules: 1. In order to make each functional module sensitive to the main frequency as much as possible, a processor with all configuration items turned on is selected; 2. Based on the selected processor, different main frequencies are configured, and the main frequency configuration range is from 100MHz to 1000MHz. That is, processors with the same configuration are integrated with 100MHz, 200MHz, 300MHz, 400MHz, 500MHz, 600MHz, 700MHz, 800MHz, 900MHz, and 1000MHz main frequencies respectively.

[0135] Collect the comprehensive data reports generated at different frequencies, that is, extract the required second area data from the comprehensive report area.rpt.

[0136] The extraction method is to use a python script to extract the required second area data from the processor comprehensive directory. The second area data is the total area of ​​the entire processor under the corresponding configuration, such as Figure 8 shown.

[0137] Based on the collected second area data, a linear fitting function is generated, the independent variable of the function is the main frequency of the processor, and the dependent variable is the integrated area difference.

[0138] The fitting method is: take the area synthesized at 800MHz as the base, and make the difference between the area synthesized at other main frequency and the 800MHz base, that is, to obtain the area increment introduced under different main frequency.

[0139] The processor area evaluation formula f2 based on the main frequency is obtained as follows:

[0140] f2=coef_frequency_a0×core_frequency+coef_frequency_a1

[0141]

[0142]

[0143]

[0144] Among them, f2 is the processor area based on the main frequency; coef_frequency_a0 and coef_frequency_a1 are the coefficients of linear fitting for sample data; core_frequency is the main frequency of the processor.

[0145] By comparing the processor area evaluation formula f2 based on the main frequency with the comprehensive data reports at different frequencies, the accuracy of the area evaluation method and process is further analyzed and validated.

[0146] Step 105: Evaluate the processor areas under different configurations and different main frequency frequencies according to the processor area evaluation formula based on the configuration item and the processor area evaluation formula based on the main frequency.

[0147] In practical applications, step 105 specifically includes: using the formula fest=f1×f2 to evaluate the processor area under different configurations and different main frequency; wherein fest is the processor area under different configurations and different main frequency; f1 is the processor area based on the configuration item; and f2 is the processor area based on the main frequency.

[0148] The present invention finally generates a processor area evaluation formula, which can quickly generate processor areas under different configurations and different main frequencies. By obtaining this processor area evaluation result, the processor PPA (performance / power consumption / area) data under the corresponding configuration can be quickly determined, because the comprehensive area has a relatively certain linear relationship with the area after the final chip is taped out, and the chip area and power consumption and performance also have a relatively certain relationship. Therefore, through this solution, users can quickly determine the PPA data of processors under different configurations, thereby providing a scientific basis for customers to make decisions quickly.

[0149] Embodiment 2

[0150] In order to execute the method corresponding to the above-mentioned embodiment 1 to achieve corresponding functions and technical effects, a processor area evaluation system is provided below.

[0151] A processor area estimation system, comprising:

[0152] The configuration item information extraction module is used to extract all configuration item information of the processor.

[0153] A function relationship analysis module is used to select configuration items that affect the processor area and analyze the functional relationship between the configuration items that affect the processor area and the area of ​​each functional module; the functional modules include an instruction fetch unit, a storage access unit, a decoding execution unit, a pipeline control and internal timer unit and other units; the other units include a direct memory access unit, an interrupt controller, a debug tracking unit and a memory protection unit.

[0154] A processor area evaluation formula determination module based on configuration items is used to determine a processor area evaluation formula based on configuration items according to the functional relationship based on the configured sample table.

[0155] The processor area evaluation formula determination module based on main frequency is used to determine the processor area evaluation formula based on main frequency according to the functional relationship based on the sample table defined by the main frequency.

[0156] The processor area evaluation module under different configurations and different main frequency is used to evaluate the processor area under different configurations and different main frequency according to the processor area evaluation formula based on the configuration item and the processor area evaluation formula based on the main frequency.

[0157] In actual applications, a processor area assessment formula determination module based on configuration items specifically includes: a configuration unit, which is used to configure a plurality of processors of different configuration items according to the functional relationship based on a configured sample table; a first area data extraction unit, which is used to generate sample data reports under different configuration items through digital circuits according to the configured processors of different configuration items, and extract the required first area data; the first area data includes the total area of ​​the entire processor and the area of ​​each functional module under the corresponding configuration; a processor area assessment formula determination unit based on configuration items, which is used to generate a processor area assessment formula based on configuration items for each of the functional modules according to the first area data; the processor area assessment formula based on configuration items is a processor area assessment formula that combines piecewise function, linear fitting and switch function.

[0158] Embodiment 3

[0159] An embodiment of the present invention provides an electronic device including a memory and a processor. The memory is used to store a computer program, and the processor runs the computer program to enable the electronic device to execute the processor area evaluation method provided in the first embodiment.

[0160] In practical applications, the above electronic device may be a server.

[0161] In practical applications, an electronic device includes: at least one processor, a memory, a bus and a communications interface.

[0162] Wherein: the processor, the communication interface, and the memory communicate with each other via a communication bus.

[0163] Communication interface, used to communicate with other devices.

[0164] The processor is used to execute the program, and specifically can execute the method described in the above embodiment.

[0165] Specifically, the program may include program codes including computer operation instructions.

[0166] The processor may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention. The one or more processors included in the electronic device may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs.

[0167] The memory is used to store programs. The memory may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0168] Based on the description of the above embodiments, the embodiments of the present application provide a storage medium on which computer program instructions are stored. The computer program instructions can be executed by a processor to implement the method described in any embodiment.

[0169] The processor area evaluation system provided in the embodiment of the present application exists in various forms, including but not limited to:

[0170] (1) Mobile communication devices: These devices are characterized by having mobile communication functions and providing voice and data communications as their main purpose. These terminals include: smart phones (such as iPhone), multimedia phones, functional phones, and low-end phones.

[0171] (2) Ultra-mobile personal computer devices: These devices fall into the category of personal computers, have computing and processing capabilities, and generally also have mobile Internet access capabilities. These terminals include: PDA, MID and UMPC devices, such as iPad.

[0172] (3) Portable entertainment devices: These devices can display and play multimedia content. They include audio and video players (such as iPods), handheld game consoles, e-books, smart toys, and portable car navigation devices.

[0173] (4) Other electronic devices with data interaction functions.

[0174] Thus far, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve the desired results. Additionally, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing may be advantageous.

[0175] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0176] For the convenience of description, the above device is described by being divided into various units according to their functions and described separately. Of course, when implementing the present application, the functions of each unit can be implemented in the same one or more software and / or hardware. It should be understood by those skilled in the art that the embodiments of the present application can be provided as methods, systems or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0177] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0178] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0179] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0180] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0181] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0182] Computer-readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM),

[0183] Digital Versatile Disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, disk storage or other magnetic storage devices

[0184] Or any other non-transmission medium that can be used to store information that can be accessed by a computing device. According to the definition in this article, computer-readable media does not include temporary computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0185] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0186] The present application may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific transactions or implement specific abstract data types. The present application may also be practiced in distributed computing environments where transactions are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0187] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0188] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A processor area estimation method, It is characterized in that include: Extract all configuration item information of the processor; Selecting configuration items that affect the processor area, and analyzing the functional relationship between the configuration items that affect the processor area and the area of ​​each functional module; the functional modules include an instruction fetch unit, a memory access unit, a decoding execution unit, a pipeline control and internal timer unit and other units; the other units include a direct memory access unit, an interrupt controller, a debug tracking unit and a memory protection unit; Based on the sample table of configurations, determining a processor area evaluation formula based on the configuration items according to the functional relationship; Based on the sample table defined by the main frequency, determining a processor area evaluation formula based on the main frequency according to the functional relationship; The processor areas under different configurations and different main frequencies are evaluated according to the processor area evaluation formula based on the configuration items and the processor area evaluation formula based on the main frequency.

2. The processor area estimation method according to claim 1, It is characterized in that Based on the configured sample table, the processor area evaluation formula based on the configuration item of each functional module is determined according to the functional relationship, specifically including: Based on the configured sample table, configuring processors of multiple different configuration items according to the functional relationship; According to the processors of different configuration items configured, sample data reports under different configuration items are comprehensively generated by digital circuits to extract the required first area data; the first area data includes the total area of ​​the entire processor under the corresponding configuration and the area of ​​each functional module; A processor area evaluation formula based on configuration items of each of the functional modules is generated according to the first area data; the processor area evaluation formula based on configuration items is a processor area evaluation formula that combines piecewise function, linear fitting and switch function.

3. The processor area estimation method according to claim 1, It is characterized in that Based on the sample table defined by the main frequency, a processor area evaluation formula based on the main frequency is determined according to the functional relationship, specifically including: Based on the sample table of main frequency definition, multiple processors with different main frequency powers are configured according to the functional relationship; According to the processors with different main frequencies and powers configured, a comprehensive data report under different frequencies is comprehensively generated by a digital circuit to extract the required second area data; the second area data includes the total area of ​​the entire processor under the corresponding configuration; A linear fitting function is generated according to the second area data to determine a processor area evaluation formula based on the main frequency; the independent variable of the linear fitting function is the main frequency of the processor, and the dependent variable is the comprehensive area difference.

4. The processor area estimation method according to claim 1, It is characterized in that The processor area evaluation formula based on configuration items is: f1=lsu_size+ifu_size+udl_size+misc_size+others_size Among them, f1 is the processor area based on the configuration item; ifu_size is the instruction fetch unit area; lsu_size is the storage access unit area; udl_size is the decoding execution unit area; misc_size is the pipeline control and internal timer unit area; others_size is the area of ​​other units.

5. The processor area estimation method according to claim 1, It is characterized in that The processor area evaluation formula based on main frequency is: f2=coef_frequency_a0×core_frequency+coef_frequency_a1 Among them, f2 is the processor area based on the main frequency; coef_frequency_a0 and coef_frequency_a1 are the coefficients of linear fitting for sample data; core_frequency is the main frequency of the processor.

6. The processor area estimation method according to claim 1, It is characterized in that Evaluating the processor area under different configurations and different main frequency frequencies according to the processor area evaluation formula based on the configuration item and the processor area evaluation formula based on the main frequency specifically includes: The formula fest=f1×f2 is used to evaluate the processor area under different configurations and different main frequency; where fest is the processor area under different configurations and different main frequency; f1 is the processor area based on the configuration item; and f2 is the processor area based on the main frequency.

7. A processor area estimation system, It is characterized in that include: Configuration item information extraction module, used to extract all configuration item information of the processor; A function relationship analysis module, used for selecting configuration items that affect the processor area, and analyzing the function relationship between the configuration items that affect the processor area and the area of ​​each functional module; the functional modules include an instruction fetch unit, a storage access unit, a decoding execution unit, a pipeline control and internal timer unit and other units; the other units include a direct memory access unit, an interrupt controller, a debug tracking unit and a memory protection unit; A processor area evaluation formula determination module based on configuration items, used for determining a processor area evaluation formula based on configuration items according to the functional relationship based on the configured sample table; A processor area evaluation formula determination module based on main frequency, used to determine the processor area evaluation formula based on main frequency according to the functional relationship based on the sample table defined by the main frequency; The processor area evaluation module under different configurations and different main frequency is used to evaluate the processor area under different configurations and different main frequency according to the processor area evaluation formula based on the configuration item and the processor area evaluation formula based on the main frequency.

8. The processor area estimation system according to claim 7, It is characterized in that A processor area evaluation formula determination module based on configuration items specifically includes: A configuration unit, configured to configure processors of a plurality of different configuration items according to the functional relationship based on the configuration sample table; A first area data extraction unit is used to generate sample data reports under different configuration items through digital circuits according to the processors of different configuration items configured, and extract the required first area data; the first area data includes the total area of ​​the entire processor under the corresponding configuration and the area of ​​each functional module; A processor area assessment formula determination unit based on configuration items is used to generate a processor area assessment formula based on configuration items for each of the functional modules according to the first area data; the processor area assessment formula based on configuration items is a processor area assessment formula that combines piecewise function, linear fitting and switch function.

9. An electronic device, It is characterized in that The electronic device comprises a memory and a processor, wherein the memory is used to store a computer program, and the processor runs the computer program to enable the electronic device to execute the processor area evaluation method according to any one of claims 1 to 6.

10. A computer-readable storage medium, It is characterized in that The device stores a computer program, which, when executed by a processor, implements the processor area evaluation method according to any one of claims 1 to 6.

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