Two-dimensional FFT operation method and system based on dynamic reconfigurable processor architecture
The two-dimensional FFT operation method on a dynamically reconfigurable processor architecture addresses the limitations of existing methods by reducing memory access conflicts and enhancing efficiency, enabling flexible and efficient processing of large-point FFT operations.
Patent Information
- Application Number
- CN202411208976.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2024-12-10
AI Technical Summary
Existing FFT operation methods fail to simultaneously meet the requirements of computing power, energy efficiency, area efficiency, real-time performance, and flexibility, particularly in large-point FFT operations.
A two-dimensional FFT operation method and system based on a dynamically reconfigurable processor architecture, utilizing off-chip and on-chip memories, shared memory, and a controller to perform group and reverse group processing, reducing memory access conflicts and storage demands while enhancing computational efficiency.
The solution effectively reduces memory access conflicts, improves computational efficiency, and meets high precision and real-time performance requirements, with scalability and flexibility, allowing processing of larger point FFT operations without altering hardware modules.
Smart Images
Figure CN119106225A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of reconfigurable processors, and in particular to a two-dimensional FFT operation method and system based on a dynamically reconfigurable processor architecture. Background Art
[0002] This section is intended to provide a background or context to the embodiments of the invention recited in the claims. No admission is made that the description herein is prior art by inclusion in this section.
[0003] Fast Fourier transform (FFT) provides an efficient method to convert signals from the time domain to the frequency domain and perform various frequency domain operations. It plays an important role in signal processing, image processing, scientific computing and other fields. With the continuous emergence of new application scenarios and requirements, the number of points that need to be processed by FFT operations continues to increase, which easily leads to memory access conflicts and reduces the efficiency of operations. At the same time, current applications have put forward higher requirements for the energy efficiency and flexibility of operations. Therefore, it is of great significance to realize large-point, fast, energy-efficient and flexible FFT operations.
[0004] The existing FFT operation implementation methods are mainly divided into two categories:
[0005] (1) Software-based approach
[0006] Software-based methods are generally implemented on general-purpose platforms such as CPUs. Although such methods have been highly optimized on the target platform, their computational efficiency still cannot meet the requirements due to limitations on inherent memory access patterns.
[0007] (2) Hardware-based methods
[0008] The hardware-based method is generally implemented by ASIC, DSP or FPGA. Since the storage architecture can be specially designed, the hardware-based method can achieve higher performance. The ASIC-based implementation method has high energy efficiency and area efficiency, but the hardware function cannot be changed after tape-out and has no flexibility; the DSP-based implementation method has certain programmability (i.e. flexibility), but it still cannot meet the processing power and flexibility requirements of some applications. The FPGA-based implementation method is highly flexible, but at the same time the energy consumption is too high.
[0009] Therefore, there is currently a lack of a solution that can simultaneously meet multiple requirements of computing power, energy efficiency, area efficiency, real-time performance, and flexibility. Summary of the invention
[0010] The embodiment of the present invention provides a two-dimensional FFT operation method based on a dynamically reconfigurable processor architecture, which can simultaneously meet multiple requirements such as computing power, energy efficiency, area efficiency, real-time performance, and flexibility. The method includes:
[0011] The N-point raw data, the rotation factors and the configuration package required for the two-dimensional FFT operation are stored in the off-chip memory;
[0012] Split the N-point original data into N1 groups, each group contains N2 original data;
[0013] The original data of each group is group processed sequentially to obtain N operation results, wherein the group processing step includes: transferring the original data of each group and the configuration package of N2-point FFT operation from the off-chip memory to the on-chip memory, and transferring the N2 rotation factors from the off-chip memory to the shared memory; performing N2-point FFT operation based on the configuration package of N2-point FFT operation, the original data in the on-chip memory, and the N2 rotation factors through the controller and the processing unit array, and writing the operation results to the on-chip memory;
[0014] Repeat the reverse group processing N3 times to obtain N final operation results, wherein the reverse group processing step includes: taking N3 groups of N1 operation results from the on-chip memory, and moving the configuration package of the N1-point FFT from the off-chip memory to the on-chip memory; performing an N1-point FFT operation based on the configuration package of the N1-point FFT operation, the operation results in the on-chip memory, and the rotation factors in the shared memory through the controller and the processing unit array, and writing the final operation result to the on-chip memory;
[0015] Move the N final calculation results from the on-chip memory to the off-chip memory.
[0016] The embodiment of the present invention further provides a two-dimensional FFT operation system based on a dynamically reconfigurable processor architecture, which can simultaneously meet multiple requirements such as computing power, energy efficiency, area efficiency, real-time performance, and flexibility. The system includes:
[0017] Off-chip memory and dynamically reconfigurable processors;
[0018] The dynamically reconfigurable processor includes a controller, a processing unit array, a shared memory and an on-chip memory;
[0019] The off-chip memory is used to store N-point original data, rotation factors and configuration packages required for two-dimensional FFT operation;
[0020] The on-chip memory is used to store the original data of each group and the configuration package of the N2-point FFT operation transferred from the off-chip memory when group processing is performed on the original data of each group, wherein the N-point original data is split into N1 groups, each group containing N2 original data;
[0021] The shared memory is used to store N2 rotation factors transferred from the off-chip memory when performing group processing on the original data of each group;
[0022] The controller is used to: when performing group processing on the original data of each group, control the processing unit array to perform N2-point FFT operation based on the configuration package of N2-point FFT operation, the original data in the on-chip memory, and N2 rotation factors, and write the operation result to the on-chip memory;
[0023] The on-chip memory is also used to store the N1-point FFT configuration package transferred from the off-chip memory each time the reverse group processing is performed, wherein the reverse group processing needs to be repeated N2 times;
[0024] The controller is also used to: perform an N1-point FFT operation based on the configuration package of the N1-point FFT operation, the operation result in the on-chip memory, and the rotation factor in the shared memory each time the reverse group processing is performed, and write the final operation result into the on-chip memory;
[0025] The off-chip memory is also used to store N final calculation results transferred from the on-chip memory.
[0026] In an embodiment of the present invention, N-point original data, rotation factors and configuration packages required for two-dimensional FFT operation are stored in an off-chip memory; the N-point original data are split into N1 groups, each group containing N2 original data; the original data of each group are group processed in sequence to obtain N operation results, and the group processing step includes: transferring the original data of each group and the configuration package of N2-point FFT operation from the off-chip memory to the on-chip memory, and transferring the N2 rotation factors from the off-chip memory to the shared memory; through a controller and a processing unit array, based on the configuration package of N2-point FFT operation, the original data in the on-chip memory, and the N2 rotation factors, the configuration package of N2-point FFT operation is processed. The rotation factors are subjected to N2-point FFT operations, and the operation results are written to the on-chip memory; the reverse group processing is repeated N3 times to obtain N final operation results, and the reverse group processing step includes: taking N3 groups of N1 operation results from the on-chip memory, and moving the configuration package of the N1-point FFT from the off-chip memory to the on-chip memory; through the controller and the processing unit array, an N1-point FFT operation is performed based on the configuration package of the N1-point FFT operation, the operation results in the on-chip memory, and the rotation factors in the shared memory, and the final operation results are written to the on-chip memory; and the N final operation results are moved from the on-chip memory to the off-chip memory. Compared with the prior art solutions, the solution proposed in the embodiment of the present invention is based on a dynamically reconfigurable processor architecture, and realizes two-dimensional FFT operations through group processing and reverse group processing, which can effectively reduce memory access conflicts and reduce the demand for storage space; at the same time, it can improve the computational efficiency of FFT operations, and especially meet the application requirements of high precision and strong real-time performance; in addition, by simply increasing the capacity of the shared memory, FFT operations with a larger number of points can be processed without changing other hardware modules, and the reconfigurable processor can also be configured to complete other operations or functions, with strong scalability, good flexibility, and high energy efficiency and area efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:
[0028] Figure 1 It is a flow chart of a two-dimensional FFT operation method based on a dynamically reconfigurable processor architecture in an embodiment of the present invention;
[0029] Figure 2 A schematic diagram of a two-dimensional FFT operation system based on a dynamically reconfigurable processor architecture in an embodiment of the present invention;
[0030] Figure 3A detailed schematic diagram of a two-dimensional FFT operation system based on a dynamically reconfigurable processor architecture in an embodiment of the present invention;
[0031] Figure 4 A flow chart of group processing in an embodiment of the present invention;
[0032] Figure 5 Flow chart of reverse group processing in an embodiment of the present invention. DETAILED DESCRIPTION
[0033] To make the purpose, technical solution and advantages of the embodiments of the present invention more clear, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Here, the exemplary embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.
[0034] First, the terms involved in the embodiments of the present invention are explained.
[0035] ASIC, application specific integrated circuit, application specific integrated circuit;
[0036] CGRA, coarse-grained reconfigurable array, coarse-grained reconfigurable array;
[0037] CPU, central processing unit, central processing unit;
[0038] DSP,digital signal processor,digital signal processor;
[0039] FFT, fast Fourier transform, fast Fourier transform;
[0040] FPGA, field programmable gate array, field programmable gate array.
[0041] Because the existing technology cannot meet multiple requirements of computing power, energy efficiency, area efficiency, real-time performance, and flexibility at the same time. To solve this problem, the present invention implements FFT operations based on the dynamically reconfigurable processor architecture CGRA. The CGRA tool chain uses high-level languages (such as C or C++) to shorten the development cycle. The reconfigurable unit provides CGRA with multi-level flexibility and parallelism, which can realize dynamic reconstruction of functions and interconnections. In addition, CGRA is superior to fine-grained FPGAs in terms of energy and area efficiency.
[0042] Figure 1The flowchart of the two-dimensional FFT operation method based on the dynamically reconfigurable processor architecture in the embodiment of the present invention includes:
[0043] Step 101, storing N-point original data, rotation factors and configuration packages required for two-dimensional FFT operation in an off-chip memory;
[0044] Step 102, splitting the N point original data into N1 groups, each group containing N2 original data;
[0045] Step 103, sequentially performing group processing on the original data of each group to obtain N operation results, wherein the group processing step includes: transferring the original data of each group and the configuration package of the N2-point FFT operation from the off-chip memory to the on-chip memory, and transferring the N2 rotation factors from the off-chip memory to the shared memory; performing N2-point FFT operation based on the configuration package of the N2-point FFT operation, the original data in the on-chip memory, and the N2 rotation factors through the controller and the processing unit array, and writing the operation results to the on-chip memory;
[0046] Step 104, repeating N3 reverse group processing to obtain N final operation results, wherein the reverse group processing step includes: taking N3 groups of N1 operation results from the on-chip memory, and moving the configuration package of the N1-point FFT from the off-chip memory to the on-chip memory; performing an N1-point FFT operation based on the configuration package of the N1-point FFT operation, the operation results in the on-chip memory, and the rotation factors in the shared memory through the controller and the processing unit array, and writing the final operation result to the on-chip memory;
[0047] Step 105, moving the N final operation results from the on-chip memory to the off-chip memory.
[0048] The solution proposed in the embodiment of the present invention is based on a dynamically reconfigurable processor architecture. Through group processing and reverse group processing, two-dimensional FFT operations are implemented, which can effectively reduce memory access conflicts and reduce the demand for storage space. At the same time, the computational efficiency of FFT operations can be improved, and in particular, the application requirements of high precision and strong real-time performance can be met. In addition, by simply increasing the capacity of the shared memory, FFT operations with a larger number of points can be processed without changing other hardware modules. The reconfigurable processor can also be configured to complete other operations or functions, with strong scalability, good flexibility, and high energy efficiency and area efficiency.
[0049] In one embodiment, the off-chip memory includes a first off-chip memory and a second off-chip memory;
[0050] The N-point raw data, the rotation factors and configuration packages required for the two-dimensional FFT operation are stored in the off-chip memory, including:
[0051] storing the original data in a first off-chip memory;
[0052] Generate the rotation factors and configuration packets required for the two-dimensional FFT operation and store them in the second off-chip memory.
[0053] In one embodiment, the on-chip memory includes a first on-chip memory and a second on-chip memory;
[0054] Move the original data of each group and the configuration package of the N2-point FFT operation from the off-chip memory to the on-chip memory, and move the N2 rotation factors from the off-chip memory to the shared memory, including:
[0055] Moving the original data of each group from the first off-chip memory to the first on-chip memory;
[0056] Move the N2 rotation factors from the second off-chip memory to the second on-chip memory, and then to the shared memory;
[0057] Moving the configuration package of the N2-point FFT operation from the second off-chip memory to the second on-chip memory;
[0058] Move the N1-point FFT configuration package from the off-chip memory to the on-chip memory, including:
[0059] The configuration package of the N1-point FFT operation is moved from the second off-chip memory to the second on-chip memory.
[0060] In one embodiment, the controller and the processing unit array perform N2-point FFT operations based on the configuration package of the N2-point FFT operation, the original data in the on-chip memory, and the rotation factors in the shared memory, and write the operation results to the on-chip memory, including:
[0061] Parsing the configuration package through the controller to obtain configuration information, and configuring the processing unit array based on the configuration information;
[0062] Through the processing unit array, the original data is obtained from the first on-chip memory, the rotation factors are obtained from the shared memory, N2-point FFT operation is performed, the intermediate results in the operation process are stored in the shared memory, and the operation results after the operation are completed are written to the first on-chip memory.
[0063] In one embodiment, a controller and a processing unit array perform an N1-point FFT operation based on a configuration package of an N1-point FFT operation, read the operation result in an on-chip memory, and the rotation factor in a shared memory, and write the final operation result to the on-chip memory, including:
[0064] The controller parses the configuration package of the N1-point FFT operation to obtain configuration information, and configures the processing unit array based on the configuration information;
[0065] Through the processing unit array, the operation result is obtained from the first on-chip memory, the rotation factor is obtained from the shared memory, an N1-point FFT operation is performed, the intermediate results in the operation process are stored in the shared memory, and the final operation result after the operation is completed is written to the first on-chip memory.
[0066] In one embodiment, the shared memory is composed of 64 memory banks, each of which has a depth of N3;
[0067] The N2 rotation factors are moved from the second off-chip memory to the second on-chip memory, and then to the shared memory, including:
[0068] Reading rotation factors in N3 consecutive addresses from the second on-chip memory each time to form a group of rotation factors;
[0069] The i-th group of N3 rotation factors are sequentially placed into the first N3 addresses with a depth of i-1 in the storage body of the shared memory;
[0070] Get the twiddle factors from shared memory, including:
[0071] N3 data are read from the shared memory one by one until the reading of N2 rotation factors is completed.
[0072] Figure 2 FIG. 1 is a schematic diagram of a two-dimensional FFT operation system based on a dynamically reconfigurable processor architecture in an embodiment of the present invention. Figure 2 , the system comprising:
[0073] Off-chip memory and dynamically reconfigurable processors;
[0074] The dynamically reconfigurable processor includes a controller, a processing unit array, a shared memory and an on-chip memory;
[0075] The off-chip memory is used to store N-point original data, rotation factors and configuration packages required for two-dimensional FFT operation;
[0076] The on-chip memory is used to store the original data of each group and the configuration package of the N2-point FFT operation transferred from the off-chip memory when group processing is performed on the original data of each group, wherein the N-point original data is split into N1 groups, each group containing N2 original data;
[0077] The shared memory is used to store N2 rotation factors transferred from the off-chip memory when performing group processing on the original data of each group;
[0078] The controller is used to: when performing group processing on the original data of each group, control the processing unit array to perform N2-point FFT operation based on the configuration package of N2-point FFT operation, the original data in the on-chip memory, and N2 rotation factors, and write the operation result to the on-chip memory;
[0079] The on-chip memory is also used to store the N1-point FFT configuration package transferred from the off-chip memory each time the reverse group processing is performed, wherein the reverse group processing needs to be repeated N2 times;
[0080] The controller is also used to: perform an N1-point FFT operation based on the configuration package of the N1-point FFT operation, the operation result in the on-chip memory, and the rotation factor in the shared memory each time the reverse group processing is performed, and write the final operation result into the on-chip memory;
[0081] The off-chip memory is also used to store N final calculation results transferred from the on-chip memory.
[0082] Figure 3 FIG. 1 is a detailed schematic diagram of a two-dimensional FFT operation system based on a dynamically reconfigurable processor architecture in an embodiment of the present invention. Figure 3 , the off-chip memory includes a first off-chip memory and a second off-chip memory;
[0083] The first off-chip memory is used for: storing original data;
[0084] The second off-chip memory is used for: rotation factors and configuration packets required for two-dimensional FFT operations.
[0085] In one embodiment, the on-chip memory includes a first on-chip memory and a second on-chip memory;
[0086] The first on-chip memory is used to store the original data of each group transferred from the first off-chip memory;
[0087] The second on-chip memory is used to store the configuration package of the N2-point FFT operation and the configuration package of the N1-point FFT operation transferred from the second off-chip memory;
[0088] The shared memory is used to store the N2 rotation factors transferred from the second off-chip memory.
[0089] In one embodiment, the second on-chip memory is used to: store N2 rotation factors transferred from the second off-chip memory;
[0090] The shared memory is used to store the N2 rotation factors transferred from the second on-chip memory.
[0091] In the embodiment of the present invention, the processing unit array is composed of m×n processing units, which are responsible for performing FFT operations. The controller parses the configuration package and writes the configuration information into the configuration memory in each processing unit. The processing unit performs corresponding operations under the dual drive of the data flow and the configuration flow. Each reconfigurable processing unit and the interconnection between the reconfigurable processing units can be configured separately.
[0092] Shared memory is a group of memories (multiple storage bodies), which has two main functions: one is to store the rotation factors (FFT operation requires the data to be processed + rotation factors), and the other is to store the intermediate data generated during the FFT operation. By increasing the capacity of shared memory, the accelerator can handle FFT operations with a larger number of points (reflecting scalability).
[0093] In order to improve data access efficiency, the embodiment of the present invention designs a hierarchical data storage system, involving three levels: system, processing unit array, and processing unit. The corresponding physical units that provide data access are shared memory, global registers, and local registers. The main function of the global register is to store data and parameters pointing to multiple processing units. The local register is mainly used to save the intermediate data inside the processing unit and is only accessible to the current processing unit.
[0094] The controller is responsible for controlling the operation of the entire system, including the configuration of the control processing unit array and the data movement between modules. The on-chip memory is used to store programs, configuration packages and data.
[0095] The off-chip memory is used to store raw data / data to be processed and configuration packages required for the operation of the dynamically reconfigurable processor.
[0096] In many applications, large-point FFT operations are required. Direct one-dimensional FFT operations require a lot of storage space. Splitting large-point FFT operations into two-dimensional FFT operations can greatly reduce the demand for storage space. Take N-point (such as N = 32768) point FFT as an example, split it into N1-point FFT and N2-point FFT (such as N1 = 32, N2 = 1024), N = N1 × N2. Divide the original data (N-point original data) into N1 groups, each group of N2 data, the overall operation process is to take out N2 data each time to perform N2-point FFT operations, a total of N1 times, called group processing; then perform N1-point FFT, each time you can take N3 (can take 32) groups of N1 data and perform N3 groups of N1 point FFTs at the same time, a total of N3 times, called reverse group processing, to get the final operation result. The following describes this process in detail.
[0097] The first step is to store the original data in the first off-chip memory; at the same time, generate the rotation factors and configuration packages required for the two-dimensional FFT operation and store them in the second off-chip memory.
[0098] Step 2: Perform N1 groups of N2 point FFT (group processing). Figure 4 This is a flow chart for group processing in an embodiment of the present invention. The N-point original data is split into N1 groups, each group has N2 data, and one group of original data is taken each time and moved from the first off-chip memory to the first on-chip memory; at the same time, the N2 rotation factors are moved from the second off-chip memory to the second on-chip memory, and then to the shared memory. Considering the simultaneous read and write conflicts, the address of the rotation factors stored in the shared memory needs to be swapped between storage bodies; at the same time, the configuration package of the N2-point FFT is moved from the second off-chip memory to the second on-chip memory. At this point, the data preparation work is completed. Then, the controller parses the configuration package and configures the processing unit array. After all data and configuration information are prepared, the processing unit array is started. The processing unit array obtains the original data from the first on-chip memory, obtains the rotation factors from the shared memory, and performs N2-point FFT operations. The intermediate results in the calculation process are stored in the shared memory. After the calculation is completed, the results are written to the first on-chip memory. At this point, the first group of N2-point FFT operations is completed, and then the second group of N2 data is taken from the first off-chip memory, and the process is repeated to complete the second group of N2-point FFT operations; this process is repeated until all N1 groups of N2-point FFT operations are completed, and all N operation results are stored in the first on-chip memory.
[0099] Step 3: Perform N2 groups of N1-point FFT (reverse group processing). Figure 5 This is a flow chart for reverse group processing in an embodiment of the present invention. The calculation result after the second step is stored in the first on-chip memory. The processing unit array can perform 1024-point FFT operations, so N3 (here 32 can be taken) groups of N1 data are taken each time; at the same time, the configuration package of the N1-point FFT is moved from the second off-chip memory to the second on-chip memory. At this point, the data preparation work is completed. Then, the controller parses the configuration package and configures the processing unit array. After all data and configuration information are prepared, the processing unit array is started. The processing unit array obtains the original data from the first on-chip memory, obtains the rotation factor from the shared memory, and performs N1-point FFT operations. The intermediate results in the calculation process are stored in the shared memory. After the calculation is completed, the final calculation result is written to the first on-chip memory. At this point, the first 32 groups of N1-point FFT operations are completed, and then 32 groups of N1 data are taken from the first on-chip memory, and the process is repeated to complete the second 32 groups of N1-point FFT operations; this process is repeated until all 32 32 groups of N1-point FFT operations are completed, and all N final operation results are stored in the first on-chip memory to obtain the final operation result of the final N-point FFT.
[0100] Step 4: Move the final calculation result of the N-point FFT from the first on-chip memory to the first off-chip memory.
[0101] In the second step above, it is mentioned that "considering the conflict of simultaneous reading and writing, the address of the rotation factor stored in the shared memory needs to be swapped between storage bodies (i.e., banks)", which is explained here. In this embodiment, the shared memory can be designed to be composed of 64 storage bodies, each of which has a depth of 32 (i.e., it can store 32 data, and the value of N3 in the embodiment of the present invention). When N2 rotation factors are moved from the second on-chip memory to the shared memory, the specific operation is to read the data in 32 consecutive addresses from the second on-chip memory each time, and a total of 32 times are required to be read, and each 32 data is called a group, and the first group of 32 data is sequentially placed in the address with a depth of 0 in the first 32 storage bodies of the shared memory, and the second group of 32 data is sequentially placed in the address with a depth of 1 in the first 32 storage bodies of the shared memory, and so on, the i-th group of 32 data is sequentially placed in the address with a depth of i-1 in the first 32 storage bodies of the shared memory, until the last group of 32 data is sequentially placed in the address with a depth of 31 in the first 32 storage bodies of the shared memory. When the processing unit array performs an N2-point FFT operation, N2 rotation factors are read from the shared memory, that is, the N2 data stored in the shared memory. The reading method is to read one memory bank at a time, that is, to read 32 data from memory bank 0, and then to read 32 data from memory bank 1, ..., until 32 data are read from memory bank 31, and the reading of the N2 rotation factors is completed.
[0102] In summary, in the method and system proposed in the embodiment of the present invention, based on the dynamically reconfigurable processor architecture, two-dimensional FFT operations are implemented through group processing and reverse group processing, which can effectively reduce memory access conflicts and reduce the demand for storage space; at the same time, the computational efficiency of FFT operations can be improved, especially to meet the application requirements of high precision and strong real-time performance; in addition, by simply increasing the capacity of the shared memory, FFT operations with a larger number of points can be processed without changing other hardware modules, and the reconfigurable processor can also be configured to complete other operations or functions, with strong scalability, good flexibility, and high energy efficiency and area efficiency.
[0103] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A two-dimensional FFT calculation method based on a dynamically reconfigurable processor architecture, characterized in that: include: The N-point raw data, the rotation factors and the configuration package required for the two-dimensional FFT operation are stored in the off-chip memory; Split the N-point original data into N1 groups, each group contains N2 original data; The original data of each group is group processed sequentially to obtain N operation results, wherein the group processing step includes: transferring the original data of each group and the configuration package of N2-point FFT operation from the off-chip memory to the on-chip memory, and transferring the N2 rotation factors from the off-chip memory to the shared memory; performing N2-point FFT operation based on the configuration package of N2-point FFT operation, the original data in the on-chip memory, and the N2 rotation factors through the controller and the processing unit array, and writing the operation results to the on-chip memory; Repeat the reverse group processing N3 times to obtain N final operation results, wherein the reverse group processing step includes: taking N3 groups of N1 operation results from the on-chip memory, and moving the configuration package of the N1-point FFT from the off-chip memory to the on-chip memory; performing an N1-point FFT operation based on the configuration package of the N1-point FFT operation, the operation results in the on-chip memory, and the rotation factors in the shared memory through the controller and the processing unit array, and writing the final operation result to the on-chip memory; Move the N final calculation results from the on-chip memory to the off-chip memory.
2. The method according to claim 1, characterized in that The off-chip memory includes a first off-chip memory and a second off-chip memory; The N-point raw data, the rotation factors and configuration packages required for the two-dimensional FFT operation are stored in the off-chip memory, including: storing the original data in a first off-chip memory; Generate the rotation factors and configuration packets required for the two-dimensional FFT operation and store them in the second off-chip memory.
3. The method according to claim 2, characterized in that The on-chip memory includes a first on-chip memory and a second on-chip memory; Move the original data of each group and the configuration package of the N2-point FFT operation from the off-chip memory to the on-chip memory, and move the N2 rotation factors from the off-chip memory to the shared memory, including: Moving the original data of each group from the first off-chip memory to the first on-chip memory; Move the N2 rotation factors from the second off-chip memory to the second on-chip memory, and then to the shared memory; Moving the configuration package of the N2-point FFT operation from the second off-chip memory to the second on-chip memory; Move the N1-point FFT configuration package from the off-chip memory to the on-chip memory, including: The configuration package of the N1-point FFT operation is moved from the second off-chip memory to the second on-chip memory.
4. The method according to claim 3, characterized in that Through the controller and the processing unit array, based on the configuration package of the N2-point FFT operation, the original data in the on-chip memory and the rotation factors in the shared memory perform the N2-point FFT operation, and write the operation result to the on-chip memory, including: Parsing the configuration package through the controller to obtain configuration information, and configuring the processing unit array based on the configuration information; Through the processing unit array, the original data is obtained from the first on-chip memory, the rotation factors are obtained from the shared memory, an N2-point FFT operation is performed, the intermediate results in the operation process are stored in the shared memory, and the operation results after the operation are completed are written to the first on-chip memory.
5. The method according to claim 4, characterized in that Through the controller and the processing unit array, based on the configuration package of the N1-point FFT operation, the operation result in the on-chip memory and the rotation factor in the shared memory are read to perform an N1-point FFT operation, and the final operation result is written to the on-chip memory, including: The controller parses the configuration package of the N1-point FFT operation to obtain configuration information, and configures the processing unit array based on the configuration information; Through the processing unit array, the operation result is obtained from the first on-chip memory, the rotation factor is obtained from the shared memory, an N1-point FFT operation is performed, the intermediate results in the operation process are stored in the shared memory, and the final operation result after the operation is completed is written to the first on-chip memory.
6. The method according to claim 3, characterized in that The shared memory consists of 64 memory banks, each with a depth of N3; The N2 rotation factors are moved from the second off-chip memory to the second on-chip memory, and then to the shared memory, including: Reading rotation factors in N3 consecutive addresses from the second on-chip memory each time to form a group of rotation factors; The i-th group of N3 rotation factors are sequentially placed into the first N3 addresses with a depth of i-1 in the storage body of the shared memory; Get the twiddle factors from shared memory, including: N3 data are read from the shared memory one by one until the reading of N2 rotation factors is completed.
7. A two-dimensional FFT operation system based on a dynamically reconfigurable processor architecture, characterized in that: include: Off-chip memory and dynamically reconfigurable processors; The dynamically reconfigurable processor includes a controller, a processing unit array, a shared memory and an on-chip memory; The off-chip memory is used to store N-point original data, rotation factors and configuration packages required for two-dimensional FFT operation; The on-chip memory is used to store the original data of each group and the configuration package of the N2-point FFT operation transferred from the off-chip memory when group processing is performed on the original data of each group, wherein the N-point original data is split into N1 groups, each group containing N2 original data; The shared memory is used to store N2 rotation factors transferred from the off-chip memory when group processing is performed on the original data of each group; The controller is used to: when performing group processing on the original data of each group, control the processing unit array to perform N2-point FFT operation based on the configuration package of N2-point FFT operation, the original data in the on-chip memory, and N2 rotation factors, and write the operation result to the on-chip memory; The on-chip memory is also used to store the N1-point FFT configuration package transferred from the off-chip memory each time the reverse group processing is performed, wherein the reverse group processing needs to be repeated N2 times; The controller is also used to: perform an N1-point FFT operation based on the configuration package of the N1-point FFT operation, the operation result in the on-chip memory, and the rotation factor in the shared memory each time the reverse group processing is performed, and write the final operation result into the on-chip memory; The off-chip memory is also used to store N final calculation results transferred from the on-chip memory.
8. The system according to claim 7, characterized in that The off-chip memory includes a first off-chip memory and a second off-chip memory; The first off-chip memory is used for: storing original data; The second off-chip memory is used for: rotation factors and configuration packets required for two-dimensional FFT operations.
9. The system according to claim 8, characterized in that The on-chip memory includes a first on-chip memory and a second on-chip memory; The first on-chip memory is used to store the original data of each group transferred from the first off-chip memory; The second on-chip memory is used to store the configuration package of the N2-point FFT operation and the configuration package of the N1-point FFT operation transferred from the second off-chip memory; The shared memory is used to store the N2 rotation factors transferred from the second off-chip memory.
10. The system according to claim 9, characterized in that The second on-chip memory is used to store N2 rotation factors transferred from the second off-chip memory; The shared memory is used to store the N2 rotation factors transferred from the second on-chip memory.